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/* vfpArmLib.h - Arm Version of Vector Floating-Point Include File */
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/*
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* Copyright (c) 2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01a,07may13,c_t VFPv4 SP written based on standard version
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*/
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#ifndef __INCvfpArmLibSph
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#define __INCvfpArmLibSph
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* for cortex M the following register are memory mapped and the addresses
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* are architectural defined.
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*/
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/* Coprocessor Access Control Register, CPACR, enable CP10 & CP11 for VFP */
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#define CPACR (0xE000ED88)
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#define CPACR_CP_FULL(x) (3<<(2*(x))) /* 0b11 : Full access for this cp */
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/* Floating-Point Context Control Register, FPCCR */
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#define FPCCR (0xE000EF34)
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#define FPCCR_ASPEN (1<<31) /* enable auto FP context stacking */
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#define FPCCR_LSPEN (1<<30) /* enable lazy FP context stacking */
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#define FPCCR_MONRDY (1<<8)
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#define FPCCR_BFRDY (1<<6)
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#define FPCCR_MMRDY (1<<5)
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#define FPCCR_HFRDY (1<<4)
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#define FPCCR_THREAD (1<<3) /* allocated FP stack in thread */
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#define FPCCR_USER (1<<1) /* allocated FP stack in priviledged */
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#define FPCCR_LSPACT (1<<0) /* lazy stacking is active */
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/* Floating-Point Context Address Register, FPCAR */
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/* this register contains the FP context address in the exception stack */
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#define FPCAR (0xE000EF38)
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/* Floating-Point Default Status Control Register, FPDSCR */
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/*
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* set the initial value of FPSCR, however we can set it manually to FPSCR
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* when creating the VFP task, so let it as is at this time.
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*/
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#define FPDSCR (0xE000EF3C)
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#define FPDSCR_AHP (1<<26)
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#define FPDSCR_DN (1<<25)
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#define FPDSCR_FZ (1<<24)
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#define FPDSCR_RMODE 0x00C00000
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#define FPDSCR_RN 0x00000000 /* round to nearest */
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#define FPDSCR_RP 0x00400000 /* round toward plus infinity */
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#define FPDSCR_RM 0x00800000 /* round toward minus infinity */
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#define FPDSCR_RZ 0x00C00000 /* round toward zero */
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/* Media and FP Feature Register 0, MVFR0 & Register 1, MVFR1*/
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/* these read only registers are using to detect feature that supported */
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#define MVFR0 (0xE000EF40)
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#define MVFR0_SP_MSK (0x000000F0) /* bit 4~7 = 0x2, support sp */
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#define MVFR0_SP_EN (0x20) /* bit 4~7 = 0x2, support sp */
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#define MVFR1 (0xE000EF44)
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/* FPSCR (Floating Status and Control Register) bit definitions for VFPv4SP */
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/*
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* At the time of implementation bits 27, 21-8, and 6-5,
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* are described as reserved, one must employ
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* read/modify/write techniques when handling the FPSCR in order
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* to ensure that these bits are not modified...
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*/
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#define FPSCR_N_BIT (1<<31) /* less than result */
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#define FPSCR_Z_BIT (1<<30) /* equal result */
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#define FPSCR_C_BIT (1<<29) /* equal, greater than, or unordered result */
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#define FPSCR_V_BIT (1<<28) /* unordered result */
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#define FPSCR_AHP (1<<26)
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#define FPSCR_DN_BIT (1<<25) /* Default NaN mode control */
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#define FPSCR_DN_MSK FPSCR_DN_BIT
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#define FPSCR_DN_ENABLE FPSCR_DN_BIT
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#define FPSCR_DN_DISABLE 0x00000000
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#define FPSCR_FZ_BIT (1<<24) /* flush to zero mode control */
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#define FPSCR_FZ_MSK FPSCR_FZ_BIT
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#define FPSCR_FZ_ENABLE FPSCR_FZ_BIT
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#define FPSCR_FZ_DISABLE 0x00000000
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/* Cumulative Exception Bits */
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#define FPSCR_IDC_BIT (1<<7) /* Input Subnormal */
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#define FPSCR_IXC_BIT (1<<4) /* Inexact */
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#define FPSCR_UFC_BIT (1<<3) /* Underflow */
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#define FPSCR_OFC_BIT (1<<2) /* Overflow */
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#define FPSCR_DZC_BIT (1<<1) /* Division By Zero */
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#define FPSCR_IOC_BIT (1<<0) /* Invalid Operation */
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/* Round Mode Control Bits */
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#define FPSCR_RMODES_MSK 0x00C00000 /* round mode */
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#define FPSCR_RN 0x00000000 /* round to nearest */
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#define FPSCR_RP 0x00400000 /* round toward plus infinity */
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#define FPSCR_RM 0x00800000 /* round toward minus infinity */
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#define FPSCR_RZ 0x00C00000 /* round toward zero */
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#ifdef _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO
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#define FPSCR_INIT FPSCR_DN_MSK
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#else /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
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#define FPSCR_INIT (FPSCR_DN_MSK | FPSCR_FZ_BIT)
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#endif /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
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#define VFPREG_SET VFP_CONTEXT
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#define _VFP_ALIGN_SIZE 8 /* Not sure if this is needed */
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/* vfpv4 sp only support D16/S32. */
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#define VFP_DGPR_NUM 16 /* 16-double precision general purpose */
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#define VFP_SGPR_NUM 32 /* 32-single precision general purpose */
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/* FP_CONTEXT structure offsets */
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#define VFP_FPSCR 0x00
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#define VFP_PAD -
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#define VFP_GPR 0x08 /* OFFSET(FP_CONTEXT, vfp_gpr[0]) */
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#define VFP_GPR_OFFSET(n) (VFP_GPR + (n)*4) /* vfp_gpr[n]) */
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#ifndef _ASMLANGUAGE
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/* standard interface to fp lib. */
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/* vfpv4 sp context is different with standard vfp. */
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typedef struct vfpContext /* VFP Context */
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{
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UINT32 fpscr; /* status and control register */
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UINT32 pad; /* pad to match 8 byte alignment */
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UINT32 vfp_gpr[VFP_SGPR_NUM]; /* general purpose registers */
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/* TOTAL */
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} WRS_PACK_ALIGN(_VFP_ALIGN_SIZE) VFP_CONTEXT;
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/* function declarations */
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IMPORT void vfpArchInit (void);
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IMPORT void vfpArchTaskCreateInit (VFP_CONTEXT *pDspContext);
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IMPORT void vfpSave (VFP_CONTEXT *);
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IMPORT void vfpRestore (VFP_CONTEXT *);
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IMPORT STATUS vfpProbe (void);
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IMPORT STATUS vfpEnable (void);
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IMPORT STATUS vfpDisable (void);
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IMPORT VFP_CONTEXT * vfpCtxCreate (int);
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IMPORT STATUS vfpCtxDelete (VFP_CONTEXT *);
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IMPORT void vfpCtxShow (VFP_CONTEXT *);
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void vfpRegsToCtx (VFPREG_SET *, VFP_CONTEXT *);
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void vfpCtxToRegs (VFP_CONTEXT *, VFPREG_SET *);
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#ifdef _WRS_HW_VFP_SUPPORT
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IMPORT int vfpIsEnabled (void);
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IMPORT int vfpHasException (void);
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IMPORT STATUS vfpProbeSup (void);
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IMPORT UINT32 vfpFpSidGet (void);
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IMPORT UINT32 vfpFpScrGet (void);
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IMPORT void vfpFpScrSet (UINT32);
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#endif
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvfpArmLibSph */
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