original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,284 @@
|
||||
|
||||
/* arm-m.h - ARM CPU registers and flags for ARM-M architecture */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012-2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01f,01aug13,yjw add cache support
|
||||
01e,03aug12,jdw Add boot macro _WRS_ARM_BOOT_THUMB2
|
||||
01d,06jun12,j_b add core control registers and initialization values
|
||||
01c,29may12,j_b add control and configuration registers
|
||||
01b,24may12,m_h Add CPUID address
|
||||
01a,03feb12,jdw Created
|
||||
*/
|
||||
|
||||
#ifndef __INCarm_mh
|
||||
#define __INCarm_mh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
extern int cacheArchAlignSize;
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#undef _CACHE_ALIGN_SIZE
|
||||
#define _CACHE_ALIGN_SIZE cacheArchAlignSize
|
||||
|
||||
/* Define Arch features which are supported by ARM-M */
|
||||
|
||||
/* ARM-M only operates in Thumb2 mode */
|
||||
|
||||
#define ARM_THUMB2 TRUE
|
||||
#define PORTABLE
|
||||
|
||||
/* multiple cache libraries */
|
||||
|
||||
#define _ARCH_MULTIPLE_CACHELIB TRUE
|
||||
|
||||
/* ARMv7-M support exclusive load/store */
|
||||
|
||||
#define ARM_HAS_LDREX_STREX TRUE
|
||||
|
||||
#define ARM_HAS_HALFWORD_INSTRUCTIONS TRUE
|
||||
|
||||
/* MPU is optional on some ARM-M cores */
|
||||
|
||||
#define ARM_HAS_NO_MMU TRUE
|
||||
|
||||
/* ARM-M always boots in Thumb2 mode */
|
||||
|
||||
#define _WRS_ARM_BOOT_THUMB2 TRUE
|
||||
|
||||
#define _WRS_ARCH_HAS_CPU_PWR_MGMT
|
||||
|
||||
/* bits in the PSR */
|
||||
|
||||
#define Q_BIT (1<<27)
|
||||
#define V_BIT (1<<28)
|
||||
#define C_BIT (1<<29)
|
||||
#define Z_BIT (1<<30)
|
||||
#define N_BIT (1<<31)
|
||||
#define T_BIT (1<<24)
|
||||
|
||||
/*
|
||||
* On entry to an exception the processor will use xPSR bit 9
|
||||
* to indicate if the SP has been aligned to an 8-byte boundary
|
||||
*/
|
||||
|
||||
#define PSR_STK_ALIGN (1<<9)
|
||||
|
||||
/* masks for getting bits from PSR */
|
||||
|
||||
#define MASK_EXC_NUM 0x000001FF
|
||||
#define MASK_ICIIT 0x0600FC00
|
||||
#define MASK_GE 0x000F0000
|
||||
#define MASK_T 0x01000000
|
||||
#define MASK_CC 0xF8000000
|
||||
|
||||
/* PRIMASK, FAULTMASK, & BASEMASK fields */
|
||||
|
||||
#define PRIMASK_PM 0x00000001
|
||||
#define FAULTMASK_FM 0x00000001
|
||||
#define MASK_BASEPRI 0x000000FF
|
||||
|
||||
/* Bits in EXC_RETURN */
|
||||
|
||||
#define EXC_RTN_BASE 0xFFFFFFF1
|
||||
#define EXC_RTN_MODE_THREAD 0x00000008
|
||||
#define EXC_RTN_MODE_HANDLER 0x00000000
|
||||
#define EXC_RTN_STACK_PROCESS 0x00000004
|
||||
#define EXC_RTN_STACK_MAIN 0x00000000
|
||||
|
||||
#define MASK_EXC_RTN_MODE 0x00000008
|
||||
#define MASK_EXC_RTN_STACK 0x00000004
|
||||
|
||||
|
||||
/*
|
||||
* System Control Block Registers
|
||||
*/
|
||||
|
||||
|
||||
/* CPU ID Base Register */
|
||||
|
||||
#define CORTEXM_CPUID_BASE_REGISTER (0xE000ED00)
|
||||
|
||||
/* Interrupt Controller Type Register */
|
||||
|
||||
#define CORTEXM_ICTR (0xE000E004)
|
||||
|
||||
#define CORTEXM_ICTR_INTNUM_MASK (0xF) /* # of interrupt lines field */
|
||||
#define CORTEXM_ICTR_INTNUM_MAX (0xF) /* # of interrupt lines field max */
|
||||
|
||||
/* Auxiliary Control Register - usage is implementation-defined/core-specific */
|
||||
|
||||
#define CORTEXM_ACTLR (0xE000E008)
|
||||
|
||||
/* Interrupt Controller State Register */
|
||||
|
||||
#define CORTEXM_ICSR (0xE000ED04)
|
||||
|
||||
/* Vector Table Offset Register */
|
||||
|
||||
#define CORTEXM_VTOR (0xE000ED08)
|
||||
|
||||
#define CORTEXM_VTOR_MASK (0xFFFFFF80) /* reserved bits 6:0 */
|
||||
|
||||
/*
|
||||
* Application Interrupt and Reset Control Register
|
||||
*
|
||||
* Note that the proper access key must be included in a write to this
|
||||
* regsiter or the write is ignored.
|
||||
*/
|
||||
|
||||
#define CORTEXM_AIRCR (0xE000ED0C)
|
||||
|
||||
#define CORTEXM_AIRCR_VECTKEY 0x05FA0000 /* Access Key for writes */
|
||||
#define CORTEXM_AIRCR_VECTKEY_MASK 0xFFFF0000 /* (0xFA05 is the read value) */
|
||||
|
||||
#define CORTEXM_AIRCR_PRIGROUP_SHIFT 8 /* Priority Group */
|
||||
#define CORTEXM_AIRCR_PRIGROUP_MASK (0x7 << CORTEXM_AIRCR_PRIGROUP_SHIFT)
|
||||
|
||||
/* System Control and Register */
|
||||
|
||||
#define CORTEXM_SCR (0xE000ED10)
|
||||
|
||||
/* Configuration and Control Register */
|
||||
|
||||
#define CORTEXM_CCR (0xE000ED14)
|
||||
|
||||
#define CORTEXM_CCR_DIV0TRP (0x00000010) /* divide by zero trap enable */
|
||||
#define CORTEXM_CCR_STKALIGN (0x00000200) /* 8-byte stacking align enable */
|
||||
|
||||
/*
|
||||
* System Handler Priority Level Registers
|
||||
* (aka System Exception Priority Level Registers)
|
||||
*/
|
||||
|
||||
#define CORTEXM_SHPR1 (0xE000ED18) /* Pri lvl for Exceptions 4-7 */
|
||||
#define CORTEXM_SHPR2 (0xE000ED1C) /* Pri lvl for Exceptions 8-11 */
|
||||
#define CORTEXM_SHPR3 (0xE000ED20) /* Pri lvl for Exceptions 12-15 */
|
||||
|
||||
/*
|
||||
* Note: SHPR actually starts with PRI_4. There is no such thing as PRI_0 but
|
||||
* this makes the address calculation easier.
|
||||
*/
|
||||
|
||||
#define CORTEXM_SHPR_PRI_0 (0xE000ED14)
|
||||
#define CORTEXM_SHPR_PRI_15 (0xE000ED23)
|
||||
|
||||
#define CORTEXM_SHPR_PENDSV (CORTEXM_SHPR_PRI_14)
|
||||
#define CORTEXM_SHPR_SYSTICK (CORTEXM_SHPR_PRI_15)
|
||||
|
||||
/* system priority register address, calculated by exception # (= offset) */
|
||||
|
||||
#define CORTEXM_SHPR_PRI_BYTE(n) (CORTEXM_SHPR_PRI_0 + (n))
|
||||
|
||||
/* System Handler Control and State Register */
|
||||
|
||||
#define CORTEXM_SHCSR (0xE000ED24)
|
||||
|
||||
#define CORTEXM_SHCSR_USGFLT_EN (0x00040000) /* Usage Fault Enable bit */
|
||||
#define CORTEXM_SHCSR_BUSFLT_EN (0x00020000) /* Bus Fault Enable bit */
|
||||
#define CORTEXM_SHCSR_MEMFLT_EN (0x00010000) /* Memory Mgt Fault Enable bit */
|
||||
|
||||
#define CORTEXM_SHCSR_SVC_PEND (0x00008000) /* SVCall Pending bit */
|
||||
#define CORTEXM_SHCSR_BUSFLT_PEND (0x00004000) /* Bus Fault Pend bit */
|
||||
#define CORTEXM_SHCSR_MEMFLT_PEND (0x00002000) /* Memory Mgt Pend bit */
|
||||
#define CORTEXM_SHCSR_USGFLT_PEND (0x00001000) /* Usage Fault Pend bit */
|
||||
|
||||
#define CORTEXM_SHCSR_SYSTCK_ACT (0x00000800) /* SysTick Active bit */
|
||||
#define CORTEXM_SHCSR_PENDSV_ACT (0x00000400) /* PendSV Active bit */
|
||||
#define CORTEXM_SHCSR_DBGMON_ACT (0x00000100) /* Debug Monitor Active */
|
||||
#define CORTEXM_SHCSR_SVC_ACT (0x00000080) /* SVCall Active */
|
||||
#define CORTEXM_SHCSR_USGFLT_ACT (0x00000008) /* Usage Fault Active */
|
||||
#define CORTEXM_SHCSR_BUSFLT_ACT (0x00000002) /* Usage Fault Active */
|
||||
#define CORTEXM_SHCSR_MEMFLT_ACT (0x00000001) /* Usage Fault Active */
|
||||
|
||||
/* Debug Exception and Monitor Control Register */
|
||||
|
||||
#define CORTEXM_DEMCR (0xE000EDFC)
|
||||
#define CORTEXM_DEMCR_MON_STEP (0x00040000)
|
||||
#define CORTEXM_DEMCR_MON_PEND (0x00020000)
|
||||
#define CORTEXM_DEMCR_MON_EN (0x00010000)
|
||||
|
||||
/* ROM table for debug */
|
||||
|
||||
#define CORTEXM_ROM_TABLE (0xE00FF000)
|
||||
#define CORTEXM_ROM_TABLE_FPB_OFFSET (0x00000008)
|
||||
#define CORTEXM_FPB_VALID (0xFFF03003)
|
||||
|
||||
/* FlashPatch Control Register */
|
||||
|
||||
#define CORTEXM_FP_CTRL (0xE0002000)
|
||||
#define CORTEXM_FP_CTRL_ENABLE (3)
|
||||
|
||||
/* FlashPatch Comparatorregister */
|
||||
|
||||
#define CORTEXM_FP_COMP0 (0xE0002008)
|
||||
|
||||
/*
|
||||
* Configurable Fault Status Register
|
||||
* This register includes the:
|
||||
* - 8-bit Memory Management Fault Status Register
|
||||
* - 8-bit Bus Fault Status Register; and
|
||||
* - 16-bit Usage Fault Status Register;
|
||||
*/
|
||||
|
||||
#define CORTEXM_CFSR (0xE000ED28)
|
||||
#define CORTEXM_BFSR_SHIFT (8) /* Bus Fault Status bit shift */
|
||||
#define CORTEXM_UFSR_SHIFT (16) /* Usage Fault Status bit shift */
|
||||
|
||||
#define CORTEXM_DFSR (0xE000ED30)
|
||||
#define CORTEXM_HALTED (0x1) /* trace */
|
||||
#define CORTEXM_BKPT (0x2) /* FPB break point */
|
||||
|
||||
#define CORTEXM_MMFSR CORTEXM_CFSR /* Mem Manage Fault Status byte */
|
||||
#define CORTEXM_MMFSR_FARVALID (0x80) /* fault address valid mask */
|
||||
|
||||
#define CORTEXM_BFSR (0xE000ED29) /* Bus Fault Status byte */
|
||||
#define CORTEXM_BFSR_FARVALID (0x80) /* fault address valid mask */
|
||||
|
||||
#define CORTEXM_UFSR (0xE000ED2A) /* Usage Fault Status halfword */
|
||||
|
||||
/* Usage Fault Status fields */
|
||||
|
||||
#define CORTEXM_UFSR_DIV0 (0x00000200) /* Divide by Zero */
|
||||
#define CORTEXM_UFSR_UNALIGN (0x00000100) /* Unaligned Access */
|
||||
#define CORTEXM_UFSR_NOCP (0x00000008) /* Coprocessor Access */
|
||||
#define CORTEXM_UFSR_INVPC (0x00000004) /* Invalid EXC_RETURN */
|
||||
#define CORTEXM_UFSR_INVSTATE (0x00000002) /* Invalid State */
|
||||
#define CORTEXM_UFSR_UNDEF (0x00000001) /* Undefined Instruction */
|
||||
|
||||
/* Hard Fault Status Register */
|
||||
|
||||
#define CORTEXM_HFSR (0xE000ED2C)
|
||||
|
||||
#define CORTEXM_HFSR_FORCED (0x40000000) /* escalated configurable fault */
|
||||
/* (bus/mem mgt/usage fault) */
|
||||
#define CORTEXM_HFSR_CLRALL (0xC0000002) /* clear all Hard faults */
|
||||
|
||||
/* Memory Manage Fault Address Register */
|
||||
|
||||
#define CORTEXM_MMFAR (0xE000ED34)
|
||||
|
||||
/* Bus Fault Address Register */
|
||||
|
||||
#define CORTEXM_BFAR (0xE000ED38)
|
||||
|
||||
/* MPU Control Register */
|
||||
|
||||
#define CORTEXM_MPU_CTRL (0xE000ED94)
|
||||
|
||||
/* Software Trigger Interrupt Register */
|
||||
|
||||
#define CORTEXM_STIR (0xE000EF00)
|
||||
|
||||
#define INVALID_INST (0xFF00FF00) /* invalid opcode */
|
||||
#endif /* __INCarm_mh */
|
||||
@@ -0,0 +1,57 @@
|
||||
/* esfArm-m.h - ARM exception stack frames */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,10may12,j_b fix tabs/spacing
|
||||
01b,03may12,j_b replace "-" in filename include macro
|
||||
01a,03apr12,j_b created from target/h/arch/arm/esfArm.f version 01b
|
||||
*/
|
||||
|
||||
#ifndef __INCesfArm_mh
|
||||
#define __INCesfArm_mh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* The Exception Stack Frame
|
||||
* On ARMv7-M, this is faked by a stub and the pointer
|
||||
* passed back points to the PC and PSR at the end of the
|
||||
* register structure. If that changes, so must this.
|
||||
*
|
||||
* I.E., REG_SET struct & ESF struct 'overlap' on last 4
|
||||
* elements of REG_SET (pc, psr, primask and basepri).
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
INSTR *pc; /* program counter */
|
||||
ULONG psr; /* combined A/I/E PSR */
|
||||
ULONG basepri; /* BASEPRI */
|
||||
ULONG demcr; /* MON_STEP in DEMCR */
|
||||
ULONG primask; /* PRIMASK */
|
||||
ULONG faultmask; /* FAULTMASK */
|
||||
ULONG control; /* CONTROL */
|
||||
UINT32 vecNum; /* exception number */
|
||||
} ESF;
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCesfArm_mh */
|
||||
@@ -0,0 +1,160 @@
|
||||
/* excArmLib-m.h - ARMv7-M exception library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,05sep12,rec add excClearFault prototype
|
||||
01c,24may12,j_b add fault status to EXC_INFO
|
||||
01b,22may12,jdw Add exception vector offset mapping for scopetools
|
||||
01a,14may12,m_h create from target/h/arch/arm/excArmLib.h version 01f
|
||||
*/
|
||||
|
||||
#ifndef __INCexcArmLib_mh
|
||||
#define __INCexcArmLib_mh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* NOTE: if this structure changes, the TCB offsets in h/private/taskLibP.h
|
||||
* must be updated. See also taskLib.h.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT32 valid; /* flags indicate following fields are valid */
|
||||
UINT32 vecNum; /* exception number */
|
||||
INSTR * pc; /* PC */
|
||||
UINT32 psr; /* combined A/I/E PSR */
|
||||
UINT32 primask; /* PRIMASK */
|
||||
UINT32 faultmask; /* FAULTMASK */
|
||||
UINT32 basepri; /* BASEPRI */
|
||||
UINT32 control; /* Control Register */
|
||||
UINT32 sysHandlrStat; /* System Handler Control and State Register */
|
||||
UINT32 hardFltStat; /* Hard Fault Status Register */
|
||||
UINT32 configFltStat; /* Configurable Fault Status Register */
|
||||
UINT32 memFltAddr; /* Memory Manage Fault Address Register */
|
||||
UINT32 busFltAddr; /* Bus Fault Address Register */
|
||||
} EXC_INFO;
|
||||
|
||||
extern FUNCPTR excExcepHook; /* add'l rtn to call when exceptions occur */
|
||||
extern VOIDFUNCPTR _func_excBreakpoint; /* called to handle breakpoints */
|
||||
|
||||
extern void excVecBaseSet (UINT32 base); /* non-zero exception base address */
|
||||
|
||||
extern STATUS excIntConnect (VOIDFUNCPTR * vector, VOIDFUNCPTR routine);
|
||||
|
||||
extern void excVecSet (FUNCPTR * vector, FUNCPTR function);
|
||||
extern FUNCPTR excVecGet (FUNCPTR * vector);
|
||||
|
||||
extern STATUS excVecPrioSet (VOIDFUNCPTR * vector, UINT8 priority);
|
||||
extern STATUS excVecPrioGet (VOIDFUNCPTR * vector, UINT8 * pPriority);
|
||||
extern void excClearFault (void);
|
||||
|
||||
#endif /* ASMLANGUAGE */
|
||||
|
||||
/* exception information valid bits */
|
||||
|
||||
#define EXC_INFO_VECNUM 0x01 /* vector is valid */
|
||||
#define EXC_INFO_PC 0x02 /* PC is valid */
|
||||
#define EXC_INFO_XPSR 0x04 /* xPSR is valid */
|
||||
#define EXC_INFO_PRIMASK 0x08 /* PRIMASK is valid */
|
||||
#define EXC_INFO_FAULTMASK 0x10 /* FAULTMASK is valid */
|
||||
#define EXC_INFO_BASEPRI 0x20 /* BASEPRI is valid */
|
||||
#define EXC_INFO_CONTROL 0x40 /* Control Register is valid */
|
||||
#define EXC_INFO_SYSHDLRSTAT 0x80 /* System Handler Ctrl/State is valid */
|
||||
#define EXC_INFO_HRDFLTSTAT 0x100 /* Hard Fault Status is valid */
|
||||
#define EXC_INFO_CFGFLTSTAT 0x200 /* Configurable Fault Status is valid */
|
||||
#define EXC_INFO_MEMFLTADDR 0x400 /* Mem Manage Fault Address is valid */
|
||||
#define EXC_INFO_BUSFLTADDR 0x800 /* Bus Fault Address is valid */
|
||||
|
||||
#define EXC_INFO_ALL_VALID 0xFFF /* all EXC_INFO fields are valid */
|
||||
|
||||
/*
|
||||
* Exception Numbers
|
||||
*
|
||||
* Note there is no Exception number 0. If the IPSR contains zero then we are
|
||||
* in thread mode and therefore not servicing an exception or interrupt.
|
||||
*/
|
||||
|
||||
#define EXC_NUM_THREAD_MODE 0 /* IPSR is 0 when in thread mode */
|
||||
|
||||
#define EXC_NUM_RESET 1 /* Reset */
|
||||
#define EXC_NUM_NMI 2 /* Nonmaskable Interrupt */
|
||||
#define EXC_NUM_HARD_FAULT 3 /* unimplemented fault handler */
|
||||
#define EXC_NUM_MEM_MANAGE 4 /* MPU Violation */
|
||||
#define EXC_NUM_BUS_FAULT 5 /* Bus Error */
|
||||
#define EXC_NUM_USAGE_FAULT 6 /* Program error or coprocessor */
|
||||
#define EXC_NUM_SVCALL 11 /* Supervisor Call */
|
||||
#define EXC_NUM_DEBUG_MONITOR 12 /* Debug Monitor */
|
||||
#define EXC_NUM_PENDSV 14 /* PendSV */
|
||||
#define EXC_NUM_SYSTICK 15 /* System Tick Timer */
|
||||
#define EXC_NUM_IRQ_BASE 16 /* First External Interrupt */
|
||||
|
||||
#define EXC_NUM_IRQ(num) (EXC_NUM_IRQ_BASE + (num))
|
||||
|
||||
#define EXC_NUM_LAST_IRQ 511
|
||||
|
||||
/* Exception Vectors
|
||||
*
|
||||
* The values at these offsets are 32-bit addresses of exception handlers.
|
||||
* This is different from traditional arm architectures (such as ARMv7) which
|
||||
* expect branch instructions or some other executable instructions.
|
||||
*
|
||||
* Note: the first entry (entry 0) in the exception vector table is the
|
||||
* initial value of the stack pointer after reset, and not an exception vector
|
||||
* address. Although not actually an exception vector, it is included here
|
||||
* for completeness.
|
||||
*/
|
||||
|
||||
#define EXC_OFF_INITIAL_SP 0x00
|
||||
|
||||
#define EXC_OFF_RESET (EXC_NUM_RESET * 4)
|
||||
#define EXC_OFF_NMI (EXC_NUM_NMI * 4)
|
||||
#define EXC_OFF_HARD_FAULT (EXC_NUM_HARD_FAULT * 4)
|
||||
#define EXC_OFF_MEM_MANAGE (EXC_NUM_MEM_MANAGE * 4)
|
||||
#define EXC_OFF_BUS_FAULT (EXC_NUM_BUS_FAULT * 4)
|
||||
#define EXC_OFF_USAGE_FAULT (EXC_NUM_USAGE_FAULT * 4)
|
||||
#define EXC_OFF_SVCALL (EXC_NUM_SVCALL * 4)
|
||||
#define EXC_OFF_DEBUG_MONITOR (EXC_NUM_DEBUG_MONITOR * 4)
|
||||
#define EXC_OFF_PENDSV (EXC_NUM_PENDSV * 4)
|
||||
#define EXC_OFF_SYSTICK (EXC_NUM_SYSTICK * 4)
|
||||
#define EXC_OFF_IRQ_BASE (EXC_NUM_IRQ_BASE * 4)
|
||||
|
||||
#define EXC_OFF_IRQ(num) (EXC_OFF_IRQ_BASE + ((num)*4))
|
||||
|
||||
#define EXC_OFF_LAST_IRQ EXC_OFF_IRQ(EXC_NUM_LAST_IRQ)
|
||||
|
||||
/* Exception Vector Base */
|
||||
#define ARM_EXC_VEC_BASE 0x00
|
||||
|
||||
/*
|
||||
* Map the traditional ARM definition to the ARM-M exception offset.
|
||||
*/
|
||||
|
||||
/* Scope tools needs to know which vector handles undefined instructions. */
|
||||
#define EXC_OFF_UNDEF (EXC_NUM_USAGE_FAULT)
|
||||
|
||||
/* ObjVerify needs to know which vector handles Page Faults */
|
||||
#define EXC_OFF_DATA (EXC_NUM_MEM_MANAGE)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCexcArmLib_mh */
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,116 @@
|
||||
/* intArmLib.h - ARM-specific interrupt library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,12apr12,jdw created.
|
||||
*/
|
||||
|
||||
#ifndef __INCintArmLibh
|
||||
#define __INCintArmLibh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef _WRS_ENABLE_IRQ_TRACING
|
||||
/*
|
||||
* For tracing we can define some "no-op" instructions which can be
|
||||
* inserted and identified in the ICE trace buffer.
|
||||
*/
|
||||
#define WRS_ICE_TRACE_IRQ_LOCK orr r5,r5,r5
|
||||
#define WRS_ICE_TRACE_IRQ_UNLOCK orr r6,r6,r6
|
||||
#else /* _WRS_ENABLE_IRQ_TRACING */
|
||||
#define WRS_ICE_TRACE_IRQ_LOCK
|
||||
#define WRS_ICE_TRACE_IRQ_UNLOCK
|
||||
#endif /* _WRS_ENABLE_IRQ_TRACING */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* inline intCpuLock()/intCpuUnlock() and intCpuMicroLock/Unlock() */
|
||||
|
||||
#if defined (__DCC__)
|
||||
|
||||
__asm volatile int _inline_intCpuLock ()
|
||||
{
|
||||
! "r0"
|
||||
mrs r0, BASEPRI /* get current status */
|
||||
mov r1, #0x10
|
||||
mrs BASEPRI, r1
|
||||
WRS_ICE_TRACE_IRQ_LOCK
|
||||
}
|
||||
|
||||
__asm volatile void _inline_intCpuUnlock (int key)
|
||||
{
|
||||
% reg key; lab label ! "r0" /* input: key in r0 */
|
||||
|
||||
mrs BASEPRI, r0
|
||||
WRS_ICE_TRACE_IRQ_UNLOCK
|
||||
}
|
||||
|
||||
#elif defined (__GNUC__)
|
||||
|
||||
static __inline__ int _inline_intCpuLock (void)
|
||||
{
|
||||
int key;
|
||||
__asm__ volatile
|
||||
(
|
||||
"mrs r0, BASEPRI; " /* get current status */
|
||||
"mov r1, #0x10 " /* set new status */
|
||||
"mrs BASEPRI, r1 "
|
||||
: "=&r" (key) /* output: key is %0 */
|
||||
: /* no input */
|
||||
: "r0", "r1"
|
||||
);
|
||||
return key;
|
||||
}
|
||||
|
||||
static __inline__ void _inline_intCpuUnlock (int key)
|
||||
{
|
||||
__asm__ volatile
|
||||
(
|
||||
"mrs BASEPRI, r0 " /* set new status */
|
||||
: "r" (key) /* input: key is %0 */
|
||||
: "r0" /* r0, r1 clobbered; memory */
|
||||
/* clobber for code barrier */
|
||||
);
|
||||
}
|
||||
|
||||
#endif /* __DCC__ */
|
||||
|
||||
/*
|
||||
* For ARM-M these functions are identical
|
||||
*/
|
||||
|
||||
#define _inline_intCpuMicroLock() _inline_intCpuLock()
|
||||
#define _inline_intCpuMicroUnlock(key) _inline_intCpuUnlock(key)
|
||||
|
||||
/* functions in intArchLib.c and intALib.s */
|
||||
|
||||
extern STATUS intArchConnect (VOIDFUNCPTR * vector,
|
||||
VOIDFUNCPTR routine, int argument);
|
||||
extern STATUS intArchDisconnect (VOIDFUNCPTR * vector,
|
||||
VOIDFUNCPTR routine, int argument);
|
||||
extern int intLevelSet (int level);
|
||||
|
||||
extern STATUS intEnable (int level);
|
||||
extern STATUS intDisable (int level);
|
||||
|
||||
extern unsigned int getBasePri( void );
|
||||
extern unsigned int setBasePri( unsigned int level );
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCintArmLibh */
|
||||
@@ -0,0 +1,106 @@
|
||||
/* regsArm-m.h - ARMv7-M registers */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,19jul12,jdw Add missing TCB offset register definitions
|
||||
01d,23may12,jdw Add PRIMASK and BASEPRI offsets
|
||||
01c,10may12,j_b fix tabs/spacing
|
||||
01b,03may12,j_b replace "-" in filename include macro
|
||||
01a,03apr12,j_b created from target/h/arch/arm/regsArm.f version 01f
|
||||
*/
|
||||
|
||||
#ifndef __INCregsArm_mh
|
||||
#define __INCregsArm_mh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define GREG_NUM 15 /* has 15 32-bit general registers */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* REG_SET - ARMv7-M Register set
|
||||
* Note that the exception stack frame relies on the order of items
|
||||
* in this so don't change this without changing the ESF and the stub
|
||||
* in excALib which creates it.
|
||||
*/
|
||||
|
||||
typedef struct /* REG_SET - ARMv7-M register set */
|
||||
{
|
||||
ULONG r[GREG_NUM]; /* general purpose registers 0-14 */
|
||||
INSTR *pc; /* program counter */
|
||||
ULONG psr; /* combined A/I/E PSR */
|
||||
ULONG basepri; /* BASEPRI */
|
||||
ULONG demcr; /* MON_STEP in DEMCR */
|
||||
} REG_SET;
|
||||
|
||||
typedef struct wind_cpu_state
|
||||
{
|
||||
REG_SET regs;
|
||||
} WIND_CPU_STATE;
|
||||
|
||||
#define fpReg r[11] /* frame pointer */
|
||||
#define spReg r[13] /* stack pointer */
|
||||
#define lrReg r[14] /* link reg pointer */
|
||||
|
||||
#define reg_pc pc /* program counter */
|
||||
|
||||
#define reg_lr lrReg /* link reg pointer */
|
||||
#define reg_sp spReg /* stack pointer */
|
||||
#define reg_fp fpReg /* frame pointer */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#define ARM_REG_SIZE 4
|
||||
#define REG_SET_G_REG_BASE 0x00 /* data reg's base offset to REG_SET */
|
||||
#define REG_SET_G_REG_OFFSET(n) (REG_SET_G_REG_BASE + (n)*ARM_REG_SIZE)
|
||||
#define REG_SET_PC_OFFSET (REG_SET_G_REG_OFFSET(GREG_NUM))
|
||||
#define REG_SET_CPSR_OFFSET (REG_SET_PC_OFFSET + ARM_REG_SIZE)
|
||||
#define REG_SET_BASEPRI_OFFSET (REG_SET_CPSR_OFFSET + ARM_REG_SIZE)
|
||||
#define REG_SET_DEMCR_OFFSET (REG_SET_BASEPRI_OFFSET + ARM_REG_SIZE)
|
||||
|
||||
#define PC_OFFSET REG_SET_PC_OFFSET
|
||||
|
||||
/* PAL additions */
|
||||
|
||||
/* moved here from h/private/taskLibP.h */
|
||||
|
||||
#define WIND_TCB_R0 WIND_TCB_REGS
|
||||
#define WIND_TCB_R1 (WIND_TCB_R0+4*1)
|
||||
#define WIND_TCB_R2 (WIND_TCB_R0+4*2)
|
||||
#define WIND_TCB_R3 (WIND_TCB_R0+4*3)
|
||||
#define WIND_TCB_R4 (WIND_TCB_R0+4*4)
|
||||
#define WIND_TCB_R5 (WIND_TCB_R0+4*5)
|
||||
#define WIND_TCB_R6 (WIND_TCB_R0+4*6)
|
||||
#define WIND_TCB_R7 (WIND_TCB_R0+4*7)
|
||||
#define WIND_TCB_R8 (WIND_TCB_R0+4*8)
|
||||
#define WIND_TCB_R9 (WIND_TCB_R0+4*9)
|
||||
#define WIND_TCB_R10 (WIND_TCB_R0+4*10)
|
||||
#define WIND_TCB_R11 (WIND_TCB_R0+4*11)
|
||||
#define WIND_TCB_R12 (WIND_TCB_R0+4*12)
|
||||
#define WIND_TCB_SP (WIND_TCB_R0+4*13)
|
||||
#define WIND_TCB_LR (WIND_TCB_R0+4*14)
|
||||
#define WIND_TCB_PC (WIND_TCB_R0+4*15)
|
||||
#define WIND_TCB_CPSR (WIND_TCB_PC+4)
|
||||
#define WIND_TCB_BASEPRI (WIND_TCB_PC+8)
|
||||
#define WIND_TCB_DEMCR (WIND_TCB_PC+12)
|
||||
|
||||
|
||||
/* End PAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCregsArm_mh */
|
||||
@@ -0,0 +1,196 @@
|
||||
/* vfpArmLib.h - Arm Version of Vector Floating-Point Include File */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,07may13,c_t VFPv4 SP written based on standard version
|
||||
*/
|
||||
|
||||
#ifndef __INCvfpArmLibSph
|
||||
#define __INCvfpArmLibSph
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* for cortex M the following register are memory mapped and the addresses
|
||||
* are architectural defined.
|
||||
*/
|
||||
|
||||
/* Coprocessor Access Control Register, CPACR, enable CP10 & CP11 for VFP */
|
||||
|
||||
#define CPACR (0xE000ED88)
|
||||
#define CPACR_CP_FULL(x) (3<<(2*(x))) /* 0b11 : Full access for this cp */
|
||||
|
||||
/* Floating-Point Context Control Register, FPCCR */
|
||||
|
||||
#define FPCCR (0xE000EF34)
|
||||
#define FPCCR_ASPEN (1<<31) /* enable auto FP context stacking */
|
||||
#define FPCCR_LSPEN (1<<30) /* enable lazy FP context stacking */
|
||||
#define FPCCR_MONRDY (1<<8)
|
||||
#define FPCCR_BFRDY (1<<6)
|
||||
#define FPCCR_MMRDY (1<<5)
|
||||
#define FPCCR_HFRDY (1<<4)
|
||||
#define FPCCR_THREAD (1<<3) /* allocated FP stack in thread */
|
||||
#define FPCCR_USER (1<<1) /* allocated FP stack in priviledged */
|
||||
#define FPCCR_LSPACT (1<<0) /* lazy stacking is active */
|
||||
|
||||
/* Floating-Point Context Address Register, FPCAR */
|
||||
/* this register contains the FP context address in the exception stack */
|
||||
|
||||
#define FPCAR (0xE000EF38)
|
||||
|
||||
/* Floating-Point Default Status Control Register, FPDSCR */
|
||||
|
||||
/*
|
||||
* set the initial value of FPSCR, however we can set it manually to FPSCR
|
||||
* when creating the VFP task, so let it as is at this time.
|
||||
*/
|
||||
|
||||
#define FPDSCR (0xE000EF3C)
|
||||
#define FPDSCR_AHP (1<<26)
|
||||
#define FPDSCR_DN (1<<25)
|
||||
#define FPDSCR_FZ (1<<24)
|
||||
#define FPDSCR_RMODE 0x00C00000
|
||||
#define FPDSCR_RN 0x00000000 /* round to nearest */
|
||||
#define FPDSCR_RP 0x00400000 /* round toward plus infinity */
|
||||
#define FPDSCR_RM 0x00800000 /* round toward minus infinity */
|
||||
#define FPDSCR_RZ 0x00C00000 /* round toward zero */
|
||||
|
||||
/* Media and FP Feature Register 0, MVFR0 & Register 1, MVFR1*/
|
||||
|
||||
/* these read only registers are using to detect feature that supported */
|
||||
|
||||
#define MVFR0 (0xE000EF40)
|
||||
#define MVFR0_SP_MSK (0x000000F0) /* bit 4~7 = 0x2, support sp */
|
||||
#define MVFR0_SP_EN (0x20) /* bit 4~7 = 0x2, support sp */
|
||||
#define MVFR1 (0xE000EF44)
|
||||
|
||||
/* FPSCR (Floating Status and Control Register) bit definitions for VFPv4SP */
|
||||
|
||||
/*
|
||||
* At the time of implementation bits 27, 21-8, and 6-5,
|
||||
* are described as reserved, one must employ
|
||||
* read/modify/write techniques when handling the FPSCR in order
|
||||
* to ensure that these bits are not modified...
|
||||
*/
|
||||
|
||||
#define FPSCR_N_BIT (1<<31) /* less than result */
|
||||
#define FPSCR_Z_BIT (1<<30) /* equal result */
|
||||
#define FPSCR_C_BIT (1<<29) /* equal, greater than, or unordered result */
|
||||
#define FPSCR_V_BIT (1<<28) /* unordered result */
|
||||
|
||||
#define FPSCR_AHP (1<<26)
|
||||
|
||||
#define FPSCR_DN_BIT (1<<25) /* Default NaN mode control */
|
||||
#define FPSCR_DN_MSK FPSCR_DN_BIT
|
||||
#define FPSCR_DN_ENABLE FPSCR_DN_BIT
|
||||
#define FPSCR_DN_DISABLE 0x00000000
|
||||
|
||||
#define FPSCR_FZ_BIT (1<<24) /* flush to zero mode control */
|
||||
#define FPSCR_FZ_MSK FPSCR_FZ_BIT
|
||||
#define FPSCR_FZ_ENABLE FPSCR_FZ_BIT
|
||||
#define FPSCR_FZ_DISABLE 0x00000000
|
||||
|
||||
/* Cumulative Exception Bits */
|
||||
|
||||
#define FPSCR_IDC_BIT (1<<7) /* Input Subnormal */
|
||||
#define FPSCR_IXC_BIT (1<<4) /* Inexact */
|
||||
#define FPSCR_UFC_BIT (1<<3) /* Underflow */
|
||||
#define FPSCR_OFC_BIT (1<<2) /* Overflow */
|
||||
#define FPSCR_DZC_BIT (1<<1) /* Division By Zero */
|
||||
#define FPSCR_IOC_BIT (1<<0) /* Invalid Operation */
|
||||
|
||||
/* Round Mode Control Bits */
|
||||
|
||||
#define FPSCR_RMODES_MSK 0x00C00000 /* round mode */
|
||||
#define FPSCR_RN 0x00000000 /* round to nearest */
|
||||
#define FPSCR_RP 0x00400000 /* round toward plus infinity */
|
||||
#define FPSCR_RM 0x00800000 /* round toward minus infinity */
|
||||
#define FPSCR_RZ 0x00C00000 /* round toward zero */
|
||||
|
||||
#ifdef _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO
|
||||
#define FPSCR_INIT FPSCR_DN_MSK
|
||||
#else /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
|
||||
#define FPSCR_INIT (FPSCR_DN_MSK | FPSCR_FZ_BIT)
|
||||
#endif /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
|
||||
|
||||
#define VFPREG_SET VFP_CONTEXT
|
||||
|
||||
#define _VFP_ALIGN_SIZE 8 /* Not sure if this is needed */
|
||||
|
||||
/* vfpv4 sp only support D16/S32. */
|
||||
|
||||
#define VFP_DGPR_NUM 16 /* 16-double precision general purpose */
|
||||
#define VFP_SGPR_NUM 32 /* 32-single precision general purpose */
|
||||
|
||||
/* FP_CONTEXT structure offsets */
|
||||
|
||||
#define VFP_FPSCR 0x00
|
||||
#define VFP_PAD -
|
||||
#define VFP_GPR 0x08 /* OFFSET(FP_CONTEXT, vfp_gpr[0]) */
|
||||
#define VFP_GPR_OFFSET(n) (VFP_GPR + (n)*4) /* vfp_gpr[n]) */
|
||||
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* standard interface to fp lib. */
|
||||
|
||||
/* vfpv4 sp context is different with standard vfp. */
|
||||
|
||||
typedef struct vfpContext /* VFP Context */
|
||||
{
|
||||
UINT32 fpscr; /* status and control register */
|
||||
UINT32 pad; /* pad to match 8 byte alignment */
|
||||
UINT32 vfp_gpr[VFP_SGPR_NUM]; /* general purpose registers */
|
||||
/* TOTAL */
|
||||
} WRS_PACK_ALIGN(_VFP_ALIGN_SIZE) VFP_CONTEXT;
|
||||
|
||||
/* function declarations */
|
||||
|
||||
IMPORT void vfpArchInit (void);
|
||||
IMPORT void vfpArchTaskCreateInit (VFP_CONTEXT *pDspContext);
|
||||
|
||||
IMPORT void vfpSave (VFP_CONTEXT *);
|
||||
IMPORT void vfpRestore (VFP_CONTEXT *);
|
||||
|
||||
IMPORT STATUS vfpProbe (void);
|
||||
IMPORT STATUS vfpEnable (void);
|
||||
IMPORT STATUS vfpDisable (void);
|
||||
|
||||
IMPORT VFP_CONTEXT * vfpCtxCreate (int);
|
||||
IMPORT STATUS vfpCtxDelete (VFP_CONTEXT *);
|
||||
IMPORT void vfpCtxShow (VFP_CONTEXT *);
|
||||
|
||||
void vfpRegsToCtx (VFPREG_SET *, VFP_CONTEXT *);
|
||||
void vfpCtxToRegs (VFP_CONTEXT *, VFPREG_SET *);
|
||||
|
||||
#ifdef _WRS_HW_VFP_SUPPORT
|
||||
IMPORT int vfpIsEnabled (void);
|
||||
IMPORT int vfpHasException (void);
|
||||
IMPORT STATUS vfpProbeSup (void);
|
||||
IMPORT UINT32 vfpFpSidGet (void);
|
||||
IMPORT UINT32 vfpFpScrGet (void);
|
||||
IMPORT void vfpFpScrSet (UINT32);
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __INCvfpArmLibSph */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user