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neelimap
2026-07-30 11:19:44 +05:30
parent 170c2b3f3a
commit afc7070c1f
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vxworks-6.9/target/h/arch/arm/_G_configArch.h
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/* _G_config.h - autogenerated on Tue Feb 3 10:11:41 PST 1998*/
/* There may be a few (VxWorks related) differences between this file and the
* corresponding one in host/$WIND_HOST_TYPE/arm-wrs-vxworks/include
*/
/* AUTOMATICALLY GENERATED; DO NOT EDIT! */
#ifndef _G_config_h
#define _G_config_h
#define _G_LIB_VERSION "2.8.0"
#define _G_NAMES_HAVE_UNDERSCORE 1
#define _G_VTABLE_LABEL_HAS_LENGTH 1
#define _G_VTABLE_LABEL_PREFIX "__vt$"
#define _G_HAVE_ST_BLKSIZE 1
#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 7)
typedef int _G_int8_t __attribute__((__mode__(__QI__)));
typedef unsigned int _G_uint8_t __attribute__((__mode__(__QI__)));
typedef int _G_int16_t __attribute__((__mode__(__HI__)));
typedef unsigned int _G_uint16_t __attribute__((__mode__(__HI__)));
typedef int _G_int32_t __attribute__((__mode__(__SI__)));
typedef unsigned int _G_uint32_t __attribute__((__mode__(__SI__)));
typedef int _G_int64_t __attribute__((__mode__(__DI__)));
typedef unsigned int _G_uint64_t __attribute__((__mode__(__DI__)));
#if defined (__cplusplus)
__extension__ typedef long long _G_llong;
__extension__ typedef unsigned long long _G_ullong;
#else
typedef long long _G_llong;
typedef unsigned long long _G_ullong;
#endif
#else
typedef short /* deduced */ _G_int16_t;
typedef unsigned short /* deduced */ _G_uint16_t;
typedef long /* deduced */ _G_int32_t;
typedef unsigned long /* deduced */ _G_uint32_t;
#endif
typedef unsigned long _G_clock_t;
typedef short _G_dev_t;
typedef long _G_fpos_t;
typedef unsigned short _G_gid_t;
typedef unsigned short _G_ino_t;
typedef int _G_mode_t;
typedef unsigned short _G_nlink_t;
typedef long _G_off_t;
typedef int _G_pid_t;
#ifndef __PTRDIFF_TYPE__
#define __PTRDIFF_TYPE__ long int
#endif
typedef __PTRDIFF_TYPE__ _G_ptrdiff_t;
typedef unsigned long _G_sigset_t;
#ifndef __SIZE_TYPE__
#define __SIZE_TYPE__ long unsigned int
#endif
typedef __SIZE_TYPE__ _G_size_t;
typedef long _G_time_t;
typedef unsigned short _G_uid_t;
typedef int _G_wchar_t;
#define _G_BUFSIZ 1024
#define _G_FOPEN_MAX 20
#define _G_FILENAME_MAX 1024
#if defined (__cplusplus) || defined (__STDC__)
#define _G_ARGS(ARGLIST) ARGLIST
#else
#define _G_ARGS(ARGLIST) ()
#endif
#if !defined (__GNUG__) || defined (__STRICT_ANSI__)
#define _G_NO_NRV
#endif
#if !defined (__GNUG__)
#define _G_NO_EXTERN_TEMPLATES
#endif
typedef int /* default */ _G_ssize_t;
typedef int /* default */ _G_wint_t;
typedef void * _G_va_list;
#define _G_signal_return_type void
#define _G_sprintf_return_type int
#define _G_HAVE_ATEXIT 0
#define _G_HAVE_SYS_RESOURCE 0
#define _G_HAVE_SYS_TIMES 1
#define _G_HAVE_SYS_SOCKET 0
#define _G_HAVE_SYS_CDEFS 0
#define _G_HAVE_SYS_WAIT 1
#define _G_HAVE_UNISTD 1
#define _G_HAVE_DIRENT 0
#define _G_HAVE_CURSES 0
#define _G_MATH_H_INLINES 0
#define _G_HAVE_BOOL 1
#define _G_HAVE_PRINTF_FP 0
#define _G_HAVE_LONG_DOUBLE_IO 0
#undef NULL
#ifdef __cplusplus
#define NULL __null
#else
#define NULL 0
#endif
#include <stddef.h>
#endif /* !_G_config_h */
vxworks-6.9/target/h/arch/arm/archArm.h
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/* archArm.h - ARM specific header */
/*
* Copyright (c) 1996, 1998, 1999, 2001, 2003-2011, 2013
* Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
02t,01jun13,yjw update for ARMARCH7M
02s,12aug11,jb WIND00238999 Limit Device Power Mgmt to ARMARCH7
02r,17nov10,dbr define _WRS_ARCH_HAS_DEV_PWR_MGMT for device power management
02q,16sep10,gls added VX_OBJ_ALIGN_SIZE
02p,29jul10,pad Moved extern C statement after include statements.
02o,27aug10,rlp Added _WRS_ARCH_HAS_VXDBG_BP_ADDR_CHECK macro.
02n,24aug10,jdw Fix _WRS_REV_INSN_SET_CHANGE for Thumb2
02m,09jun10,m_h Thumb-2 Support
02l,10mar10,j_b define _WRS_PHYS_ADDR_IS_64_BITS for XScale, ARMv6+
(WIND00129408)
02k,20oct09,z_l add SMP support for ARMARCH7
02j,25feb09,j_b merge ARM SMP support, incl adding VSB header file:
22feb08,j_b replace intUnlock with intCpuUnlock
12nov07,jmp Define _WRS_ARCH_HAS_VXDBG_CPU_CTRL_SUPPORT
02nov07,jb Add coherency flag for SMP and build exclusions
10oct07,j_b define _WRS_ARCH_HAS_DBG_IPI
02i,27feb09,m_h ARMARCH7 Support
02h,31jul08,tcr change macro for compatibility
02g,19may08,tcr update SV instrumentation
02f,16aug07,j_b added _WRS_MMU_HAS_MAP_STATE_API
02e,08jun07,j_b Add definition for _WRS_VX_NO_GLOBAL_ERRNO
02d,21may07,j_b define _WRS_ARCH_HAS_IDLE_TASK, VX_MAX_SMP_CPUS
02c,04may07,zl updated portable library build configuration,
added _WRS_CPU_HAS_CLZ_INSTR.
02b,21feb07,jmg Added include vxPortableP.h
02a,11dec06,kk removed references to _WRS_BASE6_SCHEDULER, no longer needed
01z,21jun06,jb Re-enable fast ffs for arch5, make ARMARCH6 64 bit PHYS_ADDR
01y,02mar06,jb Fix for SPR 118321 - vfp references in 920t
01x,01feb06,jb Adding VFP Support
01w,12jan06,jb Enabling 920t variant support
01v,10jan06,hya Add ARM CPU variant code for FFS(x) (WRN)
01u,19dec05,jb Changing XSCALE to 64 bit PHYS_ADDR
01t,24aug05,h_k Added _WRS_SUPPORT_CACHE_XLATE.
01s,12apr05,kk remove _WRS_OBJLIB_SUPPORT_VERIFY_TRAP macro (SPR# 106486)
01r,28mar05,scm add _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
01q,18feb05,dbt Moved some loader specific macros to elfArm.h.
01p,17feb05,scm add _WRS_OSM_INIT definition, and clarify
PORTABLE/NON-PORTABLE inclussion
01o,17jan05,jb Adding architecture specific objVerify support
01n,08sep04,scm move INSTR to archArmCommon.h
01m,10aug04,scm undef "OPTIMIZE", define "PORTABLE"...
01l,27apr04,cjj Defined workQLib_PORTABLE
01k,01dec03,scm clean up, SPR #90358... remove obnoxious warning...
01j,25nov03,pes Move setting of _BYTE_ORDER macro into archArmCommon.h
01i,14nov03,job Moved some blib stuff to archArmCommon.h
01h,13nov03,pes Add include of archArmCommon.h
01h,29oct03,sn gcc 3.3.2 does not currently support arm or sh
01g,27aug03,to added defines for semLib.
01f,07may03,pes PAL conditional compilation cleanup. Phase 2.
01e,29apr03,pes PAL conditional compilation cleanup.
01d,13mar01,sn SPR 73723 - define supported toolchains
01c,20jan99,cdp removed support for old ARM libraries.
01b,17aug98,cdp added big-endian and multiple cachelib support.
01a,08may96,cdp written based on archI86.h
*/
#ifndef __INCarchArmh
#define __INCarchArmh
#include <vsbConfig.h>
/* In the cases where vxWorks.h is not defined first... */
#if !defined (TRUE)
#define TRUE 1
#endif
#if !defined (FALSE)
#define FALSE 0
#endif
#undef _ARCH_SUPPORTS_GCC
#define _ARCH_SUPPORTS_DCC
/* define to indicate ARM supports device power management */
#if (CPU==ARMARCH7) || (CPU==ARMARCH7_T2)
#define _WRS_ARCH_HAS_DEV_PWR_MGMT
#endif /* (CPU==ARMARCH7) || (CPU==ARMARCH7_T2) */
/* temporary macro to indicate ARM uses the idle task stack */
#define _WRS_ARCH_HAS_IDLE_TASK
/* temporary define to indicate ARM uses task-specific errnos */
#define _WRS_VX_NO_GLOBAL_ERRNO
/* temporary define to indicate ARM supports MMU state info with map request */
#define _WRS_MMU_HAS_MAP_STATE_API
/* temporary macro to indicate ARM has Debug IPI */
#define _WRS_ARCH_HAS_DBG_IPI
/* indicates that ARM has VxDBG CPU control support */
#define _WRS_ARCH_HAS_VXDBG_CPU_CTRL_SUPPORT
/*
* Indicate that the ARM architecture has the VxDBG support to check the
* alignment of the breakpoint address.
*/
#define _WRS_ARCH_HAS_VXDBG_BP_ADDR_CHECK
#undef VX_MAX_SMP_CPUS
#define VX_MAX_SMP_CPUS 4 /* maximum processors in SMP configuration */
/*
* For SMP, any shared data region that is created from the RAM need
* to be memory coherent.
* So we need to set the page attribute to MMU_ATTR_CACHE_COHERENCY.
* The arches, need to specify this via the macro
* VM_DEFAULT_CACHE_COHERENCY_ATTR
*/
#ifdef _WRS_CONFIG_SMP
/* Limit SMP build to ARMARCH6 and ARMARCH7 little endian */
#if ((CPU == ARMARCH6) || (CPU == ARMARCH7)) && !defined(ARMEB) && !defined(__ARMEB__)
#define VM_DEFAULT_CACHE_COHERENCY_ATTR MMU_ATTR_CACHE_COHERENCY
#else
#error SMP build is NOT supported by this architecture/tool combination
#endif /* (CPU == ARMARCH6) && !defined(ARMEB) && !defined(__ARMEB__) */
#endif /* _WRS_CONFIG_SMP */
#define _DYNAMIC_BUS_SIZING FALSE /* require alignment for swap */
#define _ARCH_MULTIPLE_CACHELIB TRUE /* multiple cache libraries */
/* macros for AIM Cache */
#define _WRS_SUPPORT_CACHE_XLATE /* cache virt-phys translate */
#if !defined(ARMCPU920T)
/* Say VFP is Supported */
#define _WRS_HW_VFP_SUPPORT
#endif /* !defined(ARMCPU920T) */
#ifdef __cplusplus
extern "C" {
#endif
#if ((CPU == XSCALE) || (CPU == ARMARCH6) || (CPU == ARMARCH7) \
|| (CPU == ARMARCH7_T2))
/* physical addresses are represented with 64 bits for these CPUs */
#define _TYPE_PHYS_ADDR typedef UINT64 PHYS_ADDR
#define _WRS_PHYS_ADDR_IS_64_BITS
#endif /* ((CPU == XSCALE, ARMARCH6, ARMARCH7, ARMARCH7_T2)) */
#ifdef __cplusplus
}
#endif
#include "arm.h"
#ifdef __cplusplus
extern "C" {
#endif
/* PAL additions */
/*
* VX_OBJ_ALIGN_SIZE is the default allocation boundary for kernel objects.
* This is used for both statically and dynamically allocated objects.
*/
#define VX_OBJ_ALIGN_SIZE 8 /* 8-byte alignment */
/* moved here from h/private/eventP.h */
/*
* (Borrowed from PPC.)
*
* Macro for event logging of intEnt events for ARM architectures.
* The ARM architecture is different in that there is only one external
* interrupt line coming into the CPU. At the time of the intEnt, the
* external interrupt number is unknown, meaning that logging cannot
* take place at this time. In this architecture, the logging of an
* intEnt event is deferred until the interrupt controller driver
* is executed.
* Since the logging has to take place in drivers and/or BSP world files,
* the details of how the logging to be done has been deferred to a macro
* which is defined here.
*
* Note: This replaces the previous technique of saving the timestamp
* during the intEnt code to be used later, when the logging was done.
* SPR 21868 refers to a problem in which this can give rise to out-of-order
* timestamps in the event log.
*/
#define WV_EVT_INT_ENT(intNum) EVT_CTX_1(EVENT_INT_ENTER, intNum);
/* moved here from h/private/classLibP.h */
#define OBJ_CLASS_initRtn 0x24 /* Offsets into OBJ_CLASS */
/* status codes */
#define S_vmLib_NO_FREE_REGIONS (M_vmLib | 6)
#define S_vmLib_ADDRS_NOT_EQUAL (M_vmLib | 7)
/* from dbgLib.c */
#define _WRS_FRAME_PRINT_STRING " : "
/* from loadElfLib.c */
#define _WRS_USE_ELF_LOAD_FORMAT
/* from periodHost.c, repeatHost.c, shell.c, and taskLib.c */
#if (ARM_THUMB) || (ARM_THUMB2)
#define _WRS_CHANGE_INSN_SET_ENABLE
#define _WRS_CHANGE_INSN_SET(p) (p) = ((FUNCPTR)(((UINT32)(p))|1))
#define _WRS_CHANGE_INSN_SET_PTR(p) ((FUNCPTR)(((UINT32)(p))|1))
#define _WRS_REV_INSN_SET_CHANGE(p) ((FUNCPTR)(((UINT32)(p)) & ~1))
#endif /* ARM_THUMB || (ARM_THUMB2) */
/* OSM support for stack protection, used in sysOsmLib.c */
#define _WRS_OSM_INIT
/* Interrupt stack protection, used in usrDepend.c and usrKernelStack.c */
#define _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
/*
* if OSM support not available for stack protection,
* then support can not be available for interrupt
* stack protection.
*/
#if !defined(_WRS_OSM_INIT)
#undef _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
#endif
#if defined(_ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK)
#undef _WRS_SVC_INT_STACK
#undef _WRS_IRQ_INT_STACK
#undef _WRS_DUAL_INT_STACK
#undef _WRS_SPLIT_STACKS
#else
/*
* Old split interrupt stack method...,
* not used when OSM stack protection is
* enabled...
*/
/* from usrLib.c */
#define _WRS_SVC_INT_STACK
#define _WRS_IRQ_INT_STACK
#define _WRS_DUAL_INT_STACK
/* from kernelLib.c */
/*
* The ARM family uses 3 interrupt stacks. The ratio of the sizes of
* these stacks is dependent on the interrupt structure of the board
* and so is handled in the BSP code. Note that FIQ is now external to
* VxWorks.
*/
#define _WRS_SPLIT_STACKS {if (_func_armIntStackSplit != NULL) \
(_func_armIntStackSplit)(vxIntStackBase, intStackSize);}
#endif /* _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK */
/* from xdr_float.c */
#define FLOAT_NORM
/* Set to force the use of the big-endian call to XDR_GETLONG() */
#define _WRS_XDR_FORCE_BE
#define _WRS_ENABLE_IDLE_INTS {intCpuUnlock(0);}
/* macros for getting frame and return PC from a jmp_buf */
#define _WRS_FRAMEP_FROM_JMP_BUF(env) ((char *) (env)[0].reg.reg_sp)
#define _WRS_RET_PC_FROM_JMP_BUF(env) ((INSTR *) (env)[0].reg.reg_pc)
#ifdef __cplusplus
}
#endif
#include <arch/arm/archArmCommon.h>
#ifdef __cplusplus
extern "C" {
#endif
/* variants that support the clz instruction, "count leading zeroes" */
#if ((CPU == XSCALE) || (CPU == ARMARCH6) || (CPU == ARMARCH5) \
|| (CPU == ARMARCH7) || (CPU == ARMARCH7_T2) || (CPU == ARMARCH7M))
#define _WRS_CPU_HAS_CLZ_INSTR
#endif /* CPU = XSCALE ... ARMARCH7_T2 */
#ifndef _ASMLANGUAGE
#ifdef _WRS_CPU_HAS_CLZ_INSTR
/* optimize FFS(x) in network code for CPUs supporting clz instruction */
#undef FFS
#define FFS(x) (31 - _countLeadingZeroes(x))
#if defined (__GNUC__)
/*
* Return the number of zero bits in bit positions more significant
* than the first set bit.
* We don't have to handle the x=0 case, this is only called
* when x != 0. Returns a value y in the range 31 >= y >= 0.
* 0 indicates the most significant bit.
*/
static __inline__ unsigned int _countLeadingZeroes
(
unsigned int x
)
{
unsigned int y;
__asm__ ("clz %0, %1"
: "=r" (y)
: "r" (x)
);
return y;
}
#elif defined (_DIAB_TOOL)
#pragma pure_function _countLeadingZeroes
__asm unsigned int _countLeadingZeroes
(
unsigned int x
)
{
% reg x
! "r0"
clz r0, x
}
#else /* !_DIAB_TOOL */
/* Unknown compiler, use default */
#undef FFS
#define FFS(x) (ffsMsb(x) - 1)
#endif /* _DIAB_TOOL */
#else /* _WRS_CPU_HAS_CLZ_INSTR */
/* use default */
#undef FFS
#define FFS(x) (ffsMsb(x) - 1)
#endif /* _WRS_CPU_HAS_CLZ_INSTR */
#endif /* ! _ASMLANGUAGE */
/* End PAL */
#ifdef __cplusplus
}
#endif
#endif /* __INCarchArmh */
vxworks-6.9/target/h/arch/arm/archArmCommon.h
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/* archArmCommon.h - common Arm architecture specific header */
/*
* Copyright (c) 2003-2004, 2006-2007, 2010, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01l,21mar12,jpb Updated for POSIX namespace isolation conformance (part of
defect Defect WIND000307800).
01k,22jul10,jdw Update size of INSTR for Thumb2
01j,09jun10,fao add SWAP32_BE8 and SWAP16_BE8 macro.
01i,04may07,zl updated portable library build configuration.
01h,02feb06,mil Updated for POSIX namespace conformance.
01g,08sep04,scm move INSTR from archArm.h
01e,25aug04,scm move to portable trcLib...
01d,03aug04,scm Enable Coprocessor Abstraction, disable Portable trcLib.
01c,25nov03,pes Move setting of _BYTE_ORDER macro into archArmCommon.h
01b,12nov03,job Moved some blib stuff from archArm.h
01a,11nov03,pes written.
*/
#ifndef __INCarchArmCommonh
#define __INCarchArmCommonh
#ifdef __cplusplus
extern "C" {
#endif
#if defined(ARMEB) || defined(__ARMEB__)
#define _BYTE_ORDER _BIG_ENDIAN
#else
#define _BYTE_ORDER _LITTLE_ENDIAN
#endif
#ifndef _ASMLANGUAGE
#if ((ARM_THUMB) || (ARM_THUMB2))
typedef unsigned short _Vx_INSTR; /* 16 bit instructions */
#else /* ((ARM_THUMB) || (ARM_THUMB2)) */
typedef unsigned long _Vx_INSTR; /* 32 bit word-aligned instructions */
#endif /* ((ARM_THUMB) || (ARM_THUMB2)) */
#endif /* !_ASMLANGUAGE */
#if !defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE) && \
!defined(_POSIX_AEP_RT_CONTROLLER_C_SOURCE)
#ifdef ARMBE8
#define SWAP32_BE8(x) ((((x) & 0x000000ff) << 24) | \
(((x) & 0x0000ff00) << 8) | \
(((x) & 0x00ff0000) >> 8) | \
(((x)) >> 24))
#define SWAP16_BE8(x) ((((x) & 0x00ff0000) >> 8) | \
(((x)) >> 24))
#else
#define SWAP32_BE8(x) x
#define SWAP16_BE8(x) x
#endif /* ARMBE8 */
/* from bLib.c */
#define _WRS_BLIB_ALIGNMENT 3 /* quad byte alignment mask */
#define _WRS_IMPROVED_PORTABLE_SWAB
/* Enable Coprocessor Abstraction. Must do all or none. */
#define _WRS_PAL_COPROC_LIB
#ifndef _ASMLANGUAGE
typedef _Vx_INSTR INSTR;
#endif /* !_ASMLANGUAGE */
#endif /* !_POSIX_xxx_SOURCE */
#ifdef __cplusplus
}
#endif
#endif /* __INCarchArmCommonh */
vxworks-6.9/target/h/arch/arm/arm-m/arm-m.h
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/* arm-m.h - ARM CPU registers and flags for ARM-M architecture */
/*
* Copyright (c) 2012-2013 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01f,01aug13,yjw add cache support
01e,03aug12,jdw Add boot macro _WRS_ARM_BOOT_THUMB2
01d,06jun12,j_b add core control registers and initialization values
01c,29may12,j_b add control and configuration registers
01b,24may12,m_h Add CPUID address
01a,03feb12,jdw Created
*/
#ifndef __INCarm_mh
#define __INCarm_mh
#ifndef _ASMLANGUAGE
extern int cacheArchAlignSize;
#endif /* _ASMLANGUAGE */
#undef _CACHE_ALIGN_SIZE
#define _CACHE_ALIGN_SIZE cacheArchAlignSize
/* Define Arch features which are supported by ARM-M */
/* ARM-M only operates in Thumb2 mode */
#define ARM_THUMB2 TRUE
#define PORTABLE
/* multiple cache libraries */
#define _ARCH_MULTIPLE_CACHELIB TRUE
/* ARMv7-M support exclusive load/store */
#define ARM_HAS_LDREX_STREX TRUE
#define ARM_HAS_HALFWORD_INSTRUCTIONS TRUE
/* MPU is optional on some ARM-M cores */
#define ARM_HAS_NO_MMU TRUE
/* ARM-M always boots in Thumb2 mode */
#define _WRS_ARM_BOOT_THUMB2 TRUE
#define _WRS_ARCH_HAS_CPU_PWR_MGMT
/* bits in the PSR */
#define Q_BIT (1<<27)
#define V_BIT (1<<28)
#define C_BIT (1<<29)
#define Z_BIT (1<<30)
#define N_BIT (1<<31)
#define T_BIT (1<<24)
/*
* On entry to an exception the processor will use xPSR bit 9
* to indicate if the SP has been aligned to an 8-byte boundary
*/
#define PSR_STK_ALIGN (1<<9)
/* masks for getting bits from PSR */
#define MASK_EXC_NUM 0x000001FF
#define MASK_ICIIT 0x0600FC00
#define MASK_GE 0x000F0000
#define MASK_T 0x01000000
#define MASK_CC 0xF8000000
/* PRIMASK, FAULTMASK, & BASEMASK fields */
#define PRIMASK_PM 0x00000001
#define FAULTMASK_FM 0x00000001
#define MASK_BASEPRI 0x000000FF
/* Bits in EXC_RETURN */
#define EXC_RTN_BASE 0xFFFFFFF1
#define EXC_RTN_MODE_THREAD 0x00000008
#define EXC_RTN_MODE_HANDLER 0x00000000
#define EXC_RTN_STACK_PROCESS 0x00000004
#define EXC_RTN_STACK_MAIN 0x00000000
#define MASK_EXC_RTN_MODE 0x00000008
#define MASK_EXC_RTN_STACK 0x00000004
/*
* System Control Block Registers
*/
/* CPU ID Base Register */
#define CORTEXM_CPUID_BASE_REGISTER (0xE000ED00)
/* Interrupt Controller Type Register */
#define CORTEXM_ICTR (0xE000E004)
#define CORTEXM_ICTR_INTNUM_MASK (0xF) /* # of interrupt lines field */
#define CORTEXM_ICTR_INTNUM_MAX (0xF) /* # of interrupt lines field max */
/* Auxiliary Control Register - usage is implementation-defined/core-specific */
#define CORTEXM_ACTLR (0xE000E008)
/* Interrupt Controller State Register */
#define CORTEXM_ICSR (0xE000ED04)
/* Vector Table Offset Register */
#define CORTEXM_VTOR (0xE000ED08)
#define CORTEXM_VTOR_MASK (0xFFFFFF80) /* reserved bits 6:0 */
/*
* Application Interrupt and Reset Control Register
*
* Note that the proper access key must be included in a write to this
* regsiter or the write is ignored.
*/
#define CORTEXM_AIRCR (0xE000ED0C)
#define CORTEXM_AIRCR_VECTKEY 0x05FA0000 /* Access Key for writes */
#define CORTEXM_AIRCR_VECTKEY_MASK 0xFFFF0000 /* (0xFA05 is the read value) */
#define CORTEXM_AIRCR_PRIGROUP_SHIFT 8 /* Priority Group */
#define CORTEXM_AIRCR_PRIGROUP_MASK (0x7 << CORTEXM_AIRCR_PRIGROUP_SHIFT)
/* System Control and Register */
#define CORTEXM_SCR (0xE000ED10)
/* Configuration and Control Register */
#define CORTEXM_CCR (0xE000ED14)
#define CORTEXM_CCR_DIV0TRP (0x00000010) /* divide by zero trap enable */
#define CORTEXM_CCR_STKALIGN (0x00000200) /* 8-byte stacking align enable */
/*
* System Handler Priority Level Registers
* (aka System Exception Priority Level Registers)
*/
#define CORTEXM_SHPR1 (0xE000ED18) /* Pri lvl for Exceptions 4-7 */
#define CORTEXM_SHPR2 (0xE000ED1C) /* Pri lvl for Exceptions 8-11 */
#define CORTEXM_SHPR3 (0xE000ED20) /* Pri lvl for Exceptions 12-15 */
/*
* Note: SHPR actually starts with PRI_4. There is no such thing as PRI_0 but
* this makes the address calculation easier.
*/
#define CORTEXM_SHPR_PRI_0 (0xE000ED14)
#define CORTEXM_SHPR_PRI_15 (0xE000ED23)
#define CORTEXM_SHPR_PENDSV (CORTEXM_SHPR_PRI_14)
#define CORTEXM_SHPR_SYSTICK (CORTEXM_SHPR_PRI_15)
/* system priority register address, calculated by exception # (= offset) */
#define CORTEXM_SHPR_PRI_BYTE(n) (CORTEXM_SHPR_PRI_0 + (n))
/* System Handler Control and State Register */
#define CORTEXM_SHCSR (0xE000ED24)
#define CORTEXM_SHCSR_USGFLT_EN (0x00040000) /* Usage Fault Enable bit */
#define CORTEXM_SHCSR_BUSFLT_EN (0x00020000) /* Bus Fault Enable bit */
#define CORTEXM_SHCSR_MEMFLT_EN (0x00010000) /* Memory Mgt Fault Enable bit */
#define CORTEXM_SHCSR_SVC_PEND (0x00008000) /* SVCall Pending bit */
#define CORTEXM_SHCSR_BUSFLT_PEND (0x00004000) /* Bus Fault Pend bit */
#define CORTEXM_SHCSR_MEMFLT_PEND (0x00002000) /* Memory Mgt Pend bit */
#define CORTEXM_SHCSR_USGFLT_PEND (0x00001000) /* Usage Fault Pend bit */
#define CORTEXM_SHCSR_SYSTCK_ACT (0x00000800) /* SysTick Active bit */
#define CORTEXM_SHCSR_PENDSV_ACT (0x00000400) /* PendSV Active bit */
#define CORTEXM_SHCSR_DBGMON_ACT (0x00000100) /* Debug Monitor Active */
#define CORTEXM_SHCSR_SVC_ACT (0x00000080) /* SVCall Active */
#define CORTEXM_SHCSR_USGFLT_ACT (0x00000008) /* Usage Fault Active */
#define CORTEXM_SHCSR_BUSFLT_ACT (0x00000002) /* Usage Fault Active */
#define CORTEXM_SHCSR_MEMFLT_ACT (0x00000001) /* Usage Fault Active */
/* Debug Exception and Monitor Control Register */
#define CORTEXM_DEMCR (0xE000EDFC)
#define CORTEXM_DEMCR_MON_STEP (0x00040000)
#define CORTEXM_DEMCR_MON_PEND (0x00020000)
#define CORTEXM_DEMCR_MON_EN (0x00010000)
/* ROM table for debug */
#define CORTEXM_ROM_TABLE (0xE00FF000)
#define CORTEXM_ROM_TABLE_FPB_OFFSET (0x00000008)
#define CORTEXM_FPB_VALID (0xFFF03003)
/* FlashPatch Control Register */
#define CORTEXM_FP_CTRL (0xE0002000)
#define CORTEXM_FP_CTRL_ENABLE (3)
/* FlashPatch Comparatorregister */
#define CORTEXM_FP_COMP0 (0xE0002008)
/*
* Configurable Fault Status Register
* This register includes the:
* - 8-bit Memory Management Fault Status Register
* - 8-bit Bus Fault Status Register; and
* - 16-bit Usage Fault Status Register;
*/
#define CORTEXM_CFSR (0xE000ED28)
#define CORTEXM_BFSR_SHIFT (8) /* Bus Fault Status bit shift */
#define CORTEXM_UFSR_SHIFT (16) /* Usage Fault Status bit shift */
#define CORTEXM_DFSR (0xE000ED30)
#define CORTEXM_HALTED (0x1) /* trace */
#define CORTEXM_BKPT (0x2) /* FPB break point */
#define CORTEXM_MMFSR CORTEXM_CFSR /* Mem Manage Fault Status byte */
#define CORTEXM_MMFSR_FARVALID (0x80) /* fault address valid mask */
#define CORTEXM_BFSR (0xE000ED29) /* Bus Fault Status byte */
#define CORTEXM_BFSR_FARVALID (0x80) /* fault address valid mask */
#define CORTEXM_UFSR (0xE000ED2A) /* Usage Fault Status halfword */
/* Usage Fault Status fields */
#define CORTEXM_UFSR_DIV0 (0x00000200) /* Divide by Zero */
#define CORTEXM_UFSR_UNALIGN (0x00000100) /* Unaligned Access */
#define CORTEXM_UFSR_NOCP (0x00000008) /* Coprocessor Access */
#define CORTEXM_UFSR_INVPC (0x00000004) /* Invalid EXC_RETURN */
#define CORTEXM_UFSR_INVSTATE (0x00000002) /* Invalid State */
#define CORTEXM_UFSR_UNDEF (0x00000001) /* Undefined Instruction */
/* Hard Fault Status Register */
#define CORTEXM_HFSR (0xE000ED2C)
#define CORTEXM_HFSR_FORCED (0x40000000) /* escalated configurable fault */
/* (bus/mem mgt/usage fault) */
#define CORTEXM_HFSR_CLRALL (0xC0000002) /* clear all Hard faults */
/* Memory Manage Fault Address Register */
#define CORTEXM_MMFAR (0xE000ED34)
/* Bus Fault Address Register */
#define CORTEXM_BFAR (0xE000ED38)
/* MPU Control Register */
#define CORTEXM_MPU_CTRL (0xE000ED94)
/* Software Trigger Interrupt Register */
#define CORTEXM_STIR (0xE000EF00)
#define INVALID_INST (0xFF00FF00) /* invalid opcode */
#endif /* __INCarm_mh */
vxworks-6.9/target/h/arch/arm/arm-m/esfArm-m.h
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/* esfArm-m.h - ARM exception stack frames */
/*
* Copyright (c) 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01c,10may12,j_b fix tabs/spacing
01b,03may12,j_b replace "-" in filename include macro
01a,03apr12,j_b created from target/h/arch/arm/esfArm.f version 01b
*/
#ifndef __INCesfArm_mh
#define __INCesfArm_mh
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
/*
* The Exception Stack Frame
* On ARMv7-M, this is faked by a stub and the pointer
* passed back points to the PC and PSR at the end of the
* register structure. If that changes, so must this.
*
* I.E., REG_SET struct & ESF struct 'overlap' on last 4
* elements of REG_SET (pc, psr, primask and basepri).
*/
typedef struct
{
INSTR *pc; /* program counter */
ULONG psr; /* combined A/I/E PSR */
ULONG basepri; /* BASEPRI */
ULONG demcr; /* MON_STEP in DEMCR */
ULONG primask; /* PRIMASK */
ULONG faultmask; /* FAULTMASK */
ULONG control; /* CONTROL */
UINT32 vecNum; /* exception number */
} ESF;
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCesfArm_mh */
vxworks-6.9/target/h/arch/arm/arm-m/excArmLib-m.h
+160
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/* excArmLib-m.h - ARMv7-M exception library header file */
/*
* Copyright (c) 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01d,05sep12,rec add excClearFault prototype
01c,24may12,j_b add fault status to EXC_INFO
01b,22may12,jdw Add exception vector offset mapping for scopetools
01a,14may12,m_h create from target/h/arch/arm/excArmLib.h version 01f
*/
#ifndef __INCexcArmLib_mh
#define __INCexcArmLib_mh
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
/*
* NOTE: if this structure changes, the TCB offsets in h/private/taskLibP.h
* must be updated. See also taskLib.h.
*/
typedef struct
{
UINT32 valid; /* flags indicate following fields are valid */
UINT32 vecNum; /* exception number */
INSTR * pc; /* PC */
UINT32 psr; /* combined A/I/E PSR */
UINT32 primask; /* PRIMASK */
UINT32 faultmask; /* FAULTMASK */
UINT32 basepri; /* BASEPRI */
UINT32 control; /* Control Register */
UINT32 sysHandlrStat; /* System Handler Control and State Register */
UINT32 hardFltStat; /* Hard Fault Status Register */
UINT32 configFltStat; /* Configurable Fault Status Register */
UINT32 memFltAddr; /* Memory Manage Fault Address Register */
UINT32 busFltAddr; /* Bus Fault Address Register */
} EXC_INFO;
extern FUNCPTR excExcepHook; /* add'l rtn to call when exceptions occur */
extern VOIDFUNCPTR _func_excBreakpoint; /* called to handle breakpoints */
extern void excVecBaseSet (UINT32 base); /* non-zero exception base address */
extern STATUS excIntConnect (VOIDFUNCPTR * vector, VOIDFUNCPTR routine);
extern void excVecSet (FUNCPTR * vector, FUNCPTR function);
extern FUNCPTR excVecGet (FUNCPTR * vector);
extern STATUS excVecPrioSet (VOIDFUNCPTR * vector, UINT8 priority);
extern STATUS excVecPrioGet (VOIDFUNCPTR * vector, UINT8 * pPriority);
extern void excClearFault (void);
#endif /* ASMLANGUAGE */
/* exception information valid bits */
#define EXC_INFO_VECNUM 0x01 /* vector is valid */
#define EXC_INFO_PC 0x02 /* PC is valid */
#define EXC_INFO_XPSR 0x04 /* xPSR is valid */
#define EXC_INFO_PRIMASK 0x08 /* PRIMASK is valid */
#define EXC_INFO_FAULTMASK 0x10 /* FAULTMASK is valid */
#define EXC_INFO_BASEPRI 0x20 /* BASEPRI is valid */
#define EXC_INFO_CONTROL 0x40 /* Control Register is valid */
#define EXC_INFO_SYSHDLRSTAT 0x80 /* System Handler Ctrl/State is valid */
#define EXC_INFO_HRDFLTSTAT 0x100 /* Hard Fault Status is valid */
#define EXC_INFO_CFGFLTSTAT 0x200 /* Configurable Fault Status is valid */
#define EXC_INFO_MEMFLTADDR 0x400 /* Mem Manage Fault Address is valid */
#define EXC_INFO_BUSFLTADDR 0x800 /* Bus Fault Address is valid */
#define EXC_INFO_ALL_VALID 0xFFF /* all EXC_INFO fields are valid */
/*
* Exception Numbers
*
* Note there is no Exception number 0. If the IPSR contains zero then we are
* in thread mode and therefore not servicing an exception or interrupt.
*/
#define EXC_NUM_THREAD_MODE 0 /* IPSR is 0 when in thread mode */
#define EXC_NUM_RESET 1 /* Reset */
#define EXC_NUM_NMI 2 /* Nonmaskable Interrupt */
#define EXC_NUM_HARD_FAULT 3 /* unimplemented fault handler */
#define EXC_NUM_MEM_MANAGE 4 /* MPU Violation */
#define EXC_NUM_BUS_FAULT 5 /* Bus Error */
#define EXC_NUM_USAGE_FAULT 6 /* Program error or coprocessor */
#define EXC_NUM_SVCALL 11 /* Supervisor Call */
#define EXC_NUM_DEBUG_MONITOR 12 /* Debug Monitor */
#define EXC_NUM_PENDSV 14 /* PendSV */
#define EXC_NUM_SYSTICK 15 /* System Tick Timer */
#define EXC_NUM_IRQ_BASE 16 /* First External Interrupt */
#define EXC_NUM_IRQ(num) (EXC_NUM_IRQ_BASE + (num))
#define EXC_NUM_LAST_IRQ 511
/* Exception Vectors
*
* The values at these offsets are 32-bit addresses of exception handlers.
* This is different from traditional arm architectures (such as ARMv7) which
* expect branch instructions or some other executable instructions.
*
* Note: the first entry (entry 0) in the exception vector table is the
* initial value of the stack pointer after reset, and not an exception vector
* address. Although not actually an exception vector, it is included here
* for completeness.
*/
#define EXC_OFF_INITIAL_SP 0x00
#define EXC_OFF_RESET (EXC_NUM_RESET * 4)
#define EXC_OFF_NMI (EXC_NUM_NMI * 4)
#define EXC_OFF_HARD_FAULT (EXC_NUM_HARD_FAULT * 4)
#define EXC_OFF_MEM_MANAGE (EXC_NUM_MEM_MANAGE * 4)
#define EXC_OFF_BUS_FAULT (EXC_NUM_BUS_FAULT * 4)
#define EXC_OFF_USAGE_FAULT (EXC_NUM_USAGE_FAULT * 4)
#define EXC_OFF_SVCALL (EXC_NUM_SVCALL * 4)
#define EXC_OFF_DEBUG_MONITOR (EXC_NUM_DEBUG_MONITOR * 4)
#define EXC_OFF_PENDSV (EXC_NUM_PENDSV * 4)
#define EXC_OFF_SYSTICK (EXC_NUM_SYSTICK * 4)
#define EXC_OFF_IRQ_BASE (EXC_NUM_IRQ_BASE * 4)
#define EXC_OFF_IRQ(num) (EXC_OFF_IRQ_BASE + ((num)*4))
#define EXC_OFF_LAST_IRQ EXC_OFF_IRQ(EXC_NUM_LAST_IRQ)
/* Exception Vector Base */
#define ARM_EXC_VEC_BASE 0x00
/*
* Map the traditional ARM definition to the ARM-M exception offset.
*/
/* Scope tools needs to know which vector handles undefined instructions. */
#define EXC_OFF_UNDEF (EXC_NUM_USAGE_FAULT)
/* ObjVerify needs to know which vector handles Page Faults */
#define EXC_OFF_DATA (EXC_NUM_MEM_MANAGE)
#ifdef __cplusplus
}
#endif
#endif /* __INCexcArmLib_mh */
vxworks-6.9/target/h/arch/arm/arm-m/intArmLib.h
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/* intArmLib.h - ARM-specific interrupt library header file */
/*
* Copyright (c) 2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01a,12apr12,jdw created.
*/
#ifndef __INCintArmLibh
#define __INCintArmLibh
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _WRS_ENABLE_IRQ_TRACING
/*
* For tracing we can define some "no-op" instructions which can be
* inserted and identified in the ICE trace buffer.
*/
#define WRS_ICE_TRACE_IRQ_LOCK orr r5,r5,r5
#define WRS_ICE_TRACE_IRQ_UNLOCK orr r6,r6,r6
#else /* _WRS_ENABLE_IRQ_TRACING */
#define WRS_ICE_TRACE_IRQ_LOCK
#define WRS_ICE_TRACE_IRQ_UNLOCK
#endif /* _WRS_ENABLE_IRQ_TRACING */
#ifndef _ASMLANGUAGE
/* inline intCpuLock()/intCpuUnlock() and intCpuMicroLock/Unlock() */
#if defined (__DCC__)
__asm volatile int _inline_intCpuLock ()
{
! "r0"
mrs r0, BASEPRI /* get current status */
mov r1, #0x10
mrs BASEPRI, r1
WRS_ICE_TRACE_IRQ_LOCK
}
__asm volatile void _inline_intCpuUnlock (int key)
{
% reg key; lab label ! "r0" /* input: key in r0 */
mrs BASEPRI, r0
WRS_ICE_TRACE_IRQ_UNLOCK
}
#elif defined (__GNUC__)
static __inline__ int _inline_intCpuLock (void)
{
int key;
__asm__ volatile
(
"mrs r0, BASEPRI; " /* get current status */
"mov r1, #0x10 " /* set new status */
"mrs BASEPRI, r1 "
: "=&r" (key) /* output: key is %0 */
: /* no input */
: "r0", "r1"
);
return key;
}
static __inline__ void _inline_intCpuUnlock (int key)
{
__asm__ volatile
(
"mrs BASEPRI, r0 " /* set new status */
: "r" (key) /* input: key is %0 */
: "r0" /* r0, r1 clobbered; memory */
/* clobber for code barrier */
);
}
#endif /* __DCC__ */
/*
* For ARM-M these functions are identical
*/
#define _inline_intCpuMicroLock() _inline_intCpuLock()
#define _inline_intCpuMicroUnlock(key) _inline_intCpuUnlock(key)
/* functions in intArchLib.c and intALib.s */
extern STATUS intArchConnect (VOIDFUNCPTR * vector,
VOIDFUNCPTR routine, int argument);
extern STATUS intArchDisconnect (VOIDFUNCPTR * vector,
VOIDFUNCPTR routine, int argument);
extern int intLevelSet (int level);
extern STATUS intEnable (int level);
extern STATUS intDisable (int level);
extern unsigned int getBasePri( void );
extern unsigned int setBasePri( unsigned int level );
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCintArmLibh */
vxworks-6.9/target/h/arch/arm/arm-m/regsArm-m.h
+106
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/* regsArm-m.h - ARMv7-M registers */
/*
* Copyright (c) 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01e,19jul12,jdw Add missing TCB offset register definitions
01d,23may12,jdw Add PRIMASK and BASEPRI offsets
01c,10may12,j_b fix tabs/spacing
01b,03may12,j_b replace "-" in filename include macro
01a,03apr12,j_b created from target/h/arch/arm/regsArm.f version 01f
*/
#ifndef __INCregsArm_mh
#define __INCregsArm_mh
#ifdef __cplusplus
extern "C" {
#endif
#define GREG_NUM 15 /* has 15 32-bit general registers */
#ifndef _ASMLANGUAGE
/*
* REG_SET - ARMv7-M Register set
* Note that the exception stack frame relies on the order of items
* in this so don't change this without changing the ESF and the stub
* in excALib which creates it.
*/
typedef struct /* REG_SET - ARMv7-M register set */
{
ULONG r[GREG_NUM]; /* general purpose registers 0-14 */
INSTR *pc; /* program counter */
ULONG psr; /* combined A/I/E PSR */
ULONG basepri; /* BASEPRI */
ULONG demcr; /* MON_STEP in DEMCR */
} REG_SET;
typedef struct wind_cpu_state
{
REG_SET regs;
} WIND_CPU_STATE;
#define fpReg r[11] /* frame pointer */
#define spReg r[13] /* stack pointer */
#define lrReg r[14] /* link reg pointer */
#define reg_pc pc /* program counter */
#define reg_lr lrReg /* link reg pointer */
#define reg_sp spReg /* stack pointer */
#define reg_fp fpReg /* frame pointer */
#endif /* _ASMLANGUAGE */
#define ARM_REG_SIZE 4
#define REG_SET_G_REG_BASE 0x00 /* data reg's base offset to REG_SET */
#define REG_SET_G_REG_OFFSET(n) (REG_SET_G_REG_BASE + (n)*ARM_REG_SIZE)
#define REG_SET_PC_OFFSET (REG_SET_G_REG_OFFSET(GREG_NUM))
#define REG_SET_CPSR_OFFSET (REG_SET_PC_OFFSET + ARM_REG_SIZE)
#define REG_SET_BASEPRI_OFFSET (REG_SET_CPSR_OFFSET + ARM_REG_SIZE)
#define REG_SET_DEMCR_OFFSET (REG_SET_BASEPRI_OFFSET + ARM_REG_SIZE)
#define PC_OFFSET REG_SET_PC_OFFSET
/* PAL additions */
/* moved here from h/private/taskLibP.h */
#define WIND_TCB_R0 WIND_TCB_REGS
#define WIND_TCB_R1 (WIND_TCB_R0+4*1)
#define WIND_TCB_R2 (WIND_TCB_R0+4*2)
#define WIND_TCB_R3 (WIND_TCB_R0+4*3)
#define WIND_TCB_R4 (WIND_TCB_R0+4*4)
#define WIND_TCB_R5 (WIND_TCB_R0+4*5)
#define WIND_TCB_R6 (WIND_TCB_R0+4*6)
#define WIND_TCB_R7 (WIND_TCB_R0+4*7)
#define WIND_TCB_R8 (WIND_TCB_R0+4*8)
#define WIND_TCB_R9 (WIND_TCB_R0+4*9)
#define WIND_TCB_R10 (WIND_TCB_R0+4*10)
#define WIND_TCB_R11 (WIND_TCB_R0+4*11)
#define WIND_TCB_R12 (WIND_TCB_R0+4*12)
#define WIND_TCB_SP (WIND_TCB_R0+4*13)
#define WIND_TCB_LR (WIND_TCB_R0+4*14)
#define WIND_TCB_PC (WIND_TCB_R0+4*15)
#define WIND_TCB_CPSR (WIND_TCB_PC+4)
#define WIND_TCB_BASEPRI (WIND_TCB_PC+8)
#define WIND_TCB_DEMCR (WIND_TCB_PC+12)
/* End PAL */
#ifdef __cplusplus
}
#endif
#endif /* __INCregsArm_mh */
vxworks-6.9/target/h/arch/arm/arm-m/vfpArmLib.h
+196
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/* vfpArmLib.h - Arm Version of Vector Floating-Point Include File */
/*
* Copyright (c) 2013 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01a,07may13,c_t VFPv4 SP written based on standard version
*/
#ifndef __INCvfpArmLibSph
#define __INCvfpArmLibSph
#ifdef __cplusplus
extern "C" {
#endif
/*
* for cortex M the following register are memory mapped and the addresses
* are architectural defined.
*/
/* Coprocessor Access Control Register, CPACR, enable CP10 & CP11 for VFP */
#define CPACR (0xE000ED88)
#define CPACR_CP_FULL(x) (3<<(2*(x))) /* 0b11 : Full access for this cp */
/* Floating-Point Context Control Register, FPCCR */
#define FPCCR (0xE000EF34)
#define FPCCR_ASPEN (1<<31) /* enable auto FP context stacking */
#define FPCCR_LSPEN (1<<30) /* enable lazy FP context stacking */
#define FPCCR_MONRDY (1<<8)
#define FPCCR_BFRDY (1<<6)
#define FPCCR_MMRDY (1<<5)
#define FPCCR_HFRDY (1<<4)
#define FPCCR_THREAD (1<<3) /* allocated FP stack in thread */
#define FPCCR_USER (1<<1) /* allocated FP stack in priviledged */
#define FPCCR_LSPACT (1<<0) /* lazy stacking is active */
/* Floating-Point Context Address Register, FPCAR */
/* this register contains the FP context address in the exception stack */
#define FPCAR (0xE000EF38)
/* Floating-Point Default Status Control Register, FPDSCR */
/*
* set the initial value of FPSCR, however we can set it manually to FPSCR
* when creating the VFP task, so let it as is at this time.
*/
#define FPDSCR (0xE000EF3C)
#define FPDSCR_AHP (1<<26)
#define FPDSCR_DN (1<<25)
#define FPDSCR_FZ (1<<24)
#define FPDSCR_RMODE 0x00C00000
#define FPDSCR_RN 0x00000000 /* round to nearest */
#define FPDSCR_RP 0x00400000 /* round toward plus infinity */
#define FPDSCR_RM 0x00800000 /* round toward minus infinity */
#define FPDSCR_RZ 0x00C00000 /* round toward zero */
/* Media and FP Feature Register 0, MVFR0 & Register 1, MVFR1*/
/* these read only registers are using to detect feature that supported */
#define MVFR0 (0xE000EF40)
#define MVFR0_SP_MSK (0x000000F0) /* bit 4~7 = 0x2, support sp */
#define MVFR0_SP_EN (0x20) /* bit 4~7 = 0x2, support sp */
#define MVFR1 (0xE000EF44)
/* FPSCR (Floating Status and Control Register) bit definitions for VFPv4SP */
/*
* At the time of implementation bits 27, 21-8, and 6-5,
* are described as reserved, one must employ
* read/modify/write techniques when handling the FPSCR in order
* to ensure that these bits are not modified...
*/
#define FPSCR_N_BIT (1<<31) /* less than result */
#define FPSCR_Z_BIT (1<<30) /* equal result */
#define FPSCR_C_BIT (1<<29) /* equal, greater than, or unordered result */
#define FPSCR_V_BIT (1<<28) /* unordered result */
#define FPSCR_AHP (1<<26)
#define FPSCR_DN_BIT (1<<25) /* Default NaN mode control */
#define FPSCR_DN_MSK FPSCR_DN_BIT
#define FPSCR_DN_ENABLE FPSCR_DN_BIT
#define FPSCR_DN_DISABLE 0x00000000
#define FPSCR_FZ_BIT (1<<24) /* flush to zero mode control */
#define FPSCR_FZ_MSK FPSCR_FZ_BIT
#define FPSCR_FZ_ENABLE FPSCR_FZ_BIT
#define FPSCR_FZ_DISABLE 0x00000000
/* Cumulative Exception Bits */
#define FPSCR_IDC_BIT (1<<7) /* Input Subnormal */
#define FPSCR_IXC_BIT (1<<4) /* Inexact */
#define FPSCR_UFC_BIT (1<<3) /* Underflow */
#define FPSCR_OFC_BIT (1<<2) /* Overflow */
#define FPSCR_DZC_BIT (1<<1) /* Division By Zero */
#define FPSCR_IOC_BIT (1<<0) /* Invalid Operation */
/* Round Mode Control Bits */
#define FPSCR_RMODES_MSK 0x00C00000 /* round mode */
#define FPSCR_RN 0x00000000 /* round to nearest */
#define FPSCR_RP 0x00400000 /* round toward plus infinity */
#define FPSCR_RM 0x00800000 /* round toward minus infinity */
#define FPSCR_RZ 0x00C00000 /* round toward zero */
#ifdef _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO
#define FPSCR_INIT FPSCR_DN_MSK
#else /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
#define FPSCR_INIT (FPSCR_DN_MSK | FPSCR_FZ_BIT)
#endif /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
#define VFPREG_SET VFP_CONTEXT
#define _VFP_ALIGN_SIZE 8 /* Not sure if this is needed */
/* vfpv4 sp only support D16/S32. */
#define VFP_DGPR_NUM 16 /* 16-double precision general purpose */
#define VFP_SGPR_NUM 32 /* 32-single precision general purpose */
/* FP_CONTEXT structure offsets */
#define VFP_FPSCR 0x00
#define VFP_PAD -
#define VFP_GPR 0x08 /* OFFSET(FP_CONTEXT, vfp_gpr[0]) */
#define VFP_GPR_OFFSET(n) (VFP_GPR + (n)*4) /* vfp_gpr[n]) */
#ifndef _ASMLANGUAGE
/* standard interface to fp lib. */
/* vfpv4 sp context is different with standard vfp. */
typedef struct vfpContext /* VFP Context */
{
UINT32 fpscr; /* status and control register */
UINT32 pad; /* pad to match 8 byte alignment */
UINT32 vfp_gpr[VFP_SGPR_NUM]; /* general purpose registers */
/* TOTAL */
} WRS_PACK_ALIGN(_VFP_ALIGN_SIZE) VFP_CONTEXT;
/* function declarations */
IMPORT void vfpArchInit (void);
IMPORT void vfpArchTaskCreateInit (VFP_CONTEXT *pDspContext);
IMPORT void vfpSave (VFP_CONTEXT *);
IMPORT void vfpRestore (VFP_CONTEXT *);
IMPORT STATUS vfpProbe (void);
IMPORT STATUS vfpEnable (void);
IMPORT STATUS vfpDisable (void);
IMPORT VFP_CONTEXT * vfpCtxCreate (int);
IMPORT STATUS vfpCtxDelete (VFP_CONTEXT *);
IMPORT void vfpCtxShow (VFP_CONTEXT *);
void vfpRegsToCtx (VFPREG_SET *, VFP_CONTEXT *);
void vfpCtxToRegs (VFP_CONTEXT *, VFPREG_SET *);
#ifdef _WRS_HW_VFP_SUPPORT
IMPORT int vfpIsEnabled (void);
IMPORT int vfpHasException (void);
IMPORT STATUS vfpProbeSup (void);
IMPORT UINT32 vfpFpSidGet (void);
IMPORT UINT32 vfpFpScrGet (void);
IMPORT void vfpFpScrSet (UINT32);
#endif
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCvfpArmLibSph */
vxworks-6.9/target/h/arch/arm/arm.h
+505
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@@ -0,0 +1,505 @@
/* arm.h - ARM CPU flags etc */
/*
* Copyright (c) 1996-2006, 2008-2014 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
17apr14,c_l add the write protection of L2 page table. (VXW6-73478)
02l,16mar13,yjw Update for ARMv7M
02k,08oct12,jdw Update FAST MATH for ARMARCH7
02j,14sep12,j_b fix whitespace issues
02i,28jun12,j_b add Cortex-A15 cache support
02h,09feb12,jdw Update definitions for __ieee_status(), WIND00332894
02g,01feb12,rec WIND00329076 - cleanup assembly macros to be consistent
02f,11aug11,jdw Add support for ARMv7 core optimizations
02e,23aug11,rec WIND00292261 - transition to common power management API
02d,15apr11,jdw Enable cached page tables
02c,13jan11,m_h Define _CACHE_ALIGN_SIZE as cacheArchAlignSize for ARMARCH7
02b,09jul10,fao add endianness state bit define
02a,21may10,m_h Thumb-2 Support
01z,02feb10,j_b add _WRS_ARM_HAS_ASID macro, defined for ARMv6+
01y,23sep09,j_b add LDREX/STREX support for ARMARCH7
01x,06jun09,mdo Don't check IEEE status for FAST_MATH
01w,25feb09,j_b merge ARM SMP:
11jul07,j_b add ARMMMU_11MPCORE support
11jul07,to added ARM_HAS_LDREX_STREX feature macro
02jul07,m_h Adding types for MPCore varient
01v,27feb09,m_h ARMARCH7 Support
01u,12jun08,j_b add Cortex-A MMU and Cortex-A/-R cache support
01t,28apr08,m_h Create macro for NOP after LDM^ and STM^
01s,13jul06,m_h MPU support
01r,25jan06,m_h Manzano support
01o,10oct05,scm correct SPR 111664
01n,04apr05,jb Adding ARMARCH6 and 1136 support
01m,21mar05,mdo Add define for ansiMath testing
01l,02mar05,mdo Add prototype for __ieee_status() and definitions for
exception flags
01k,10aug04,scm remove MPU support...
01j,25nov03,sn Avoid gcc 3.3.2 preprocessor token pasting error
01i,26aug03,rec remove SYS_PWR_MGMT conditional
01h,07jul03,rec revert to non-portable kernel
01g,01jul03,rec code review comments
01f,28may03,rec Power Management
01f,17dec02,jb Adding ARM10 and 926E support
01e,15jan02,m_h ARMARCH5 thumb problem
01d,05nov01,t_m remove leading underscores via FUNC/VAR macros
01c,05nov01,t_m Undo underscores
01b,19jul01,ed Fixing to be compatible with Diab compiler.
01d,17oct01,t_m Merge in DIAB
01c,10oct01,jb Enabling removal of pre-pended underscores for new compilers
(Diab/Gnu elf)
01b,23jul01,scm change XScale name to conform to coding standards...
01a,11dec00,scm replace references to ARMSA2 with XScale
01g,16oct00,scm reverse back I & F bits for SA2
01f,01sep00,scm add sa2 support...
01e,08feb99,jpd added further MMU/CACHE types.
01d,20jan99,cdp removed support for old ARM libraries.
01c,24aug98,cdp added MMU/cache types, ARM_HAS_MPU/ARM_THUMB, ARMST16/ARMST32.
01b,21aug97,cdp added _?_FUNCTION macros and HAS_HALFWORD_
01a,08may96,cdp written
*/
#ifndef __INCarmh
#define __INCarmh
#ifdef __cplusplus
extern "C" {
#endif
#if (CPU == ARMARCH7M)
#include "arch/arm/arm-m/arm-m.h"
#else /* (CPU == ARMARCH7M) */
/* Make sure excArmLib.h also has same settings */
/* bits in the PSR */
#define V_BIT (1<<28)
#define C_BIT (1<<29)
#define Z_BIT (1<<30)
#define N_BIT (1<<31)
#define E_BIT (1<<9)
#define I_BIT (1<<7)
#define F_BIT (1<<6)
#define T_BIT (1<<5)
/* mode bits */
#define MODE_SYSTEM32 0x1F
#define MODE_UNDEF32 0x1B
#define MODE_ABORT32 0x17
#define MODE_SVC32 0x13
#define MODE_IRQ32 0x12
#define MODE_FIQ32 0x11
#define MODE_USER32 0x10
#define MODE_MONITOR 0x16
/* masks for getting bits from PSR */
#ifdef ARM_INTERWORKINGSUPPORT
#define MASK_MODE 0x0000003F
#else /*ARM_INTERWORKINGSUPPORT*/
#define MASK_MODE 0x0000001F
#endif /*ARM_INTERWORKINGSUPPORT*/
#define MASK_32MODE 0x0000001F
#define MASK_SUBMODE 0x0000000F
#define MASK_INT 0x000000C0
#define MASK_CC 0xF0000000
/* shifts to access bits in the PSR */
#define INT_MASK_SHIFT 6
/* The coprocessor number of the MMU System Control Processor */
#define CP_MMU 15
/* ARM MMU types */
#define ARMMMU_NONE 0
#define ARMMMU_710A 1
#define ARMMMU_810 2
#define ARMMMU_SA110 3
#define ARMMMU_940T 4
#define ARMMMU_740T 5
#define ARMMMU_SA1100 6
#define ARMMMU_SA1500 7
#define ARMMMU_720T 8
#define ARMMMU_920T 9
#define ARMMMU_946E 10
#define ARMMMU_XSCALE 11
#define ARMMMU_926E 12
#define ARMMMU_1020E 13
#define ARMMMU_1022E 14
#define ARMMMU_1136JF 15
#define ARMMMU_MANZANO 16
#define ARMMMU_CORTEXA8 17
#define ARMMMU_11MPCORE 18
#define ARMMPU_940T ARMMMU_940T
#define ARMMPU_740T ARMMMU_740T
#define ARMMPU_946E ARMMMU_946E
/* ARM cache types */
#define ARMCACHE_NONE 0
#define ARMCACHE_710A 1
#define ARMCACHE_810 2
#define ARMCACHE_SA110 3
#define ARMCACHE_940T 4
#define ARMCACHE_740T 5
#define ARMCACHE_SA1100 6
#define ARMCACHE_SA1500 7
#define ARMCACHE_720T 8
#define ARMCACHE_920T 9
#define ARMCACHE_946E 10
#define ARMCACHE_XSCALE 11
#define ARMCACHE_926E 12
#define ARMCACHE_1020E 13
#define ARMCACHE_1022E 14
#define ARMCACHE_1136JF 15
#define ARMCACHE_MANZANO 16
#define ARMCACHE_CORTEXA8 17
#define ARMCACHE_11MPCORE 18
#define ARMCACHE_CORTEXA15 19
/* check CPU/cache/MMU features */
/* Cache Line sizes */
#if defined (_WRS_CONFIG_ARMV7_CORE_CTX_A8) || \
defined (_WRS_CONFIG_ARMV7_CORE_CTX_A15)
#define _CPU_CACHE_ALIGN_SIZE 64 /* Cortex-A8 and Cortex-A15 use 64 bytes */
#else /* _WRS_CONFIG_ARMV7_CORE_CTX_A8 || _WRS_CONFIG_ARMV7_CORE_CTX_A15 */
/*
* Most ARM cores have a cache line size of 32 bytes.
*
* This can be overridden through use of the global variable
* cacheArchAlignSize. See below.
*/
#define _CPU_CACHE_ALIGN_SIZE 32
#endif /* _WRS_CONFIG_ARMV7_CORE_CTX_A8 || _WRS_CONFIG_ARMV7_CORE_CTX_A15 */
/*
* The way in which _CACHE_ALIGN_SIZE is defined has been changed
* somewhat and is no longer strictly related to the CPU type defined,
* but is instead related to the cache type selected. Therefore, it would
* be better if drivers that need to know the cache line size, use this
* variable, rather than the constant. The variable will be initialized
* to the appropriate cache-type-dependent value by the variant of the
* cache library initialisation code.
*/
#ifndef _ASMLANGUAGE
extern int cacheArchAlignSize;
#endif /* _ASMLANGUAGE */
/*
* Cached page tables are supported by ARM v6 and ARM v7 processors by
* default. Turn them on here for default builds (e.g. builds not
* configured by vxprj / VSBs).
*/
#if (!defined(_WRS_CONFIG_ARM_PRJ_BUILD) && \
((CPU == ARMARCH6) || (CPU == ARMARCH7) || (CPU == ARMARCH7_T2)))
#define _WRS_CONFIG_ENABLE_CACHED_PAGE_TBL
#endif
/*
* Cached page tables are not supported for ARMv6 MPCore BSPs, so
* disable this feature here for default & VSB builds
*/
#if ((defined (_WRS_CONFIG_SMP) && (CPU == ARMARCH6)) && \
defined (_WRS_CONFIG_ENABLE_CACHED_PAGE_TBL))
#undef _WRS_CONFIG_ENABLE_CACHED_PAGE_TBL
#endif
/*
* Cached page tables are not supported for ARM v4 and ARM v5 processors, so
* disable this feature here for default & VSB builds
*/
#if (((CPU == ARMARCH4) || (CPU == ARMARCH5) || (CPU == XSCALE)) && \
defined (_WRS_CONFIG_ENABLE_CACHED_PAGE_TBL))
#undef _WRS_CONFIG_ENABLE_CACHED_PAGE_TBL
#endif
#if ((CPU == ARMARCH7) || (CPU == ARMARCH7_T2))
/*
* By default cache alignment for ARMv7 is 32 bytes. This is accomplished by
* assigning cacheArchAlignSize as _CPU_CACHE_ALIGN_SIZE where it is declared
* in cacheArchVars.c. But some cores can have a cache alignment that is not
* 32 bytes. These cores will adjust the global variable cacheAlignSize
* during runtime initialization. See cacheAimCortexA8LibInit for an example
* of this.
*/
#undef _CACHE_ALIGN_SIZE
#define _CACHE_ALIGN_SIZE cacheArchAlignSize
/* this cpu family supports power management framework */
#define _WRS_ARCH_HAS_CPU_PWR_MGMT
#else /* ((CPU == ARMARCH7) || (CPU == ARMARCH7_T2)) */
/* Cache alignment is 32 bytes */
#undef _CACHE_ALIGN_SIZE
#define _CACHE_ALIGN_SIZE _CPU_CACHE_ALIGN_SIZE
#endif /* ((CPU == ARMARCH7) || (CPU == ARMARCH7_T2)) */
#if (CPU == ARMARCH3)
#define ARM_HAS_HALFWORD_INSTRUCTIONS FALSE
#else
#define ARM_HAS_HALFWORD_INSTRUCTIONS TRUE
#endif
#define ARM_HAS_MPU FALSE
#if defined(ARMMMU) && (ARMMMU == ARMMMU_NONE)
#define ARM_HAS_NO_MMU TRUE
#else
#define ARM_HAS_NO_MMU FALSE
#endif
#if (CPU == ARMARCH4_T) || (CPU == ARMARCH5_T)
#define ARM_THUMB TRUE
#else
#define ARM_THUMB FALSE
#endif
#if (CPU == ARMARCH7_T2)
#define ARM_THUMB2 TRUE
#else /* (CPU == ARMARCH7_T2) */
#define ARM_THUMB2 FALSE
#endif /* (CPU == ARMARCH7_T2) */
#if (ARM_THUMB2)
#define PORTABLE
#endif /* ARM_THUMB2 */
/*
* For ARMv5 and earlier, STM(2) and LDM(2) instructions
* must not be immediately followed by an
* instruction that accesses a banked register.
* Banked registers are: R8-R14. STM(2) and LDM(2) are
* the variations of the OP codes that end with "^"
* (load or store registers from a different mode -- user mode)
* and do not load the PC (do not branch).
*
* One possible solution to this (suggested by the
* ARM Architecture Reference Manual) is to insert
* a NOP between the STM or LDM call and the access
* to a banked register.
*
* Here is an example of where a NOP would be required
* because sp is one of the banked registers:
*
* LDMIA r1, {sp, lr}^
* NOP
* LDR r1, [sp, #SC_SAVE_USERSR]
*
* The asm macro ARM_NOP_AFTER_USER_LDM_STM is used for
* inserting the NOP only if the version of the architecture
* requires it.
*/
#if (CPU == ARMARCH4) || (CPU == ARMARCH5) || (CPU == XSCALE)
#define ARM_NOP_AFTER_USER_LDM_STM NOP
#else
#define ARM_NOP_AFTER_USER_LDM_STM
#endif
#if (CPU == ARMARCH6) || (CPU==ARMARCH7) || (CPU==ARMARCH7_T2)
#define ARM_HAS_LDREX_STREX TRUE
#define _WRS_ARM_HAS_ASID TRUE
#else /* (CPU == ARMARCH6) || (CPU==ARMARCH7) || (CPU==ARMARCH7_T2) */
#define ARM_HAS_LDREX_STREX FALSE
#define _WRS_ARM_HAS_ASID FALSE
#endif /* (CPU == ARMARCH6) || (CPU==ARMARCH7) || (CPU==ARMARCH7_T2) */
/** Power management for XSCALE **/
#if (CPU==XSCALE)
/* The coprocessor number of the Power Mode Register */
#define CP_CCLKCFG 14
/* OPCODE for idle */
#define PWRMODE_IDLE 1
#endif /* Power management for XSCALE */
/** Power management for ARM **/
#if (CPU==ARMARCH5) || (CPU==ARMARCH5_T) || (CPU==ARMARCH6) \
|| (CPU==ARMARCH7) || (CPU==ARMARCH7_T2)
/* The coprocessor number of the Power Mode Register */
#define CP_CORECTL 15
/* OPCODE for idle */
#define PWRMODE_IDLE 1
#endif /* CPU==ARMARCH5 ... ARMARCH7_T2 */
#if !defined(_WRS_CONFG_FAST_MATH) || (VFPVARIANT != VFPV3)
/* Define __ieee_status exception flags */
#define FE_IEEE_FLUSHZERO (0x01000000)
#define FE_IEEE_ROUND_TONEAREST (0x00000000)
#define FE_IEEE_ROUND_UPWARD (0x00400000)
#define FE_IEEE_ROUND_DOWNWARD (0x00800000)
#define FE_IEEE_ROUND_TOWARDZERO (0x00C00000)
#define FE_IEEE_ROUND_MASK (0x00C00000)
#define FE_IEEE_MASK_INVALID (0x00000100)
#define FE_IEEE_MASK_DIVBYZERO (0x00000200)
#define FE_IEEE_MASK_OVERFLOW (0x00000400)
#define FE_IEEE_MASK_UNDERFLOW (0x00000800)
#define FE_IEEE_MASK_INEXACT (0x00001000)
#define FE_IEEE_MASK_ALL_EXCEPT (0x00001F00)
#define FE_IEEE_INVALID (0x00000001)
#define FE_IEEE_DIVBYZERO (0x00000002)
#define FE_IEEE_OVERFLOW (0x00000004)
#define FE_IEEE_UNDERFLOW (0x00000008)
#define FE_IEEE_INEXACT (0x00000010)
#define FE_IEEE_ALL_EXCEPT (0x0000001F)
/* Define which of the IEEE status bits are reserved */
#define IEEE_RESERVED_MASK (0xF63FE0E0)
#ifndef _ASMLANGUAGE
extern unsigned int __ieee_status (unsigned int mask, unsigned int flags);
#endif
/* Define for ansiMath Testing */
#define _WRS_ARM_IEEE_STATUS
#endif
/*
* The default for ARMARCH7 and ARMARCH7_T2 is to use _WRS_CONFIG_FAST_MATH to
* optimize builds created with VFP enabled. The flag to enable this behavior
* is from the make fragments for a CPU/TOOL pair.
*
* Builds that use a SW FP tool chain should not use FAST MATH to get best
* performance.
*
* Override VSB options here because VSB configuration does not detect the
* tool chain / floating point configuration properly.
*/
#if defined(ARM_USE_VFP)
/* Vector floating point builds use FAST MATH */
#undef _WRS_CONFIG_FAST_MATH
#define _WRS_CONFIG_FAST_MATH 1
#else
/* Software floating point build does NOT use FAST MATH */
#undef _WRS_CONFIG_FAST_MATH
#endif /* defined(USE_ARM_FP) ... */
/*
* The default for ARMARCH7 and ARMARCH7_T2 is to use _WRS_CONFIG_FAST_MATH to
* optimize builds created with VFP enabled. The flag to enable this behavior
* is from the make fragments for a CPU/TOOL pair.
*
* Builds that use a SW FP tool chain should not use FAST MATH to get best
* performance.
*
* Override VSB options here because VSB configuration does not detect the
* tool chain / floating point configuration properly.
*/
#if defined(ARM_USE_VFP)
/* Vector floating point builds use FAST MATH */
#undef _WRS_CONFIG_FAST_MATH
#define _WRS_CONFIG_FAST_MATH 1
#else
/* Software floating point build does NOT use FAST MATH */
#undef _WRS_CONFIG_FAST_MATH
#endif /* defined(USE_ARM_FP) ... */
#ifdef _ASMLANGUAGE
/*
* File below inclusion must be after ARCH specific defines such as ARM_THUMB2.
*/
#include <asm.h>
/** I80310 (coyanosa) specific helper macros **/
#if ((CPU==XSCALE) || (CPU==ARMSA110))
/*
* The following macro should be used when software needs to be assured that a
* CP15 update has taken effect. It may only used while in a privileged mode,
* because it accesses CP15. Ref. Coyanosa EAS 2.3.4 Additions to CP15
* functionality
*/
#define CPWAIT(a) \
mrc p15, 0, a, c2, c0, 0 /* arbitrary read of CP15 */ ;\
mov a, a /* wait for it */ ;\
sub pc, pc, IMMED4 /* branch to next instruction */ ;
#define IMMED4 #4
/*
* at this point, any previous CP15 writes are guaranteed
* to have taken effect
*/
/*
* The following macro should be used when software needs to be assure that
* BCU has finish all outstanding operations.
*/
/*
* CAUTION: This macro should be used only from the cacheable region, or it may
* keep the BCU eternally busy fetching the code.
*/
#define BCUWAIT(a) \
mrc p13, 0, a, c0, c1, 0; /* Read BCUCTL,updates conditon code */ \
submi pc, pc, IMMED12 ; /* If BCU busy (bit 31 set) try again */
#define IMMED12 #12
#endif /* if CPU=XSCALE */
#endif /* _ASMLANGUAGE */
#endif /* (CPU == ARMARCH7M) */
#ifdef __cplusplus
}
#endif
#endif /* __INCarmh */
vxworks-6.9/target/h/arch/arm/asmArm.h
+201
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@@ -0,0 +1,201 @@
/* asmArm.h - ARM assembler definitions header file */
/*
* Copyright (c) 1996, 2004, 2010, 2012, 2013 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01g,20feb13,yjw add macros to support Thumb-2
01f,16oct12,jdw Add SPSR set macro (WIND00259770)
01e,18jan12,rec WIND00329076 - add FUNC_END, cleanup macros to be consistent
with other arch defines. Remove THUMB support.
01d,09jan12,jdw Add macro definitions for pld instructions
01c,21may10,m_h Thumb-2 Support
01b,06jul04,md added function definition macros
01a,09may96,cdp created
*/
#ifndef __INCasmArmh
#define __INCasmArmh
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _ASMLANGUAGE
#ifdef __GNUC__
.syntax unified
#endif
/* Build for Gnu elf or Diab compiler */
/* useful, assembly-language macros */
#define FUNC(a) a
#define VAR(name) name
/*
* These macros are used to declare assembly language symbols that need
* to be typed properly(func or data) to be visible to the OMF tool.
* So that the build tool could mark them as an entry point to be linked
* correctly.
*/
#ifdef __DCC__
#if ARM_THUMB2
#define GTEXT(sym) FUNC(sym) ; .type FUNC(sym),@tfunc
#else /* ARM_THUMB2 */
#define GTEXT(sym) FUNC(sym) ; .type FUNC(sym),@function
#endif /* ARM_THUMB2 */
#define GDATA(sym) VAR(sym) ; .type VAR(sym),@object
#elif (defined __GNUC__) /* GNU macros */
#define GTEXT(sym) FUNC(sym) ; .type FUNC(sym),STT_FUNC
#define GDATA(sym) VAR(sym) ; .type VAR(sym),STT_OBJECT
#else /* neither __DCC__ nor __GNUC__ */
#error "error!!! unsupported compiler!!!"
#endif /* __DCC__ */
/* abstract assembler idiosyncrasies */
#define FUNC_LABEL(func) func:
#define VAR_LABEL(name) name:
#define FUNC_EXPORT(func) .globl GTEXT(func)
#define DATA_EXPORT(var) .globl GDATA(var)
#define FUNC_IMPORT(func) .extern FUNC(func)
#define DATA_IMPORT(var) .extern VAR(var)
#define FUNC_END(func) .size FUNC(func), . - FUNC(func)
#if ((!defined __GNUC__) && (!defined __DCC__))
#error "error!!! unsupported assembler!!!"
#endif /* (defined __GNUC__) && (!defined __DCC__) */
/*
* The DCC assembler has problems with spaces before the function label.
* To avoid assembler parse problems, the FUNC_LABEL macros below are
* not indented.
*/
#if ARM_THUMB2
#if (defined __GNUC__)
#define FUNC_BEGIN(func) \
.thumb;\
.thumb_func;\
.balign 4;\
FUNC_LABEL(func)
#else /* !__GNUC__ */
#define FUNC_BEGIN(func) \
.thumb;\
.balign 4;\
FUNC_LABEL(func)
#endif /* __GNUC__ */
#else /* !ARM_THUMB2 */
#define FUNC_BEGIN(func) \
.code 32;\
.balign 4;\
FUNC_LABEL(func)
#endif /* ARM_THUMB2 */
/*
* The following two macros are deprecated. Definitions are provided for
* backward compatibility.
*/
#define _ARM_FUNCTION_CALLED_FROM_C FUNC_BEGIN
#define _ARM_FUNCTION FUNC_BEGIN
/* Define macros to use the PLD instruction on ARM v7 processors */
#if (CPU == ARMARCH7 || CPU == ARMARCH7_T2)
#define PLD(...) pld __VA_ARGS__
#else
/* if not ARM v7, do nothing */
#define PLD(...)
#endif
#if (CPU == ARMARCH7M)
/*
* Macro to perform a 32-bit MOV operation, using the ARMv7-M encoding of the
* MOV and MOVT instructions to copy the lower and upper 16-bits of a 32-bit
* constant to a register.
*/
#define _ARM_M_MOV32(reg, val) \
LDR reg, =val
/* External interrupt toggle */
#define INT_LOCK \
PUSH {r0}; \
MOV r0, #0x10; \
MSR basepri, r0; \
POP {r0}
#define INT_UNLOCK \
PUSH {r0}; \
MOV r0, #0x00; \
MSR basepri, r0; \
POP {r0}
#endif /* CPU == ARMARCH7M */
#define TEMP_STACK_ADR 0x20000800
/*
* The SPSR has changed and additional bits have been added as newer ARM
* architecture versions have been released. The new bit definitions are
* marked as RAZ/SBZP in older architecture revisions and shouldn't be
* modified. Newer versions of the Diab compiler have changed the behavior of
* the 'MSR spsr, <reg>' operation and no longer assumes modification of only
* spsr_cf fields when specific mask fields are not specified. GCC translates
* 'MSR spsr, <reg>' to only modify spsr_cf fields by default, if specific
* fields are not specified. See the ARM Architecture Reference Manual for
* definitions of the SPSR fields and MSR instruction behavior.
*
* The _ARM_SPSR_SET() macro abstracts arch and compiler issues from common
* code.
*/
#if (CPU != ARMARCH7M)
#if ((_VX_CPU == _VX_ARMARCH7) || (_VX_CPU == _VX_ARMARCH7_T2))
/*
* For ARMv7 (ARM & Thumb2) SPSR <23:20> are RAZ/SBZP, all others are
* defined... Write all bits.
*/
#define _ARM_SPSR_SET(reg) \
MSR spsr_cxsf, reg
#else /* ((_VX_CPU == _VX_ARMARCH7) || (_VX_CPU == _VX_ARMARCH7_T2)) */
/*
* For ARMv4, ARMv5, & ARMv6 architectures only the 'c' (bits <7:0>) and 'f'
* (bits <31:24>) fields are restored in order to remain consistent with
* earlier versions of VxWorks and older Diab compiler revisions.
*
* NOTES:
* 1) The IMX31 may crash if reserved SPSR bits are modified,
* see WIND00253307 for details
* 2) For ARMARCH6 the GE[3:0] bits (SPSR <19:16>) are not preserved
* because VxWorks does not support SIMD instructions
*/
#define _ARM_SPSR_SET(reg) \
MSR spsr_cf, reg
#endif /* ((_VX_CPU == _VX_ARMARCH7) || (_VX_CPU == _VX_ARMARCH7_T2)) */
#endif /* CPU != ARMARCH7M */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCasmArmh */
vxworks-6.9/target/h/arch/arm/cacheArm1136jfLib.h
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/* cacheArm1136jfLib.h - ARM 1136JF cache library header file */
/* Copyright 2005, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,29apr10,pad Moved extern C statement after include statements.
01b,18apr05,jb Fix for SPR 108034
01a,07dec04,jb created
*/
#ifndef __INCcacheArm1136jfLibh
#define __INCcacheArm1136jfLibh
/*
* Include ARCH6 common defines.
*/
#include "arch/arm/cacheArmArch6.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Some cache designs (e.g. Harvard) have D-cache either fully or
* partially not coherent with I-cache
*/
#define ARMCACHE_NOT_COHERENT TRUE
/*
* This is a writethrough cache
*/
#define ARMCACHE_HAS_WRITETHROUGH TRUE
/*
* Does not have a mini-cache
*/
#define ARMCACHE_HAS_MINICACHE FALSE
/*
* Do not need an Instruction Memory Barrier
*/
#define ARMCACHE_NEEDS_IMB TRUE
/*
* Most of the cache designs are virtually addressed, but some newer
* ones have physically addressed caches. Note that this is the method of
* addressing, not whether the cache has physical address tags within
* it.
*/
#define ARMCACHE_IS_PHYSICALLY_ADDRESSED TRUE
#ifndef _ASMLANGUAGE
IMPORT void cacheArm1136jfLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheArm1136jfLibh */
vxworks-6.9/target/h/arch/arm/cacheArm11MPCoreLib.h
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/* cacheArm11MPCoreLib.h - ARM 11 MPCore cache library header file */
/*
* Copyright (c) 2007, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01b,29apr10,pad Moved extern C statement after include statements.
01a,10jul07,m_h created
*/
#ifndef __INCcacheArm11MPCoreLibh
#define __INCcacheArm11MPCoreLibh
/*
* Include ARCH6 common defines.
*/
#include "arch/arm/cacheArmArch6.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Some cache designs (e.g. Harvard) have D-cache either fully or
* partially not coherent with I-cache
*/
#define ARMCACHE_NOT_COHERENT TRUE
/*
* This is a writethrough cache
*/
#define ARMCACHE_HAS_WRITETHROUGH TRUE
/*
* Does not have a mini-cache
*/
#define ARMCACHE_HAS_MINICACHE FALSE
/*
* Do not need an Instruction Memory Barrier
*/
#define ARMCACHE_NEEDS_IMB TRUE
/*
* Most of the cache designs are virtually addressed, but some newer
* ones have physically addressed caches. Note that this is the method of
* addressing, not whether the cache has physical address tags within
* it.
*/
#define ARMCACHE_IS_PHYSICALLY_ADDRESSED TRUE
/* Offsets from PERIPHBASE into MPCore Private Memory Region */
#define MPCORE_PMR_SNU_CTRL_OFFSET (0x00)
#define MPCORE_PMR_SNU_CONFIG_OFFSET (0x04)
#define MPCORE_PMR_CPU_STATUS_OFFSET (0x08)
#define MPCORE_PMR_INVALIDATE_ALL_OFFSET (0x0C)
/* Snoop Control Unit -- control register masks */
#define MPCORE_PMR_SNU_CTRL_EN (0x00000001)
#ifndef _ASMLANGUAGE
IMPORT UINT32 arm11MPCorePeriphBaseAddr;
IMPORT void cacheArm11MPCoreLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheArm11MPCoreLibh */
vxworks-6.9/target/h/arch/arm/cacheArm920tLib.h
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/* cacheArm920tLib.h - ARM 920T cache library header file */
/* Copyright 1998-2005 Wind River Systems, Inc. */
/*
modification history
--------------------
01d,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01c,09dec04,jb Further Palify ARM Aim cache
01b,11dec03,scm flushing out aim...
01a,04feb99,jpd created
*/
#ifndef __INCcacheArm920tLibh
#define __INCcacheArm920tLibh
#ifdef __cplusplus
extern "C" {
#endif
#define D_CACHE_SIZE (16*1024) /* 16 kbytes DCache */
#define I_CACHE_SIZE (16*1024) /* 16 kbytes ICache */
/*
* Some cache designs (e.g. Harvard) have D-cache either fully or
* partially not coherent with I-cache
*/
#define ARMCACHE_NOT_COHERENT TRUE
/*
* This is a writethrough cache
*/
#define ARMCACHE_HAS_WRITETHROUGH TRUE
/*
* Does not have a mini-cache
*/
#define ARMCACHE_HAS_MINICACHE FALSE
/*
* Do not need an Instruction Memory Barrier
*/
#define ARMCACHE_NEEDS_IMB FALSE
#ifndef _ASMLANGUAGE
IMPORT void cacheArm920tLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
/* definitions to allow for non-cacheAiIM direct calls */
#define cacheArm920tDClearDisable cacheAim920tDClearDisable
#define cacheArm920tIClearDisable cacheAim920tIClearDisable
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheArm920tLibh */
vxworks-6.9/target/h/arch/arm/cacheArm926eLib.h
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/* cacheArm926eLib.h - ARM 926E cache library header file */
/* Copyright 2002-2005 Wind River Systems, Inc. */
/*
modification history
--------------------
01d,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01c,07dec04,jb Further Palify ARM Aim cache
01b,11dec03,scm flushing out aim...
01a,09dec02,jpd created, based on cacheArm946eLib.h
*/
#ifndef __INCcacheArm926eLibh
#define __INCcacheArm926eLibh
#ifdef __cplusplus
extern "C" {
#endif
/*
* Some cache designs (e.g. Harvard) have D-cache either fully or
* partially not coherent with I-cache
*/
#define ARMCACHE_NOT_COHERENT TRUE
/*
* This is a writethrough cache
*/
#define ARMCACHE_HAS_WRITETHROUGH TRUE
/*
* Does not have a mini-cache
*/
#define ARMCACHE_HAS_MINICACHE FALSE
/*
* Do not need an Instruction Memory Barrier
*/
#define ARMCACHE_NEEDS_IMB FALSE
#ifndef _ASMLANGUAGE
IMPORT void cacheArm926eLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheArm926eLibh */
vxworks-6.9/target/h/arch/arm/cacheArm940tLib.h
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/* cacheArm940tLib.h - ARM 940T cache library header file */
/* Copyright 1998-2005 Wind River Systems, Inc. */
/*
modification history
--------------------
01d,27jul06,m_h vxWorks 6.x Support
01c,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01b,11dec03,scm flushing out aim...
01a,24nov98,jpd created
*/
#ifndef __INCcacheArm940tLibh
#define __INCcacheArm940tLibh
#ifdef __cplusplus
extern "C" {
#endif
#define D_CACHE_SIZE (4*1024) /* 4 kbytes DCache */
/*
* Some cache designs (e.g. Harvard) have D-cache either fully or
* partially not coherent with I-cache
*/
#define ARMCACHE_NOT_COHERENT TRUE
/*
* This is a writethrough cache
*/
#define ARMCACHE_HAS_WRITETHROUGH TRUE
/*
* Does not have a mini-cache
*/
#define ARMCACHE_HAS_MINICACHE FALSE
/*
* Do not need an Instruction Memory Barrier
*/
#define ARMCACHE_NEEDS_IMB FALSE
#ifndef _ASMLANGUAGE
IMPORT void cacheArm940tLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
#if 0
/* if true, not building with cacheAIM support... */
/* The following prototypes are pre-cacheAIM support */
IMPORT void cacheArm940tDClearDisable (void);
IMPORT void cacheArm940tDFlush (void * addr);
IMPORT void cacheArm940tDFlushAll (void);
IMPORT void cacheArm940tDInvalidateAll (void);
IMPORT void cacheArm940tIInvalidateAll (void);
IMPORT void cacheArm940tIInvalidate (void * addr);
IMPORT void cacheArm940tDClearAll (void);
IMPORT void cacheArm940tDClear (void * addr);
IMPORT void cacheArm940tIClearDisable (void);
IMPORT void cacheArm940tArchPipeFlush (void);
#else
/* else, cacheAIM support... */
/* definitions to allow for non-cacheAiIM direct calls */
#define cacheArm940tDClearDisable cacheAim940tDClearDisable
#define cacheArm940tIClearDisable cacheAim940tIClearDisable
#endif
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheArm940tLibh */
vxworks-6.9/target/h/arch/arm/cacheArm946eLib.h
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/* cacheArm946eLib.h - ARM 946E cache library header file */
/*
* Copyright (c) 2000-2006 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01e,16jun06,m_h non-cacheAIM direct calls
01d,22may06,m_h Palify
01c,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01b,11dec03,scm flushing out aim...
01a,20jul00,jpd created, based on cacheArm940tLib.h
*/
#ifndef __INCcacheArm946eLibh
#define __INCcacheArm946eLibh
#ifdef __cplusplus
extern "C" {
#endif
/*
* Some cache designs (e.g. Harvard) have D-cache either fully or
* partially not coherent with I-cache
*/
#define ARMCACHE_NOT_COHERENT TRUE
/*
* This is a writethrough cache
*/
#define ARMCACHE_HAS_WRITETHROUGH TRUE
/*
* Does not have a mini-cache
*/
#define ARMCACHE_HAS_MINICACHE FALSE
/*
* Do not need an Instruction Memory Barrier
*/
#define ARMCACHE_NEEDS_IMB FALSE
#ifndef _ASMLANGUAGE
IMPORT void cacheArm946eLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
/* definitions to allow for non-cacheAIM direct calls */
#define cacheArm946eDClearDisable cacheAim946eDClearDisable
IMPORT void cacheArm946eDClearDisable (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheArm946eLibh */
vxworks-6.9/target/h/arch/arm/cacheArmArch6.h
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/* cacheArmArch6.h - ARM ARCH6 cache library header file */
/* Copyright 2004-2005, 2009, 2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01e,30sep11,cwl define functions for cache enable/disable. (WIND00284079)
01d,18feb11,my_ Declare new functions which support L2 cache.
01c,18sep09,j_b add core-specific function ptr for DClearDisable operation
01b,20apr05,jb Fix for SPR 108034
01a,07dec04,jb created
*/
#ifndef __INCcacheArmArch6h
#define __INCcacheArmArch6h
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
/*
* Common definitions for Arm Arch6 Cache support
*/
extern STATUS cacheAimArch6IEnable (void);
extern STATUS cacheAimArch6DEnable (void);
extern STATUS cacheAimArch6IDisable (void);
extern STATUS cacheAimArch6DDisable (void);
extern STATUS cacheAimArch6IProbe (void);
extern STATUS cacheAimArch6DProbe (void);
extern BOOL cacheAimArch6IIsOn (void);
extern BOOL cacheAimArch6DIsOn (void);
extern STATUS cacheAimArch6TextUpdate (void * start, UINT32 count, UINT32 IcacheLineSize, UINT32 DcacheLineSize);
extern void * cacheAimArch6DmaMalloc (size_t bytes);
extern STATUS cacheAimArch6DmaFree (void * pBuf);
extern BOOL cacheAimArch6MmuIsOn (void);
extern STATUS cacheAimArch6DInvalidate (void * start, void * end, UINT32 step);
extern STATUS cacheAimArch6DInvalidateAll (void);
extern STATUS cacheAimArch6IInvalidate (void * start, void * end, UINT32 step);
extern STATUS cacheAimArch6IInvalidateAll (void);
extern STATUS cacheAimArch6DFlush (void * start, void * end, UINT32 step);
extern STATUS cacheAimArch6DFlushAll (void);
extern STATUS cacheAimArch6DClear (void * start, void * end, UINT32 step);
extern STATUS cacheAimArch6PipeFlush (void);
extern void cacheAimArch6IMB (void);
extern void cacheAimArch6IClearDisable (void);
extern void cacheAimArch6DClearDisableWithVerify (void);
extern void cacheAimArch6DClearDisableNoVerify (void);
extern UINT32 cacheAimArch6Identify (void);
extern FUNCPTR sysCacheLibInit;
extern UINT32 cacheArchState;
extern STATUS cacheArchIInvalidate(void * start, void * end, UINT32 step);
extern STATUS cacheArchIInvalidateAll(void);
extern STATUS cacheArchDFlush(void * start, void * end, UINT32 step);
extern STATUS cacheArchDFlushAll(void);
extern STATUS cacheArchDInvalidate(void * start, void * end, UINT32 step);
extern STATUS cacheArchDInvalidateAll(void);
extern STATUS cacheArchDClear(void * start, void * end, UINT32 step);
extern STATUS cacheArchDClearAll (void);
/*
* Core-specific function pointer for D-cache ClearDisable operation.
* These must be initialized by the cacheAim<core>LibInit() routine.
*/
extern VOIDFUNCPTR _func_cacheAimArch6DClearDisable;
extern void (*_pSysL2CacheEnable)(CACHE_TYPE cacheType);
extern void (*_pSysL2CacheDisable)(CACHE_TYPE cacheType);
extern void (*_pSysL2CacheInvFunc)(CACHE_TYPE cacheType, void * start, void * end);
extern void (*_pSysL2CacheFlush)(CACHE_TYPE cacheType, void * start, void * end);
extern void (*_pSysL2CacheClear)(CACHE_TYPE cacheType, void * start, void * end);
extern void cacheArchL2CacheEnable(void);
extern void cacheArchL2CacheDisable(void);
extern BOOL cacheArchL2CacheIsOn(void);
#endif
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheArmArch6h */
vxworks-6.9/target/h/arch/arm/cacheArmArch7.h
+298
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/* cacheArmArch7.h - ARM ARCH7 cache library header file */
/*
* Copyright (c) 2008, 2010, 2012, 2014 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
06jan14,c_l Improve cache operation. (VXW6-27040)
01h,09nov12,j_b remove unnecessary L1 data cache operation macro
01g,04oct12,j_b add macro to operate only on entire L1 D-cache
01f,21sep12,j_b Add DSB to end of _CORTEX_AR_ENTIRE_DATA_CACHE_OP
01e,10sep12,m_h L2 cachePipeFlush (WIND00240234)
01d,02jun10,m_h Thumb-2 Support
01c,19may10,z_l Declare new functions which support L2 cache.
01b,01aug08,j_b fix _CORTEX_AR_ENTIRE_DATA_CACHE_OP labels
01a,11jun08,j_b Created from cacheArmArch6.h, rev 01b
*/
#ifndef __INCcacheArmArch7h
#define __INCcacheArmArch7h
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
/*
* Common definitions for Arm Arch7 Cache support
*/
/* cache levels: 7 possible, indexed starting from 0 */
#define ARMV7_CACHE_LVL1 0
#define ARMV7_CACHE_LVL2 1
#define ARMV7_CACHE_LVL3 2
#define ARMV7_CACHE_LVL4 3
#define ARMV7_CACHE_LVL5 4
#define ARMV7_CACHE_LVL6 5
#define ARMV7_CACHE_LVL7 6
/* cache types from Cache Level ID register (CLIDR) */
#define ARMV7_CLID_ICACHE_TYPE 0x1 /* instruction cache */
#define ARMV7_CLID_DCACHE_TYPE 0x2 /* data cache */
#define ARMV7_CLID_UCACHE_TYPE 0x4 /* unified cache */
/* cache types for Cache Size Selection register (CSSEL) */
#define ARMV7_CSSEL_ICACHE_TYPE 0x1 /* select instruction cache */
#define ARMV7_CSSEL_DCACHE_TYPE 0x0 /* select data or unified cache */
/* cache size info from Cache Size ID register (CCSIDR) */
#define ARMV7_CCSID_LINESIZE_MSK 0x7 /* line size bit mask */
#define ARMV7_CCSID_WAYNUM_MSK 0x1FF8 /* associativity bit mask */
#define ARMV7_CCSID_SETNUM_MSK 0xFFFE000 /* set number bit mask */
#define ARMV7_CCSID_MODE_MSK 0xF0000000 /* mode bit mask */
#define ARMV7_CCSID_WAYNUM_SHFT 3 /* associativity field shift */
#define ARMV7_CCSID_SETNUM_SHFT 13 /* set number field shift */
#define ARMV7_CCSID_MODE_WT 0x80000000 /* write-through mode */
#define ARMV7_CCSID_MODE_WB 0x40000000 /* write-back mode */
#define ARMV7_CCSID_MODE_RA 0x20000000 /* read-allocate mode */
#define ARMV7_CCSID_MODE_WA 0x10000000 /* write-allocate mode */
/*
* Common routines for Arm Arch7 Cache support
*
* Note that many of the Arch 6 routines are still valid for Arch 7 and
* have been brought forward.
*/
extern STATUS cacheAimArch7IEnable (void);
extern STATUS cacheAimArch7DEnable (void);
extern STATUS cacheAimArch7IDisable (void);
extern STATUS cacheAimArch7DDisable (void);
extern STATUS cacheAimArch7IProbe (void);
extern STATUS cacheAimArch7DProbe (void);
extern BOOL cacheAimArch7IIsOn (void);
extern BOOL cacheAimArch7DIsOn (void);
extern STATUS cacheAimArch7TextUpdate (void * start,
UINT32 count,
UINT32 IcacheLineSize,
UINT32 DcacheLineSize);
extern void * cacheAimArch7DmaMalloc (size_t bytes);
extern STATUS cacheAimArch7DmaFree (void * pBuf);
extern BOOL cacheAimArch7MmuIsOn (void);
extern STATUS cacheAimArch6DInvalidate (void * start, void * end, UINT32 step);
extern STATUS cacheAimArch7DInvalidateAll (void);
extern STATUS cacheAimArch6IInvalidate (void * start, void * end, UINT32 step);
extern STATUS cacheAimArch6IInvalidateAll (void);
extern STATUS cacheAimArch6DFlush (void * start, void * end, UINT32 step);
extern STATUS cacheAimArch7DFlushAll (void);
extern STATUS cacheAimArch7DFlushPoU (void * start, void * end, UINT32 step);
extern STATUS cacheAimArch6DClear (void * start, void * end, UINT32 step);
extern STATUS cacheAimArch7DClearAll (void);
extern STATUS cacheAimArch6PipeFlush (void);
extern void cacheAimArch7IMB (void);
extern void cacheAimArch6IClearDisable (void);
extern UINT32 cacheAimArch7Identify (UINT32 level);
extern UINT32 cacheAimArch7SizeInfoGet (UINT32 level, UINT32 type);
extern STATUS cacheArchIInvalidate(void * start, void * end, UINT32 step);
extern STATUS cacheArchIInvalidateAll(void);
extern STATUS cacheArchDFlush(void * start, void * end, UINT32 step);
extern STATUS cacheArchDFlushAll(void);
extern STATUS cacheArchDInvalidate(void * start, void * end, UINT32 step);
extern STATUS cacheArchDInvalidateAll(void);
extern STATUS cacheArchDClear(void * start, void * end, UINT32 step);
extern STATUS cacheArchDClearAll (void);
extern STATUS cacheArchPipeFlush (void);
extern size_t cacheArchLocSizeGet (void);
extern size_t cacheArchLouSizeGet (void);
extern FUNCPTR sysCacheLibInit;
extern UINT32 cacheArchState;
/*
* Core-specific function pointers for ARMv7 multilevel cache handling.
* These must be initialized by the cacheAim<core>LibInit() routine.
*/
extern VOIDFUNCPTR _func_cacheAimArch7IClearDisable;
extern VOIDFUNCPTR _func_cacheAimArch7DClearDisable;
extern void (*_pSysL2CacheEnable)(CACHE_TYPE cacheType);
extern void (*_pSysL2CacheDisable)(CACHE_TYPE cacheType);
extern void (*_pSysL2CacheInvFunc)(CACHE_TYPE cacheType, void * start, void * end);
extern void (*_pSysL2CacheFlush)(CACHE_TYPE cacheType, void * start, void * end);
extern void (*_pSysL2CacheClear)(CACHE_TYPE cacheType, void * start, void * end);
extern void cacheArchL2CacheEnable(void);
extern void cacheArchL2CacheDisable(void);
extern BOOL cacheArchL2CacheIsOn(void);
#else /* _ASMLANGUAGE */
/*
* Using "#" in the middle of a complex #define generates garbage
* passed to the assembler which results in a syntax error. ARM_IMM is
* used by this file in order to tell the assembler to use an immediate
* value.
*/
#define ARM_IMM #
#define ARM_LOC_MASK #0x7000000 /* level of coherency mask of CLIDR */
/*
* Common code for cache operations on entire data/unified caches,
* performed by set/way to the point of coherency (PoC).
* This code is based on 'Example code for cache maintenance operations'
* provided in "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
* (ARM DDI 0406)" .
*
* Registers used: For ARM ISA, r0-r8, though r4-r8 are saved/restored.
* For THUMB-2, r0-r9, though r4-r9 are saved/restored.
* Also, note that r0 is 0 when this code completes.
*/
#if ARM_THUMB2 /* LSL is less capable in Thumb-2 */
#define _CORTEX_AR_ENTIRE_DATA_CACHE_OP(crm) \
STMFD sp!, {r4-r9} /* save registers */;\
\
MRC p15, 1, r0, c0, c0, 1 /* r0 = Cache Lvl ID register info */;\
ANDS r3, r0, ARM_LOC_MASK /* get level of coherency (LoC) */;\
MOV r3, r3, LSR ARM_IMM 23 /* r3 = LoC << 1 */;\
BEQ 5f ;\
\
MOV r7, ARM_IMM 0 /* r7 = cache level << 1; start at 0 */;\
\
1: ;\
AND r1, r0, ARM_IMM 0x7 /* r1 = cache type(s) for this level */;\
CMP r1, ARM_IMM 2 ;\
BLT 4f /* no data cache at this level */;\
\
MCR p15, 2, r7, c0, c0, 0 /* select the Cache Size ID register */;\
ISB /* ISB: sync change to Cache Size ID */;\
MRC p15, 1, r1, c0, c0, 0 /* r1 = current Cache Size ID info */;\
AND r2, r1, ARM_IMM 0x7 /* r2 = line length */;\
ADD r2, r2, ARM_IMM 4 /* add line length offset = log2(16 bytes) */;\
LDR r4, =0x3FF ;\
ANDS r4, r4, r1, LSR ARM_IMM 3 /* r4 = (# of ways - 1); way index */;\
CLZ r5, r4 /* r5 = bit position of way size increment */;\
LDR r6, =0x00007FFF ;\
ANDS r6, r6, r1, LSR ARM_IMM 13/* r6 = (# of sets - 1); set index */;\
\
2: ;\
MOV r1, r4 /* r1 = working copy of way number */;\
3: ;\
LSL r9, r1, r5 /* r8 = set/way operation data word: */;\
ORR r8, r7, r9 ;\
LSL r9, r6, r2 /* cache level, way and set info */;\
ORR r8, r8, r9 ;\
\
MCR p15, 0, r8, c7, crm, 2 /* dcache operation by set/way */;\
\
SUBS r1, r1, ARM_IMM 1 /* decrement the way index */;\
BGE 3b ;\
SUBS r6, r6, ARM_IMM 1 /* decrement the set index */;\
BGE 2b ;\
\
4: ;\
ADD r7, r7, ARM_IMM 2 /* increment cache index = level << 1 */;\
CMP r3, r7 /* done when LoC is reached */;\
MOVGT r0, r0, LSR ARM_IMM 3 /* rt-align type of next cache level */;\
BGT 1b ;\
\
5: ;\
DSB ;\
LDMIA sp!, {r4-r9} /* restore registers */;
#else /* !ARM_THUMB2 */
#define _CORTEX_AR_ENTIRE_DATA_CACHE_OP(crm) \
STMFD sp!, {r4-r8} /* save registers */;\
\
MRC p15, 1, r0, c0, c0, 1 /* r0 = Cache Lvl ID register info */;\
ANDS r3, r0, ARM_LOC_MASK /* get level of coherency (LoC) */;\
MOV r3, r3, LSR ARM_IMM 23 /* r3 = LoC << 1 */;\
BEQ 5f ;\
\
MOV r7, ARM_IMM 0 /* r7 = cache level << 1; start at 0 */;\
\
1: ;\
AND r1, r0, ARM_IMM 0x7 /* r1 = cache type(s) for this level */;\
CMP r1, ARM_IMM 2 ;\
BLT 4f /* no data cache at this level */;\
\
MCR p15, 2, r7, c0, c0, 0 /* select the Cache Size ID register */;\
ISB /* ISB: sync change to Cache Size ID */;\
MRC p15, 1, r1, c0, c0, 0 /* r1 = current Cache Size ID info */;\
AND r2, r1, ARM_IMM 0x7 /* r2 = line length */;\
ADD r2, r2, ARM_IMM 4 /* add line length offset = log2(16 bytes) */;\
LDR r4, =0x3FF ;\
ANDS r4, r4, r1, LSR ARM_IMM 3 /* r4 = (# of ways - 1); way index */;\
CLZ r5, r4 /* r5 = bit position of way size increment */;\
LDR r6, =0x00007FFF ;\
ANDS r6, r6, r1, LSR ARM_IMM 13/* r6 = (# of sets - 1); set index */;\
\
2: ;\
MOV r1, r4 /* r1 = working copy of way number */;\
3: ;\
ORR r8, r7, r1, LSL r5 /* r8 = set/way operation data word: */;\
ORR r8, r8, r6, LSL r2 /* cache level, way and set info */;\
\
MCR p15, 0, r8, c7, crm, 2 /* dcache operation by set/way */;\
\
SUBS r1, r1, ARM_IMM 1 /* decrement the way index */;\
BGE 3b ;\
SUBS r6, r6, ARM_IMM 1 /* decrement the set index */;\
BGE 2b ;\
\
4: ;\
ADD r7, r7, ARM_IMM 2 /* increment cache index = level << 1 */;\
CMP r3, r7 /* done when LoC is reached */;\
MOVGT r0, r0, LSR ARM_IMM 3 /* rt-align type of next cache level */;\
BGT 1b ;\
\
5: ;\
DSB ;\
LDMIA sp!, {r4-r8} /* restore registers */;
#endif /*ARM_THUMB2*/
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheArmArch7h */
vxworks-6.9/target/h/arch/arm/cacheArmLib.h
+151
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/* cacheArmLib.h - ARM cache library header file */
/*
* Copyright (c) 1996-2008, 2010-2012, 2014 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
06jan14,c_l Improve cache operation. (VXW6-27040)
01w,17jul12,j_b Add Cortex-A15 cache support
01v,07feb12,c_l Fix compiling error. (WIND00294062)
01u,13jan11,m_h moving cacheArchAlignSize to arm.h
01t,29apr10,pad Moved extern C statement after include statements.
01s,02jul07,m_h Adding support for MPCore
01r,12jun08,j_b add Cortex-A/-R cache support
01q,22may06,m_h 946 Support
01p,22feb06,m_h Manzano Support
01o,28mar05,jb Adding 1136jfs Support
01n,25jan05,jb Removing in-advertant addition of 1136
01m,07dec04,jb Restructure for Base6
01l,01dec03,scm modify for AIM support...
01k,17dec02,jb Adding ARM10 and 926E support
01k,24jan03,jb Resolve SPR 81285 and 82533
01j,02oct01,jpd added definitions to support simplifications in source.
01i,12nov01,to added cacheArchIntMask (merged from AE)
01h,23jul01,scm change XScale name to conform to coding standards...
01g,11dec00,scm replace references to ARMSA2 with XScale
01f,01sep00,scm add sa2 support...
01e,07sep99,jpd added ARM920T support.
01d,24nov98,jpd added ARM940T, ARMSA1100, ARMSA1500 support;
cdp restructured for multiple cache/MMU libraries.
01c,09mar98,jpd tidied.
01b,16sep97,jpd added cacheIMBRange(), 810 definitions for cacheDClear() and
cacheArchIntLock().
01a,09may96,cdp created
*/
/*
* N.B. although this library contains code written for the ARM810
* CPU, at the time of writing, this code has not been fully tested on
* that CPU. YOU HAVE BEEN WARNED.
*/
#ifndef __INCcacheArmLibh
#define __INCcacheArmLibh
#ifndef _ASMLANGUAGE
/*
* Variable used to hold the interrupt mask used when disabling
* interrupts for lengthy cache operations such as cache flushing. This
* is preinitialised to a mask that disables IRQs and FIQs. The BSP may
* change this. Do not do so unless you are sure that you understand the
* consequences. In particular, if interrupts are allowed to occur
* during these operations, the state of the cache afterwards may be
* indeterminate.
*/
IMPORT UINT32 cacheArchIntMask;
/* routine that locks interrupts according to the mask above */
IMPORT UINT32 cacheArchIntLock (void);
#endif /* _ASMLANGUAGE */
/*
* Arm Arch HW specific bits used by cache routines...
*/
#define CACHE_MM_ENABLE (1<<0) /* MMU enable */
#define CACHE_DC_ENABLE (1<<2) /* (data) cache enable */
#define CACHE_WB_ENABLE (1<<3) /* write buffer enable */
#define CACHE_IC_ENABLE (1<<12) /* Instruction cache enable */
#define LoC_MASK 0x07000000 /* level of coherency mask of CLIDR */
#define LoC_SHIFT 23 /* level of coherency shift of CLIDR */
#define LoUU_MASK 0x38000000 /* level of coherency mask of CLIDR */
#define LoUU_SHIFT 26 /* level of coherency shift of CLIDR */
/*
* Reset Architecture specific cache behavior.
* It is set with the cpu include file.
*/
#undef ARMCACHE_NOT_COHERENT
#undef ARMCACHE_HAS_WRITETHROUGH
#undef ARMCACHE_HAS_MINICACHE
#undef ARMCACHE_NEEDS_IMB
#if (ARMCACHE == ARMCACHE_926E)
#include "cacheArm926eLib.h"
#elif (ARMCACHE == ARMCACHE_946E)
#include "cacheArm946eLib.h"
#elif (ARMCACHE == ARMCACHE_920T)
#include "cacheArm920tLib.h"
#elif (ARMCACHE == ARMCACHE_940T)
#include "cacheArm940tLib.h"
#elif (ARMCACHE == ARMCACHE_1022E)
#include "cacheArm1022eLib.h"
#elif (ARMCACHE == ARMCACHE_1136JF)
#include "cacheArm1136jfLib.h"
#elif (ARMCACHE == ARMCACHE_XSCALE)
#include "cacheArmXSCALELib.h"
#elif (ARMCACHE == ARMCACHE_MANZANO)
#include "cacheArmManzanoLib.h"
#elif (ARMCACHE == ARMCACHE_CORTEXA8)
#include "cacheCortexA8Lib.h"
#elif (ARMCACHE == ARMCACHE_11MPCORE)
#include "cacheArm11MPCoreLib.h"
#elif (ARMCACHE == ARMCACHE_CORTEXA15)
#include "cacheCortexA15Lib.h"
#endif /* ARMCACHE == ARMCACHE_926E */
#ifdef __cplusplus
extern "C" {
#endif
#if (ARMCACHE != ARMCACHE_NONE)
/*
* Verify the cpu has established some special attributes
*/
#ifndef ARMCACHE_NOT_COHERENT
#error ARMCACHE value not supported in definition of ARMCACHE_NOT_COHERENT
#endif
#ifndef ARMCACHE_HAS_WRITETHROUGH
#error ARMCACHE value not supported in definition of ARMCACHE_HAS_WRITETHROUGH
#endif
#ifndef ARMCACHE_HAS_MINICACHE
#define ARMCACHE_HAS_MINICACHE FALSE
#endif
#ifndef ARMCACHE_NEEDS_IMB
#error ARMCACHE value not supported in definition of ARMCACHE_NEEDS_IMB
#endif
#endif /* ARMCACHE_NONE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheArmLibh */
vxworks-6.9/target/h/arch/arm/cacheArmManzanoLib.h
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/* cacheArmManzanoLib.h - ARM XScale cache library header file */
/* Copyright 199-2005 Wind River Systems, Inc. */
/*
modification history
--------------------
01i,22feb06,m_h Manzano Support
01h,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01g,07dec04,jb Further Palify ARM Aim cache
01f,01dec03,scm flushing out aim...
01e,25jul01,scm add btbInvalidate...
01d,23jul01,scm change XScale name to conform to coding standards...
01c,09feb01,scm add support for cache & TLB locking...
01b,19dec00,scm correct cache sizes...
01a,31aug00,scm created
*/
#ifndef __INCcacheArmManzanoLibh
#define __INCcacheArmManzanoLibh
#ifdef __cplusplus
extern "C" {
#endif
#define D_CACHE_SIZE (32*1024) /* 32 kbytes DCache */
#define I_CACHE_SIZE (32*1024) /* 32 kbytes ICache */
#define MINI_CACHE_SIZE (2*1024) /* 2 kbytes minicache */
#define MINI_CACHE_LINE_SIZE 32 /* 32 bytes per line*/
/*
* Some cache designs (e.g. Harvard) have D-cache either fully or
* partially not coherent with I-cache
*/
#define ARMCACHE_NOT_COHERENT TRUE
/*
* This is a writethrough cache
*/
#define ARMCACHE_HAS_WRITETHROUGH TRUE
/*
* Has a mini-cache
*/
#define ARMCACHE_HAS_MINICACHE TRUE
/*
* Does not need an Instruction Memory Barrier
*/
#define ARMCACHE_NEEDS_IMB FALSE
#ifndef _ASMLANGUAGE
IMPORT void cacheArmManzanoLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
/* definitions to allow for non-cacheAim direct calls */
#define cacheArmManzanoDClearDisable cacheAimManzanoDClearDisable
#define cacheArmManzanoIClearDisable cacheAimManzanoIClearDisable
IMPORT void cacheAimManzanoDClearDisable (void);
IMPORT void cacheAimManzanoIClearDisable (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheArmManzanoLibh */
vxworks-6.9/target/h/arch/arm/cacheArmXSCALELib.h
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/* cacheArmXSCALELib.h - ARM XScale cache library header file */
/* Copyright 199-2005 Wind River Systems, Inc. */
/*
modification history
--------------------
01h,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01g,07dec04,jb Further Palify ARM Aim cache
01f,01dec03,scm flushing out aim...
01e,25jul01,scm add btbInvalidate...
01d,23jul01,scm change XScale name to conform to coding standards...
01c,09feb01,scm add support for cache & TLB locking...
01b,19dec00,scm correct cache sizes...
01a,31aug00,scm created
*/
#ifndef __INCcacheArmXSCALELibh
#define __INCcacheArmXSCALELibh
#ifdef __cplusplus
extern "C" {
#endif
#define D_CACHE_SIZE (32*1024) /* 32 kbytes DCache */
#define I_CACHE_SIZE (32*1024) /* 32 kbytes ICache */
#define MINI_CACHE_SIZE (2*1024) /* 2 kbytes minicache */
#define MINI_CACHE_LINE_SIZE 32 /* 32 bytes per line*/
/*
* Some cache designs (e.g. Harvard) have D-cache either fully or
* partially not coherent with I-cache
*/
#define ARMCACHE_NOT_COHERENT TRUE
/*
* This is a writethrough cache
*/
#define ARMCACHE_HAS_WRITETHROUGH TRUE
/*
* Has a mini-cache
*/
#define ARMCACHE_HAS_MINICACHE TRUE
/*
* Does not need an Instruction Memory Barrier
*/
#define ARMCACHE_NEEDS_IMB FALSE
#ifndef _ASMLANGUAGE
IMPORT void cacheArmXSCALELibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
/* definitions to allow for non-cacheAim direct calls */
#define cacheArmXSCALEDClearDisable cacheAimXSCALEDClearDisable
#define cacheArmXSCALEIClearDisable cacheAimXSCALEIClearDisable
IMPORT void cacheAimXSCALEDClearDisable (void);
IMPORT void cacheAimXSCALEIClearDisable (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheArmXSCALELibh */
vxworks-6.9/target/h/arch/arm/cacheCortexA15Lib.h
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/* cacheCortexA15Lib.h - Cortex-A15 cache library header file */
/*
* Copyright 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01b,31aug12,ggm Added SMP support.
01a,14jul12,j_b Created from cacheCortexA8Lib.h, rev 01c
*/
#ifndef __INCcacheCortexA15Libh
#define __INCcacheCortexA15Libh
/*
* Include ARCH7 common defines.
*/
#include "arch/arm/cacheArmArch7.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Some cache designs (e.g. Harvard) have D-cache either fully or
* partially not coherent with I-cache
*/
#define ARMCACHE_NOT_COHERENT TRUE
/*
* This is a writethrough cache
*/
#define ARMCACHE_HAS_WRITETHROUGH TRUE
/*
* Does not have a mini-cache
*/
#define ARMCACHE_HAS_MINICACHE FALSE
/*
* Does need an Instruction Memory Barrier
*/
#define ARMCACHE_NEEDS_IMB TRUE
/*
* Most of the cache designs are virtually addressed, but some newer
* ones have physically addressed caches. Note that this is the method of
* addressing, not whether the cache has physical address tags within
* it.
*/
#define ARMCACHE_IS_PHYSICALLY_ADDRESSED TRUE
#ifndef _ASMLANGUAGE
IMPORT void cacheCortexA15LibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
IMPORT void cacheCortexA15DClearDisable (void); /* includes L2 cache */
/* L2 Cache support functions */
IMPORT UINT32 cacheCortexA15L2CacrGet (void);
IMPORT void cacheCortexA15L2CacrSet (UINT32 cacr);
IMPORT UINT32 cacheCortexA15L2EcrGet (void);
IMPORT void cacheCortexA15L2EcrSet (UINT32 ecr);
IMPORT void cacheCortexA8L2ClearAll (void);
/* CPU ID access function and definitions */
IMPORT UINT32 mmuReadId (void);
/* SMP support functions */
#ifdef _WRS_CONFIG_SMP
IMPORT void cacheCortexA15MPCoreSMPInit(void);
#endif
#define MAIN_ID_PART_MASK 0xFFF0
#define MAIN_ID_PART_SHIFT 0x4
#define MAIN_ID_PART_CORTEXA15 0xC0F
/* Auxiliary Control Register access functions and definitions */
IMPORT UINT32 mmuCortexA8AcrGet (void);
IMPORT void mmuCortexA8AcrSet (UINT32 acrVal);
/* enable invalidation of branch tgt buffer with I-cache invalidate */
#define ACTLR_BTB_INVAL_EN 0x1
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheCortexA15Libh */
vxworks-6.9/target/h/arch/arm/cacheCortexA8Lib.h
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/* cacheCortexA8Lib.h - Cortex-A8 cache library header file */
/*
* Copyright 2008, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01c,23sep10,j_b add cacheCortexL2ClearAll() prototype
01b,29apr10,pad Moved extern C statement after include statements.
01a,03jun08,j_b Created from cacheArm1136jfLib.h, rev 01b
*/
#ifndef __INCcacheCortexA8Libh
#define __INCcacheCortexA8Libh
/*
* Include ARCH7 common defines.
*/
#include "arch/arm/cacheArmArch7.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Some cache designs (e.g. Harvard) have D-cache either fully or
* partially not coherent with I-cache
*/
#define ARMCACHE_NOT_COHERENT TRUE
/*
* This is a writethrough cache
*/
#define ARMCACHE_HAS_WRITETHROUGH TRUE
/*
* Does not have a mini-cache
*/
#define ARMCACHE_HAS_MINICACHE FALSE
/*
* Do not need an Instruction Memory Barrier
*/
#define ARMCACHE_NEEDS_IMB TRUE
/*
* Most of the cache designs are virtually addressed, but some newer
* ones have physically addressed caches. Note that this is the method of
* addressing, not whether the cache has physical address tags within
* it.
*/
#define ARMCACHE_IS_PHYSICALLY_ADDRESSED TRUE
#ifndef _ASMLANGUAGE
IMPORT void cacheCortexA8LibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
IMPORT void cacheCortexA8DClearDisable (void); /* includes L2 cache */
/* L2 Cache support functions */
IMPORT UINT32 cacheCortexA8L2CacrGet (void);
IMPORT void cacheCortexA8L2CacrSet (UINT32 cacr);
IMPORT void cacheCortexA8L2Enable (void);
IMPORT void cacheCortexA8L2Disable (void);
IMPORT void cacheCortexA8L2ClearAll (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheCortexA8Libh */
vxworks-6.9/target/h/arch/arm/cacheCortexA9Lib.h
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/* cacheCortexA9Lib.h - Cortex-A9 cache library header file */
/*
* Copyright (c) 2009, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01c,29apr10,pad Moved extern C statement after include statements.
01b,20oct09,z_l Created from cacheCortexA8Lib.h, rev 01a
*/
#ifndef __INCcacheCortexA9Libh
#define __INCcacheCortexA9Libh
/* Include ARCH7 common defines. */
#include "arch/arm/cacheArmArch7.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Some cache designs (e.g. Harvard) have D-cache either fully or
* partially not coherent with I-cache
*/
#define ARMCACHE_NOT_COHERENT TRUE
/* This is a writethrough cache */
#define ARMCACHE_HAS_WRITETHROUGH TRUE
/* Does not have a mini-cache */
#define ARMCACHE_HAS_MINICACHE FALSE
/* Do not need an Instruction Memory Barrier */
#define ARMCACHE_NEEDS_IMB TRUE
/*
* Most of the cache designs are virtually addressed, but some newer
* ones have physically addressed caches. Note that this is the method of
* addressing, not whether the cache has physical address tags within
* it.
*/
#define ARMCACHE_IS_PHYSICALLY_ADDRESSED TRUE
#ifndef _ASMLANGUAGE
IMPORT void cacheCortexA9LibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
IMPORT void cacheCortexA9DClearDisable (void);
/* SMP support functions */
#ifdef _WRS_CONFIG_SMP
IMPORT void cacheCortexA9MPCoreSMPInit(void);
#endif /* _WRS_CONFIG_SMP */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheCortexA9Libh */
vxworks-6.9/target/h/arch/arm/coprocArm.h
+45
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@@ -0,0 +1,45 @@
/* coprocArm.h - coprocessor management library header */
/*
* Copyright (c) 2004-2007, 2010, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01f,15may12,jmp CQID: Fix WIND00309977 : Added VX_COPROCS_ALL_TASK
definition.
01e,28apr10,pad Moved extern C statement after include statements.
01d,02oct07,jb Move VFP to FP equivilent, part of fix for WIND00093069
01c,30jun05,scm add support for ARM VFP...
01b,04aug04,scm fix permissions...
01a,03aug04,scm written based on coprocI86.h 01a.
*/
#ifndef __INCcoprocArmh
#define __INCcoprocArmh
/* includes */
#include <taskLib.h>
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#define VX_FP_TASK VX_COPROC1_TASK
#define VX_VFP_TASK VX_FP_TASK
#define VX_COPROCS_ALL_TASK VX_FP_TASK
#ifdef __cplusplus
}
#endif
#endif /* __INCcoprocArmh */
vxworks-6.9/target/h/arch/arm/dbgArmLib.h
+110
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/* dbgArmLib.h - header file for ARM-dependent part of debugger */
/*
* Copyright 1996-2004, 2005, 2010, 2013 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable Wind
* River license agreement.
*/
/*
modification history
--------------------
01j,26may13,pma Update for ARMARCH7M
01i,26jul10,jdw Update with support for THUMB2
01h,29apr10,pad Moved extern C statement after include statements.
01g,24feb05,jb Correct definition of SYSCALL_INST
01f,09dec04,scm resolve DBG_SYSCALL_SIZE warning, define DBG_SYSCALL_INST
01e,11feb04,elg Add syscall instruction size macro.
01d,12nov98,cdp added support for ARM generic Thumb library.
01c,20apr98,dbt modified for new breakpoint scheme
01b,24apr97,cdp added Thumb (ARM7TDMI_T) support;
changed DBG_BREAK_INST for non-Thumb processors.
01a,09may96,cdp created
*/
#ifndef __INCdbgArmLibh
#define __INCdbgArmLibh
#include "esf.h"
#ifdef __cplusplus
extern "C" {
#endif
#define BREAK_ESF ESF
#define TRACE_ESF ESF
#define DBG_SYSCALL_SIZE (sizeof (INSTR) / sizeof (INSTR))
#if (ARM_THUMB2)
#define DBG_SYSCALL_INST 0xDF00 /* SVC */
#define DBG_SYSCALL_MASK 0xFF00
#else /* (ARM_THUMB2) */
#define DBG_SYSCALL_INST 0xEF0000FA /* SVC (formerly SWI) */
#endif /* (ARM_THUMB2) */
#if (ARM_THUMB2)
/*
* For Thumb2 we can not support cret() without a valid frame pointer so
* support is disabled here.
*/
#define DBG_CRET FALSE
#endif /* (ARM_THUMB2) */
#if (ARM_THUMB) || (ARM_THUMB2)
/*
* TODO -- The WDB code which inserts breakpoints needs to be smarter
* than it is. We need to use a 16- or 32-bit value depending on the
* instruction we are going to break on.
*/
#define DBG_BREAK_INST 0xDEFE /* The undefined instruction used as a
* breakpoint for Thumb-state */
#define DBG_INST_ALIGN 2
#else /* (ARM_THUMB) || (ARM_THUMB2) */
#define DBG_BREAK_INST 0xE7FDDEFE /* The undefined instruction used as a
* breakpoint for ARM-state */
#define DBG_INST_ALIGN 4
#endif /* (ARM_THUMB) || (ARM_THUMB2) */
#define DBG_NO_SINGLE_STEP 1 /* no hardware trace support */
#if (CPU == ARMARCH7M)
#define BRK_INST 0x0 /* hardware instruction breakpoint */
#define DEFAULT_HW_BP (BRK_INST) /* default hardware breakpoint */
#define BRK_HARDWARE (0x10) /* hardware breakpoint bit */
#define BRK_HARDMASK (0x0f) /* hardware breakpoint mask */
#define DBG_HARDWARE_BP 1
#ifdef DBG_NO_SINGLE_STEP
#undef DBG_NO_SINGLE_STEP
#endif
#define DBG_NO_SINGLE_STEP 0 /* no trace support */
#define MAX_HW_BP_NUM 6
#ifndef _ASMLANGUAGE
/* hardware breakpoint registers */
typedef struct /* DBG_REGS */
{
unsigned int fp_compx[MAX_HW_BP_NUM]; /* debug register: flash patch */
} DBG_REGS;
#endif /* _ASMLANGUAGE */
#endif /* ARMARCH7M */
#ifdef __cplusplus
}
#endif
#endif /* __INCdbgArmLibh */
vxworks-6.9/target/h/arch/arm/dsmArmLib.h
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/* dsmArmLib.h - ARM disassembler header file */
/*
* Copyright (c) 1996-2005, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01c,19oct10,jmp Updated INSTR_IS() macro to use VXDBG_INSTR_CMP()
(CQ:WIND00185617).
01b,29apr10,pad Moved extern C statement after include statements.
01a,14jan05,rec add print function to dsmInst
01c,09oct97.jpd added more Thumb instructions.
01b,09sep97,cdp added more instructions.
01a,09may96,cdp created.
*/
#ifndef __INCdsmArmLibh
#define __INCdsmArmLibh
#include <vwModNum.h>
#ifdef __cplusplus
extern "C" {
#endif
/* dsmLib status codes */
#define S_dsmLib_UNKNOWN_INSTRUCTION (M_dsmLib | 1)
/*
* Macro and definitions for simple decoding of instuctions.
* To check an instruction, it is ANDed with the IMASK_ and
* the result is compared with the IOP_. The macro INSTR_IS
* does this and returns !0 to indicate a match.
*/
#define INSTR_IS(pInstr,o) VXDBG_INSTR_CMP(pInstr,(IOP_##o),(IMASK_##o))
#define IMASK_BL 0x0F000000 /* BL xxx */
#define IOP_BL 0x0B000000
#define IMASK_STMDB_SPP_FP_IP_LR_PC 0xFFFFF800 /* STMDB sp!,{..fp,ip,lr,pc} */
#define IOP_STMDB_SPP_FP_IP_LR_PC 0xE92DD800
#define IMASK_SUB_FP_IP_4 0xFFFFFFFF /* SUB fp,ip,#4 */
#define IOP_SUB_FP_IP_4 0xE24CB004
#define IMASK_SUB_FP_IP_4PLUS 0xFFFFF000 /* SUB fp,ip,#4+ */
#define IOP_SUB_FP_IP_4PLUS 0xE24CB000
#define IMASK_MOV_IP_SP 0xFFFFFFFF /* MOV ip,sp */
#define IOP_MOV_IP_SP 0xE1A0C00D
#define IMASK_MOVXX_LR_PC 0x0FFFFFFF /* MOVxx lr,pc */
#define IOP_MOVXX_LR_PC 0x01A0E00F
#define IMASK_STMDB_SPP_AREGS 0xFFFFFFF0 /* STMDB sp!,{a1-a4} */
#define IOP_STMDB_SPP_AREGS 0xE92D0000
#define IMASK_SUB_SP_SP 0xFFFFF000 /* SUB sp,sp,#n */
#define IOP_SUB_SP_SP 0xE24DD000
#define IMASK_MOVS_PC_LR 0xFFFFFFFF /* MOVS pc,lr */
#define IOP_MOVS_PC_LR 0xE1B0F00E
/* Thumb instructions */
#define IMASK_T_BL0 0xF800 /* BL prefix */
#define IOP_T_BL0 0xF000
#define IMASK_T_BL1 0xF800 /* BL */
#define IOP_T_BL1 0xF800
#define IMASK_T_MOV_LR_PC 0xFFFF /* MOV lr,pc */
#define IOP_T_MOV_LR_PC 0x46FE
#define IMASK_T_SUB_SP_16 0xFFFF /* SUB sp,#16 */
#define IOP_T_SUB_SP_16 0xB084
#define IMASK_T_MOV_FP_LO 0xFFC7 /* MOV fp,loreg */
#define IOP_T_MOV_FP_LO 0x4683
#define IMASK_T_MOV_SP_LO 0xFFC7 /* MOV sp,loreg */
#define IOP_T_MOV_SP_LO 0x4685
#define IMASK_T_ADD_LO_SP 0xF800 /* ADD loreg, sp, #Imm */
#define IOP_T_ADD_LO_SP 0xA800
#define IMASK_T_POP_LO 0xFF00 /* POP {reglist} (not PC) */
#define IOP_T_POP_LO 0xBC00
#define IMASK_T_PUSH_LO 0xFF00 /* PUSH {reglist} (not LR) */
#define IOP_T_PUSH_LO 0xB400
#define IMASK_T_PUSH 0xFF00 /* PUSH {reglist} (inc LR) */
#define IOP_T_PUSH 0xB500
#define IMASK_T_BX_LO 0xFFC0 /* BX loreg */
#define IOP_T_BX_LO 0x4700
#define IMASK_T_MOV_LO_PC 0xFFF8 /* MOV loreg,pc */
#define IOP_T_MOV_LO_PC 0x4678
#define IMASK_T_MOV_LO_FP 0xFFF8 /* MOV loreg,fp */
#define IOP_T_MOV_LO_FP 0x4658
IMPORT int dsmNbytes(FAST INSTR *binInst);
IMPORT int dsmInst(FAST INSTR *binInst, int address, VOIDFUNCPTR prtAddress,
FUNCPTR oFn, int oArg);
#ifndef _ASMLANGUAGE
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCdsmArmLibh */
vxworks-6.9/target/h/arch/arm/elfArm.h
+100
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@@ -0,0 +1,100 @@
/* elfArm.h - ARM-specific elf loader header */
/*
* Copyright (c) 2001,2004-2005,2009-2010 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software may be
* licensed only pursuant to the terms of an applicable Wind River license
* agreement.
*/
/*
modification history
--------------------
01g,11oct10,v_r Added support for the R_ARM_CALL and R_ARM_THM_JUMP24
relocation types (CQ:WIND00234720).
Removed unused types (by both the kernel loader and the
userspace shared lib loader).
01f,14dec09,pgh Add EM_ARCH_MACHINE_x macro definition.
01e,25jul05,v_r Updated copyright.
01d,18feb05,dbt Cleanup.
01c,18sep04,jn Move towards shared code for host and target loaders
01b,17feb04,jn Merged version from AE.
01b,30nov01,pad Moved definitions of CHECK_FITS and SIGN_EXTEND into
loadElfLibP.h
01a,24aug01,jn created, based on vxWorksAE 1.1
share/src/loader/elfArm.h@@/main/tor3_x/5
*/
#ifndef __INCelfArmh
#define __INCelfArmh
#ifdef __cplusplus
extern "C" {
#endif
/*
* macro to check that a signed <val> fits in <nBits> without overflow
* i.e. that the "sign-bit" is correctly propagated into the excess high bits
*/
#define CHECK_FITS(val,nBits) \
((((val) & ~((1 << ((nBits)-1))-1)) == 0) || \
(((val) & ~((1 << ((nBits)-1))-1)) == ~(UINT32)((1 << ((nBits)-1))-1)))
/* macros to insert the low n bits of a value into a buffer. */
#define LOW24_INSERT(buf,value) INSERT ((buf), (value), 0x00ffffff)
#define LOW16_INSERT(buf,value) INSERT ((buf), (value), 0x0000ffff)
#define LOW12_INSERT(buf,value) INSERT ((buf), (value), 0x00000fff)
#define LOW11_INSERT(buf,value) INSERT ((buf), (value), 0x000007ff)
#define LOW8_INSERT(buf,value) INSERT ((buf), (value), 0x000000ff)
#define BITS6_10_INSERT(buf,value) INSERT ((buf), (value) << 6, 0x000007c0)
#define UBIT_INSERT(buf,value) INSERT ((buf), (value) << 23 , 0x0080000)
/*
* The following macro defines the ELF machine type value that can be loaded
* into an ARM CPU.
*/
#define EM_ARCH_MACHINE_1 EM_ARM
#define EM_ARCH_MACHINE EM_ARM
#define EM_ARCH_MACH_ALT EM_ARM /* not used */
/* Relocation Type Definitions */
#define R_ARM_NONE 0 /* No reloc */
#define R_ARM_PC24 1
#define R_ARM_ABS32 2
#define R_ARM_REL32 3
#define R_ARM_PC13 4
#define R_ARM_ABS16 5
#define R_ARM_ABS12 6
#define R_ARM_THM_ABS5 7
#define R_ARM_ABS8 8
#define R_ARM_THM_PC22 10
#define R_ARM_THM_PC8 11
#define R_ARM_COPY 20 /* copy symbol at runtime */
#define R_ARM_GLOB_DAT 21 /* create GOT entry */
#define R_ARM_JUMP_SLOT 22 /* create PLT entry */
#define R_ARM_RELATIVE 23 /* adjust by program base */
#define R_ARM_CALL 28
#define R_ARM_THM_JUMP24 30
#define R_ARM_THM_PC11 102 /* cygnus extension to abi: */
/* thumb unconditional branch */
#define R_ARM_THM_PC9 103 /* cygnus extension to abi: */
/* thumb conditional branch */
#ifdef __cplusplus
}
#endif
#endif /* __INCelfArmh */
vxworks-6.9/target/h/arch/arm/esfArm.h
+64
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@@ -0,0 +1,64 @@
/* esfArm.h - ARM exception stack frames */
/*
* Copyright (c) 1996, 2004, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01e,09may12,j_b enable ARMARCH7M-specific header usage
01d,03may12,j_b revert to remove ARMARCH7M-specific header usage
01c,01may12,j_b Update for ARMv7M
01b,09sep04,scm add ttbase to ESF, so structs REG_SET & ESF overlap correctly
01a,09may96,cdp created
*/
#ifndef __INCesfArmh
#define __INCesfArmh
#if (CPU == ARMARCH7M)
#include "arch/arm/arm-m/esfArm-m.h"
#else /* (CPU == ARMARCH7M) */
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
/* The Exception Stack Frame
* On the ARM, this is faked by a stub and the pointer
* passed back points to the PC and CPSR at the end of the
* register structure. If that changes, so must this.
*
* I.E. REG_SET struct & ESf struct 'overlap' on last 3
* elements of REG_SET (pc,cpsr,ttbase)...
*/
typedef struct
{
INSTR *pc; /* program counter */
ULONG cpsr; /* current PSR */
ULONG ttbase; /* Trans Table Base */
UINT32 vecAddr; /* address of exception vector => type */
} ESF;
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* (CPU == ARMARCH7M) */
#endif /* __INCesfArmh */
vxworks-6.9/target/h/arch/arm/excArmLib.h
+119
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@@ -0,0 +1,119 @@
/* excArmLib.h - ARM exception library header file */
/*
* Copyright (c) 1996-2003,2006,2009,2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01g,14may12,m_h enable ARMARCH7M-specific header usage
01f,23mar09,m_h Support for non-zero exception vector base
01e,01feb06,jb Adding VFP Support
01d,26nov03,pes Correct _WRS_IS_SUPV_EXC macro.
01c,18nov03,pes Add _WRS_IS_SUPV_EXC macro.
01b,23jul01,scm change XScale name to conform to coding standards...
01a,11dec00,scm replace references to ARMSA2 with XScale
01c,16oct00,scm reverse back I & F bits for SA2
01b,15sep00,scm update for SA2 support...
01a,09may96,cdp created
*/
#ifndef __INCexcArmLibh
#define __INCexcArmLibh
#if (CPU == ARMARCH7M)
#include "arch/arm/arm-m/excArmLib-m.h"
#else /* (CPU == ARMARCH7M) */
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
/*
* NOTE: if this structure changes, the TCB offsets in h/private/taskLibP.h
* must be updated. See also taskLib.h.
*/
typedef struct
{
UINT32 valid; /* indicators that following fields are valid */
UINT32 vecAddr; /* exception vector address */
INSTR * pc; /* PC */
UINT32 cpsr; /* CPSR */
} EXC_INFO;
#define _WRS_IS_SUPV_EXC() (((excInfo.cpsr & MASK_MODE) == MODE_USER32) ? FALSE : TRUE)
extern FUNCPTR excExcepHook; /* add'l rtn to call when exceptions occur */
extern VOIDFUNCPTR _func_excBreakpoint; /* called to handle breakpoints */
extern void excVecBaseSet (UINT32 base); /* non-zero exception base address */
#if defined(__STDC__) || defined(__cplusplus)
extern STATUS excIntConnect (VOIDFUNCPTR *, VOIDFUNCPTR);
extern void excVecSet (FUNCPTR *, FUNCPTR);
extern FUNCPTR excVecGet (FUNCPTR *);
#else /* __STDC__ */
extern STATUS excIntConnect ();
extern void excVecSet ();
extern FUNCPTR excVecGet ();
#endif /* __STDC__ */
#endif /* ASMLANGUAGE */
/* exception information valid bits */
#define EXC_INFO_VECADDR 0x01 /* vector is valid */
#define EXC_INFO_PC 0x02 /* PC is valid */
#define EXC_INFO_CPSR 0x04 /* CPSR is valid */
#define EXC_INFO_VFPCSR 0x08 /* VFP CSR is valid */
/* exception vector addresses */
#define EXC_OFF_RESET 0x00 /* reset */
#define EXC_OFF_UNDEF 0x04 /* undefined instruction */
#define EXC_OFF_SWI 0x08 /* software interrupt */
#define EXC_OFF_PREFETCH 0x0c /* prefetch abort */
#define EXC_OFF_DATA 0x10 /* data abort */
#define EXC_OFF_IRQ 0x18 /* interrupt */
#define EXC_OFF_FIQ 0x1C /* fast interrupt */
/* Exception Vector Base */
#define ARM_EXC_VEC_BASE 0x00
/*
* In coyanosa I80310 the default vector base is 0x00,
* can be relocated into 0xFFFF0000
*
*/
#if ((CPU==XSCALE) || (CPU==ARMSA110))
#define ARM_EXC_VEC_BASE_RELOCATED 0xffff0000
#endif
#ifdef __cplusplus
}
#endif
#endif /* (CPU == ARMARCH7M) */
#endif /* __INCexcArmLibh */
vxworks-6.9/target/h/arch/arm/fppArmLib.h
+64
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@@ -0,0 +1,64 @@
/* fppArmLib.h - ARM floating-point coprocessor support header file */
/*
* Copyright 1996, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01b,11jan12,jdw Update to call the VFP routines, WIND00327855
01a,09may96,cdp created
*/
#ifndef __INCfppArmLibh
#define __INCfppArmLibh
#include <arch/arm/vfpArmLib.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
#define FP_CONTEXT VFP_CONTEXT
#define FPREG_SET FP_CONTEXT
/* variable declarations */
extern REG_INDEX fpRegName[]; /* f-point data register table */
extern REG_INDEX fpCtlRegName[]; /* f-point control register table */
extern WIND_TCB *pFppTaskIdPrevious; /* task id for deferred exceptions */
extern FUNCPTR fppCreateHookRtn; /* arch dependent create hook routine */
extern FUNCPTR fppDisplayHookRtn; /* arch dependent display routine */
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT void fppArchInit (void);
IMPORT void fppArchTaskCreateInit (FP_CONTEXT *pFpContext);
#else /* __STDC__ */
IMPORT void fppArchInit ();
IMPORT void fppArchTaskCreateInit ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCfppArmLibh */
vxworks-6.9/target/h/arch/arm/in_cksum.h
+179
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/* in_cksum.h - x86 version in_cksum header file */
/* Copyright 2001-2002 Wind River Systems, Inc. */
/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from tahoe: in_cksum.c 1.2 86/01/05
* from: @(#)in_cksum.c 1.3 (Berkeley) 1/19/91
* from: Id: in_cksum.c,v 1.8 1995/12/03 18:35:19 bde Exp
* $FreeBSD: src/sys/i386/include/in_cksum.h,v 1.7.2.1 2000/05/05 13:37:00 jlemon Exp $
*/
/*
modification history
--------------------
01g,25aug05,dlk Add section tags.
01f,24mar04,m_h Internet Checksum
01e,18mar04,m_h move to arch/arm
01d,20nov03,niq Remove copyright_wrs.h file inclusion
01c,05nov03,rlm Ran batch header update for header re-org.
01b,25jul02,rvr removed DCC specific code
01a,13sep01,hsh Created from BSD 4.3
*/
#ifndef _MACHINE_IN_CKSUM_H_
#define _MACHINE_IN_CKSUM_H_ 1
#include <sys/cdefs.h>
/*
* in_cksum_hdr - checksum on header only
*
* It is useful to have an Internet checksum routine which is inlineable
* and optimized specifically for the task of computing IP header checksums
* in the normal case (where there are no options and the header length is
* therefore always exactly five 32-bit words.
*/
static __inline
u_int in_cksum_hdr
(
const struct ip *ip
)
{
register u_int sum = 0;
int hlen = sizeof (struct ip);
register u_short *w = (u_short *) ip;
u_short remaining = 0;
while (hlen > 1)
{
sum += *w++;
hlen -= 2;
}
if (hlen == 1)
{
*(u_char *) (&remaining) = *(u_char *) w;
sum += remaining;
}
sum = (sum & 0xffff) + (sum >> 16);
if (sum > 0xffff)
sum -= 0xffff;
return ~sum & 0xffff;
}
/*
* in_cksum_update
*/
static __inline
void in_cksum_update
(
struct ip *ip
)
{
int __tmpsum;
__tmpsum = (int)ntohs(ip->ip_sum) + 256;
ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16));
}
/*
* in_pseudo - pre-checksum parts of pseudo-header
*
* Compute significant parts of the IPv4 checksum pseudo-header * for use in a
* delayed TCP/UDP checksum calculation.
*
* Args:
*
* src Source IP address
* dst Destination IP address
* lenproto htons(proto-hdr-len + proto-number)
*/
static __inline
u_int16_t in_pseudo
(
u_int32_t src,
u_int32_t dst,
u_int32_t lenproto
)
{
u_int32_t sum;
sum = lenproto +
(u_int16_t)(src >> 16) +
(u_int16_t)(src /*& 0xffff*/) +
(u_int16_t)(dst >> 16) +
(u_int16_t)(dst /*& 0xffff*/);
sum = (u_int16_t)(sum >> 16) + (u_int16_t)(sum /*& 0xffff*/);
if (sum > 0xffff)
sum -= 0xffff;
return (sum);
}
/*
* in_addword - Add two 16-bit workd
*
* Add the two 16-bit network-order values, carry, and return.
*/
static __inline
u_int16_t in_addword
(
u_int16_t a,
u_int16_t b
)
{
u_int32_t sum = a + b;
if (sum > 0xffff)
sum -= 0xffff;
return (sum);
}
_WRS_FASTTEXT
u_short in_cksum_skip(struct mbuf *m, int len, int skip);
#endif /* _MACHINE_IN_CKSUM_H_ */
vxworks-6.9/target/h/arch/arm/intArmLib.h
+236
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@@ -0,0 +1,236 @@
/* intArmLib.h - ARM-specific interrupt library header file */
/*
* Copyright (c) 1997-1998, 2003, 2007-2010, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01l,07may12,jdw Add ARMARCH7M header include
01j,03dec10,j_b add unified FIQ/IRQ handling support
01i,23oct09,j_b fix _inline_intCpuMicroUnlock for gnu
01h,18may09,j_b add _inline_intCpuMicroLock/Unlock support
01h,25feb09,j_b merge ARM SMP support:
21jun07,jb3 Convert to vxBus
01g,16jun08,zl added memory clobber for GNUC version of inline routines.
01f,20may08,j_b fix memory accesses outside lock in
_inline_intCpuLock/Unlock for gnu (WIND00121559)
01e,07aug07,jb3 Defect00095620 wrong gnu assembler instruction.
01d,21jun07,zl updated inline build configuration.
01c,22aug03,to added inline intLock()/intUnlock().
01b,20aug98,cdp added intIFLock(), intIFUnlock().
01a,25nov97,cdp created.
*/
#ifndef __INCintArmLibh
#define __INCintArmLibh
#if (CPU == ARMARCH7M)
#include <arch/arm/arm-m/intArmLib.h>
#else /* (CPU == ARMARCH7M) */
#ifdef __cplusplus
extern "C" {
#endif
/* interrupt model feature selection bits (OR'd together) */
#define INT_NON_PREEMPT_MODEL 0
#define INT_PREEMPT_MODEL 1
#define INT_HDWE_LOCK_LVL 2
#ifndef _ASMLANGUAGE
/* inline intCpuLock()/intCpuUnlock() and intCpuMicroLock/Unlock() */
#if !(ARM_THUMB)
#if defined (__DCC__)
__asm volatile int _inline_intCpuLock ()
{
! "r1" /* r1 clobbered */
mrs r1, cpsr /* get current status */
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
and r0, r1, #0xC0 /* return current I & F in r0 */
orr r1, r1, #0xC0 /* set I & F (1<<7 | 1<<6) */
#else
and r0, r1, #0x80 /* return current I_BIT in r0 */
orr r1, r1, #0x80 /* set I_BIT (1<<7) */
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
msr cpsr, r1 /* set new status */
}
__asm volatile void _inline_intCpuUnlock (int key)
{
% reg key; /* input: key in r0 */
! "r0", "r1" /* r0, r1 clobbered */
mrs r1, cpsr /* get current status */
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
bic r1, r1, #0xC0 /* clear I & F (1<<7 | 1<<6) */
and r0, key, #0xC0 /* get passed I & F values */
#else
bic r1, r1, #0x80 /* clear I_BIT (1<<7) */
and r0, key, #0x80 /* get passed I_BIT value */
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
orr r1, r1, r0 /* or in passed value */
msr cpsr,r1 /* set new status */
}
__asm volatile int _inline_intCpuMicroLock ()
{
! "r1" /* r1 clobbered */
mrs r0, cpsr /* get, return current status */
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
orr r1, r0, #0xC0 /* set I & F (1<<7 | 1<<6) */
#else
orr r1, r0, #0x80 /* set I_BIT (1<<7) */
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
msr cpsr_c, r1 /* set new status */
}
__asm volatile void _inline_intCpuMicroUnlock (int key)
{
% reg key; /* input: key in r0 */
msr cpsr_c, key /* restore previous status */
}
#elif defined (__GNUC__)
static __inline__ int _inline_intCpuLock (void)
{
int key;
__asm__ volatile
(
"mrs r1, cpsr; " /* get current status */
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
"and %0, r1, #0xC0; " /* return current I & F */
"orr r1, r1, #0xC0; " /* set I & F (1<<7 | 1<<6) */
#else
"and %0, r1, #0x80; " /* return current I_BIT */
"orr r1, r1, #0x80; " /* set I_BIT (1<<7) */
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
"msr cpsr, r1 " /* set new status */
: "=&r" (key) /* output: key is %0 */
: /* no input */
: "r1", "memory" /* r1 clobbered; memory */
/* clobber for code barrier */
);
return key;
}
static __inline__ void _inline_intCpuUnlock (int key)
{
__asm__ volatile
(
"mrs r1, cpsr; " /* get current status */
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
"bic r1, r1, #0xC0; " /* clear I & F (1<<7 | 1<<6) */
"and r0, %0, #0xC0; " /* get passed I & F values */
#else
"bic r1, r1, #0x80; " /* clear I_BIT (1<<7) */
"and r0, %0, #0x80; " /* get passed I_BIT value */
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
"orr r1, r1, r0; " /* or in passed I_BIT value */
"msr cpsr, r1" /* set new status */
: /* no output */
: "r" (key) /* input: key is %0 */
: "r0", "r1", "memory" /* r0, r1 clobbered; memory */
/* clobber for code barrier */
);
}
static __inline__ int _inline_intCpuMicroLock (void)
{
int key;
__asm__ volatile
(
"mrs %0, cpsr; " /* get, return current status */
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
"orr r1, %0, #0xC0; " /* set I & F (1<<7 | 1<<6) */
#else
"orr r1, %0, #0x80; " /* set I_BIT (1<<7) */
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
"msr cpsr_c, r1 " /* set new status */
: "=&r" (key) /* output: key is %0 */
: /* no input */
: "r1", "memory" /* r1 clobbered; memory */
/* clobber for code barrier */
);
return key;
}
static __inline__ void _inline_intCpuMicroUnlock (int key)
{
__asm__ volatile
(
"msr cpsr_c, %0" /* restore previous status */
: /* no output */
: "r" (key) /* input: key is %0 */
/* no regs, memory clobbered */
);
}
#else
#define _inline_intCpuLock() intCpuLock()
#define _inline_intCpuUnlock(key) intCpuUnlock(key)
#define _inline_intCpuMicroLock() intCpuMicroLock()
#define _inline_intCpuMicroUnlock(key) intCpuMicroUnlock(key)
#endif /* __DCC__ */
#endif /* !ARM_THUMB */
/* functions in intArchLib.c and intALib.s */
extern STATUS intDisable (int);
extern STATUS intEnable (int);
extern STATUS intLibInit (int, int, int);
extern int intIFLock (void);
extern void intIFUnlock (int);
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
extern int intILock (void);
extern void intIUnlock (int);
extern int intFLock (void);
extern void intFUnlock (int);
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
/*
* Function pointers used in intArchLib.c and interrupt driver
*/
IMPORT FUNCPTR sysIntLvlVecChkRtn;
IMPORT FUNCPTR sysIntLvlVecAckRtn;
IMPORT FUNCPTR sysIntLvlChgRtn;
IMPORT FUNCPTR sysIntLvlEnableRtn;
IMPORT FUNCPTR sysIntLvlDisableRtn;
/*
* vxBus function pointers used in intArchLib.c and interrupt driver
*/
IMPORT FUNCPTR _func_IntLvlVecChkRtn;
IMPORT FUNCPTR _func_IntLvlVecAckRtn;
IMPORT FUNCPTR _func_IntLvlChgRtn;
IMPORT FUNCPTR _func_IntLvlEnableRtn;
IMPORT void * intCtlrDevID;
IMPORT FUNCPTR _func_IntLvlDisableRtn;
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* (CPU == ARMARCH7M) */
#endif /* __INCintArmLibh */
vxworks-6.9/target/h/arch/arm/ivArm.h
+32
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@@ -0,0 +1,32 @@
/* ivArm.h - ARM interrupt vectors */
/* Copyright 1996-1997 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,09may96,cdp created
*/
#ifndef __INCivArmh
#define __INCivArmh
#ifdef __cplusplus
extern "C" {
#endif
/* macros to convert interrupt vectors <-> interrupt numbers */
#define IVEC_TO_INUM(intVec) ((int) (intVec))
#define INUM_TO_IVEC(intNum) ((VOIDFUNCPTR *) (intNum))
/* interrupt vector definitions are in the BSP header files */
#ifdef __cplusplus
}
#endif
#endif /* __INCivArmh */
vxworks-6.9/target/h/arch/arm/mmuArm1136jfLib.h
+117
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@@ -0,0 +1,117 @@
/* mmuArm1136jfLib.h - ARM 1136JF MMU library header file */
/*
* Copyright (c) 2004, 2010-2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01d,20dec11,jdw Add missing APIs to clear up warnings related to ttbr APIs
01c,29apr10,pad Moved extern C statement after include statements.
01b,09feb10,j_b update mmuArm1136jfTtbrSet for ASID support
01a,07dec04,jb created
*/
#ifndef __INCmmuArm1136jfLibh
#define __INCmmuArm1136jfLibh
#include "memLib.h"
#define MMU_ID_ARM1136JF 0x07B360
#include "mmuArmArch6PalLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* 1136JF Specific definitions follow */
/*
* Values to be used when mmuEnable() is called. This will be after the MMU has
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
* cache enable settings have been chosen.
*
* M 1 Enable MMU
* A 0 Disable address alignment fault
* C X ((D-)Cache Enable) Controlled by cacheLib
* W X (Write Buffer) Controlled by cacheLib
* P 1 (PROG32) should be set before this
* D 1 (DATA32) should be set before this
* L 1 (Late abort on earlier CPUs) ignore
* B X (Big/Little-endian) should be set before this
* S 1 (System)
* R 0 (ROM)
* F 0 Should be Zero
* Z X (Branch prediction enable on 810) Controlled by cacheLib
* I X (I-cache enable) Controlled by cacheLib
*
* For time being, do not enable the address alignment fault, as GCC
* currently generates unaligned accesses in its code, and switching this
* on will cause immediate faults. So, do not put it into the enable
* mask.
*
* We used to clear all the Reserved/Should Be Zero bits when the
* MMU/MPU was enabled, by including one bits for them in the definition
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
* the definitions of the bits within the MMU Control Register. The MMU
* Control register is initialised within romInit()/sysInit(), as the BSP
* is the only place where the particular details of the CPU/MMU are
* actually known. In general, it will be appropriate for the BSP to
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
* MMU is enabled, we will only change the bits we are particularly
* concerned about, by using a Read-Modify-Write strategy.
*/
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
#define MMUCR_MODE 0 /* This is specific to ARMARCH6 */
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_EXTENDED_PAGE)
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE | MMUCR_EXTENDED_PAGE)
#define MMU_MUST_SET_VALUE ( MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_W_ENABLE )
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
#define MMU_INIT_VALUE ( MMU_MUST_SET_VALUE | MMUCR_MODE)
#else
#define MMU_INIT_VALUE ( MMU_MUST_SET_VALUE | MMUCR_BIGEND | MMUCR_MODE)
#endif
#ifndef _ASMLANGUAGE
IMPORT void mmuArm1136jfLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
IMPORT void mmuArm1136jfTtbrSet (MMU_LEVEL_1_DESC *pTable, UINT32 asid);
IMPORT MMU_LEVEL_1_DESC * mmuArm1136jfTtbrGet (void);
IMPORT void mmuArm1136jfTtbrSetAll (UINT32 ttbr, UINT32 asid);
IMPORT UINT32 mmuArm1136jfTtbrGetAll (void);
IMPORT void mmuArm1136jfDacrSet (UINT32 dacrVal);
IMPORT void mmuArm1136jfTLBIDFlushEntry (VIRT_ADDR *addr);
IMPORT void mmuArm1136jfTLBIDFlushAll (void);
IMPORT void mmuArm1136jfAEnable (UINT32 cacheState);
IMPORT void mmuArm1136jfADisable (void);
IMPORT STATUS mmuArm1136jfPBitSet (VIRT_ADDR virtAddr, UINT32 size);
IMPORT STATUS mmuArm1136jfPBitClear (VIRT_ADDR virtAddr, UINT32 size);
IMPORT STATUS mmuArm1136jfPBitGet (VIRT_ADDR virtAddr );
IMPORT STATUS mmuArm1136jfAcrGet (void );
IMPORT void mmuArm1136jfAcrSet (UINT32 acrVal);
IMPORT STATUS mmuArm1136jfITcmrGet (void );
IMPORT void mmuArm1136jfITcmrSet (UINT32 acrVal);
IMPORT STATUS mmuArm1136jfDTcmrGet (void );
IMPORT void mmuArm1136jfDTcmrSet (UINT32 acrVal);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuArm1136jfLibh */
vxworks-6.9/target/h/arch/arm/mmuArm11MPCoreLib.h
+139
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@@ -0,0 +1,139 @@
/* mmuArm11MPCoreLib.h - ARM 11MPCORE MMU library header file */
/*
* Copyright (c) 2007, 2010-2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01d,20dec11,jdw Add missing APIs to clear up warnings related to ttbr APIs
01c,29apr10,pad Moved extern C statement after include statements.
01b,09feb10,j_b update mmuArm11MPCoreTtbrSet for ASID support
01a,09jul07,j_b Written
*/
#ifndef __INCmmuArm11MPCoreLibh
#define __INCmmuArm11MPCoreLibh
#include "memLib.h"
#define MMU_ID_ARM11MPCORE 0x0FB024 /* from CP15 ID Code Register c0 */
#include "mmuArmArch6PalLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* 11MPCORE Specific definitions follow */
/*
* Values to be used when mmuEnable() is called. This will be after the MMU has
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
* cache enable settings have been chosen.
*
* M 1 Enable MMU
* A 0 Disable address alignment fault
* C X ((D-)Cache Enable) Controlled by cacheLib
* W 1 (Write Buffer - obsolete) Should be One
* P 1 (PROG32 - obsolete) Should be One
* D 1 (DATA32 - obsolete) Should be One
* L 1 (Late abort - obsolete) Should be One
* B 0 (Big/Little-endian - unsupported) Should be Zero
* S 0 (System protection - deprecated)
* R 0 (ROM protection - deprecated)
* F 0 Should be Zero
* Z X (Branch prediction) Controlled by cacheLib
* I X (I-cache enable) Controlled by cacheLib
* V 0 (Vector table location: Normal/High Address)
* RR 1 (Random/Round-Robin cache replacement - unsupported) Should be One
* L4 0 Load instructions to PC set T bit
* DT 1 (Data TCM enable - obsolete) Write has no effect; Read as One
* - 0 Should be Zero
* IT 1 (Instruction TCM enable - unsupported) Write has no effect; Read as One
* - 0 Should be Zero
* - 0 Should be Zero
* FI 0 (Fast Interrupt enable - obsolete) Should be Zero
* U 0 Disable Unaligned data access enable
* XP 1 Enable eXtended Page table configuration (disable subpage AP bits)
* VE 0 (VEctored Interrupt- unsupported) Should be Zero
* EE 0 E bit of CPSR upon Exception
* - 0 Should be Zero
* NM 0 Disable NMFI behavior for FIQs
* TR 0 Disable TEX Remapping
* FA 0 Disable Force AP[0] as access bit
* - 0 Should be Zero
* - 0 Should be Zero
*
* NOTE: All defined control register bits are set to 0 on Reset, except
* V, U and EE which are dependent on system configuration pin signal levels.
*
* For time being, do not enable the address alignment fault, as GCC
* currently generates unaligned accesses in its code, and switching this
* on will cause immediate faults. So, do not put it into the enable
* mask.
*
* We used to clear all the Reserved/Should Be Zero bits when the
* MMU/MPU was enabled, by including one bits for them in the definition
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
* the definitions of the bits within the MMU Control Register. The MMU
* Control register is initialised within romInit()/sysInit(), as the BSP
* is the only place where the particular details of the CPU/MMU are
* actually known. In general, it will be appropriate for the BSP to
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
* MMU is enabled, we will only change the bits we are particularly
* concerned about, by using a Read-Modify-Write strategy.
*/
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
#define MMUCR_MODE 0 /* This is specific to ARMARCH6 */
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_EXTENDED_PAGE)
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE | MMUCR_EXTENDED_PAGE)
#define MMU_MUST_SET_VALUE ( MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_W_ENABLE )
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
#define MMU_INIT_VALUE ( MMU_MUST_SET_VALUE | MMUCR_MODE)
#else
#define MMU_INIT_VALUE ( MMU_MUST_SET_VALUE | MMUCR_BIGEND | MMUCR_MODE)
#endif
#ifndef _ASMLANGUAGE
IMPORT void mmuArm11MPCoreLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
IMPORT void mmuArm11MPCoreTtbrSet (MMU_LEVEL_1_DESC *pTable, UINT32 asid);
IMPORT MMU_LEVEL_1_DESC * mmuArm11MPCoreTtbrGet (void);
IMPORT void mmuArm11MPCoreTtbrSetAll (UINT32 ttbr, UINT32 asid);
IMPORT UINT32 mmuArm11MPCoreTtbrGetAll (void);
IMPORT void mmuArm11MPCoreDacrSet (UINT32 dacrVal);
IMPORT void mmuArm11MPCoreTLBIDFlushEntry (VIRT_ADDR *addr);
IMPORT void mmuArm11MPCoreTLBIDFlushAll (void);
IMPORT void mmuArm11MPCoreAEnable (UINT32 cacheState);
IMPORT void mmuArm11MPCoreADisable (void);
IMPORT STATUS mmuArm11MPCorePBitSet (VIRT_ADDR virtAddr, UINT32 size);
IMPORT STATUS mmuArm11MPCorePBitClear (VIRT_ADDR virtAddr, UINT32 size);
IMPORT STATUS mmuArm11MPCorePBitGet (VIRT_ADDR virtAddr);
IMPORT STATUS mmuArm11MPCoreAcrGet (void);
IMPORT void mmuArm11MPCoreAcrSet (UINT32 acrVal);
IMPORT STATUS mmuArm11MPCoreITcmrGet (void);
IMPORT void mmuArm11MPCoreITcmrSet (UINT32 acrVal);
IMPORT STATUS mmuArm11MPCoreDTcmrGet (void);
IMPORT void mmuArm11MPCoreDTcmrSet (UINT32 acrVal);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuArm11MPCoreLibh */
vxworks-6.9/target/h/arch/arm/mmuArm710aLib.h
+38
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@@ -0,0 +1,38 @@
/* mmuArm710aLib.h - ARM 710a MMU library header file */
/* Copyright 1998-2005 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01b,20jan99,cdp removed support for old ARM libraries.
01a,24nov98,cdp created.
*/
#ifndef __INCmmuArm710aLibh
#define __INCmmuArm710aLibh
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
IMPORT void mmuArm710aLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
IMPORT void mmuArm710aTtbrSet (LEVEL_1_DESC *);
IMPORT void mmuArm710aDacrSet (UINT32 dacrVal);
IMPORT void mmuArm710aTLBIDFlushEntry (void *addr);
IMPORT void mmuArm710aTLBIDFlushAll (void);
IMPORT void mmuArm710aAEnable (UINT32 cacheState);
IMPORT void mmuArm710aADisable (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuArm710aLibh */
vxworks-6.9/target/h/arch/arm/mmuArm920tLib.h
+130
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@@ -0,0 +1,130 @@
/* mmuArm920tLib.h - ARM 920T MMU library header file */
/*
* Copyright (c) 1999, 2004, 2005, 2007, 2010-2011 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01g,21dec11,jdw Update APIs to clear up warnings related to ttbr APIs
01f,29apr10,pad Moved extern C statement after include statements.
01e,25jan07,j_b add mmuArm920tTtbrGet prototype
01d,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01c,10feb05,jb Reverting to ROM mode for shared data/libraries
01b,09dec04,jb Palify Arm MMU
01a,04feb99,jpd created.
*/
#ifndef __INCmmuArm920tLibh
#define __INCmmuArm920tLibh
#define MMU_ID_ARM920T 0x029200
#include "mmuArmPalLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Values to be used when mmuEnable() is called. This will be after the MMU has
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
* cache enable settings have been chosen.
*
* M 1 Enable MMU
* A 0 Disable address alignment fault
* C X ((D-)Cache Enable) Controlled by cacheLib
* W X (Write Buffer) Controlled by cacheLib
* P 1 (PROG32) should be set before this
* D 1 (DATA32) should be set before this
* L 1 (Late abort on earlier CPUs) ignore
* B X (Big/Little-endian) should be set before this
* S 1 (System)
* R 0 (ROM)
* F 0 Should be Zero
* Z X (Branch prediction enable on 810) Controlled by cacheLib
* I X (I-cache enable) Controlled by cacheLib
*
* For time being, do not enable the address alignment fault, as GCC
* currently generates unaligned accesses in its code, and switching this
* on will cause immediate faults. So, do not put it into the enable
* mask.
*
* We used to clear all the Reserved/Should Be Zero bits when the
* MMU/MPU was enabled, by including one bits for them in the definition
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
* the definitions of the bits within the MMU Control Register. The MMU
* Control register is initialised within romInit()/sysInit(), as the BSP
* is the only place where the particular details of the CPU/MMU are
* actually known. In general, it will be appropriate for the BSP to
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
* MMU is enabled, we will only change the bits we are particularly
* concerned about, by using a Read-Modify-Write strategy.
*/
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
#define MMUCR_MODE MMUCR_ROM /* This MUST remain ROM for shared libraries */
#define MMUCR_FB_DISABLE (1<<30) /* nFastBus bit */
#define MMUCR_ASYNC_BIT (1<<31) /* Async bit*/
#define MMUCR_SYNC (1<<30) /* Synchronous mode */
#define MMUCR_ASYNC (3<<30) /* Asynchronous mode */
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE)
/*
* Values to be used when the MMU Control Register is initialised from
* within romInit.s or sysALib.s (before the MMU is enabled). Note that
* on 710A, this is also used to initialise the soft-copy of the MMU CR
* that we need to keep (in order to emulate Read-Modify-Write
* operations). So, the BSP *MUST* initialise the MMU CR with the value
* contained here, or else trouble will ensue. This restriction does
* not apply to non-710A BSPs, but caution must be exercised in choosing a
* value different to that defined here.
*/
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
/* W bit is Should Be One */
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_MODE | MMUCR_W_ENABLE)
#else /* _BYTE_ORDER == _LITTLE_ENDIAN now _BIG_ENDIAN */
/* big endian */
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_W_ENABLE | MMUCR_BIGEND | MMUCR_MODE)
#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
#ifndef _ASMLANGUAGE
IMPORT void mmuArm920tLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
IMPORT MMU_LEVEL_1_DESC * mmuArm920tTtbrGet (void);
IMPORT void mmuArm920tTtbrSet (MMU_LEVEL_1_DESC *);
IMPORT UINT32 mmuArm920tTtbrGetAll (void);
IMPORT void mmuArm920tTtbrSetAll (UINT32);
IMPORT void mmuArm920tDacrSet (UINT32 dacrVal);
IMPORT void mmuArm920tTLBIDFlushEntry (void *addr);
IMPORT void mmuArm920tTLBIDFlushAll (void);
IMPORT void mmuArm920tAEnable (UINT32 cacheState);
IMPORT void mmuArm920tADisable (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuArm920tLibh */
vxworks-6.9/target/h/arch/arm/mmuArm926eLib.h
+129
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/* mmuArm926eLib.h - ARM 926E MMU library header file */
/*
* Copyright (c) 2002, 2004, 2005, 2007, 2010-2011 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01h,21dec11,jdw Update APIs to clear up warnings related to ttbr APIs
01g,29apr10,pad Moved extern C statement after include statements.
01f,15oct07,j_b fix MMU_INIT_VALUE (WIND00060071)
01e,18apr05,jb Fix for SPR 108034
01d,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01c,10feb05,jb Reverting to ROM mode for shared data/libraries
01b,09dec04,jb Palify Arm MMU
01a,09dec02,jpd created, based on mmuArm920tLib.h, version 01a.
*/
#ifndef __INCmmuArm926eLibh
#define __INCmmuArm926eLibh
#define MMU_ID_ARM926E 0x069260
#include "mmuArmPalLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Values to be used when mmuEnable() is called. This will be after the MMU has
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
* cache enable settings have been chosen.
*
* M 1 Enable MMU
* A 0 Disable address alignment fault
* C X ((D-)Cache Enable) Controlled by cacheLib
* W X (Write Buffer) Controlled by cacheLib
* P 1 (PROG32) should be set before this
* D 1 (DATA32) should be set before this
* L 1 (Late abort on earlier CPUs) ignore
* B X (Big/Little-endian) should be set before this
* S 1 (System)
* R 0 (ROM)
* F 0 Should be Zero
* Z X (Branch prediction enable on 810) Controlled by cacheLib
* I X (I-cache enable) Controlled by cacheLib
*
* For time being, do not enable the address alignment fault, as GCC
* currently generates unaligned accesses in its code, and switching this
* on will cause immediate faults. So, do not put it into the enable
* mask.
*
* We used to clear all the Reserved/Should Be Zero bits when the
* MMU/MPU was enabled, by including one bits for them in the definition
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
* the definitions of the bits within the MMU Control Register. The MMU
* Control register is initialised within romInit()/sysInit(), as the BSP
* is the only place where the particular details of the CPU/MMU are
* actually known. In general, it will be appropriate for the BSP to
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
* MMU is enabled, we will only change the bits we are particularly
* concerned about, by using a Read-Modify-Write strategy.
*/
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
#define MMUCR_MODE MMUCR_ROM /* This MUST remain ROM for shared libraries */
#define MMUCR_L4_ENABLE (1<<15) /* L4 enable, ARMv4 behavior */
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE)
#define MMUCR_926E_SBO ((1<<18) | (1<<16)) /* Should Be One bits */
/*
* Values to be used when the MMU Control Register is initialised from
* within romInit.s or sysALib.s (before the MMU is enabled). Note that
* on 710A, this is also used to initialise the soft-copy of the MMU CR
* that we need to keep (in order to emulate Read-Modify-Write
* operations). So, the BSP *MUST* initialise the MMU CR with the value
* contained here, or else trouble will ensue. This restriction does
* not apply to non-710A BSPs, but caution must be exercised in choosing a
* value different to that defined here.
*/
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
/* W bit is Should Be One */
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_MODE | MMUCR_926E_SBO)
#else /* _BYTE_ORDER == _LITTLE_ENDIAN now _BIG_ENDIAN */
/* big endian */
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_BIGEND | MMUCR_MODE | MMUCR_926E_SBO)
#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
#ifndef _ASMLANGUAGE
IMPORT void mmuArm926eLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
IMPORT MMU_LEVEL_1_DESC * mmuArm926eTtbrGet ( void);
IMPORT void mmuArm926eTtbrSet (MMU_LEVEL_1_DESC *);
IMPORT UINT32 mmuArm926eTtbrGetAll (void);
IMPORT void mmuArm926eTtbrSetAll (UINT32);
IMPORT void mmuArm926eDacrSet (UINT32 dacrVal);
IMPORT void mmuArm926eTLBIDFlushEntry (void *addr);
IMPORT void mmuArm926eTLBIDFlushAll (void);
IMPORT void mmuArm926eAEnable (UINT32 cacheState);
IMPORT void mmuArm926eADisable (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuArm926eLibh */
vxworks-6.9/target/h/arch/arm/mmuArmArch6PalLib.h
+900
View File
@@ -0,0 +1,900 @@
/* mmuArmArch6PalLib.h - ARM MMU library header file */
/*
* Copyright (c) 2005-2014, 2016 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
20jan16,jnl Clean warning.
17apr14,c_l Fix TTBR & PTE attribute macros for enabled
ENABLE_CACHED_PAGE_TBL. (VXW6-73478)
02p,18sep13,zgl Add TTBR & PTE attribute macros for ARM A15 (WIND00434990)
02o,11jun12,jdw Fix TTBR & PTE attribute macros for ARM A9,
WIND00342202, WIND00342756
02n,02mar12,rec WIND00318272 - POSIX signals conformance
02m,09jan12,rec WIND00196578 - remove unused reference _func_armPageSource
02l,28sep11,jdw Add shared attribute to cached page tables (WIND00298486)
02k,13may11,jdw Clear TTBR0 bits during MMU init (WIND00258897)
02j,20apr11,jdw Add support for cached page tables
02i,25aug10,my_ add MMUCR_EE bit definition (WIND00229795)
02h,17jun10,m_h Thumb-2 Support
02g,29apr10,pad Moved extern C statement after include statements.
02f,02feb10,j_b add not-global PTE bit (nG), ASID support
02e,03nov09,j_b add INCLUDE_MMU_TEX_SUPPORT, undef INCLUDE_MMU_SUBPAGE_SUPPORT
02d,02nov09,j_b fix translation bug due to XN bit support (WIND00189001)
02c,07feb08,j_b Change MMU_DEF_L1_PAGE so bit 4 is 0 per VMSAv6
02b,23oct07,to added lockCnt and lockOwner to MMU_TRANS_TBL
02a,21sep07,to define MMU_PAGE_SIZE_SHIFT
01z,21sep07,j_b add _func_mmuFaultAddrGet prototype
01y,08aug07,j_b modify MMU_STATE_MASK_CACHEABLE for ARMv6 extended types;
add INCLUDE_MMU_EXTD_TYPE_SUPPORT
01x,30jul07,j_b fix special purpose attributes' masks
01w,03jul07,j_b add special purpose attributes for added ARMv6 extended types
(w/ TEX)
01v,20sep06,j_b add page optimization support
01u,11sep06,m_h fix vert-to-phys translation problem in upper bits
WIND00059266
01t,01mar06,m_h Manzano supersection support
01s,30mar05,jb Extracted from mmuArmArch6PalLib.h, 01u
*/
#ifndef __INCmmuArmArch6PalLibh
#define __INCmmuArmArch6PalLibh
#ifndef _ASMLANGUAGE
#include <memLib.h>
#include <semLib.h>
#ifdef __cplusplus
extern "C" {
#endif
#endif /* _ASMLANGUAGE */
/*
* The page size we will use. Ignore the sub-page, Large Page and Tiny
* Page features.
*/
#define MMU_PAGE_SIZE 4096
#define MMU_PAGE_SIZE_SHIFT 12
/*
* See the Virtual Memory System Architecture for ARMv6 (VMSAv6) section
* in the ARM Architecture Reference Manual (ARM DDI 0100) for MMU details.
*/
#define PAGE_SIZE MMU_PAGE_SIZE
#undef INCLUDE_MMU_APXBIT_SUPPORT
#define INCLUDE_MMU_APXBIT_SUPPORT
#undef INCLUDE_MMU_XNBIT_SUPPORT
#define INCLUDE_MMU_XNBIT_SUPPORT
#undef INCLUDE_MMU_EXTD_TYPE_SUPPORT
#define INCLUDE_MMU_EXTD_TYPE_SUPPORT
#undef INCLUDE_MMU_SBIT_SUPPORT
#define INCLUDE_MMU_SBIT_SUPPORT
#undef INCLUDE_MMU_TEX_SUPPORT
#define INCLUDE_MMU_TEX_SUPPORT
#undef INCLUDE_MMU_SUBPAGE_SUPPORT
/*
* The amount described by a Level 1 Descriptor, which equals the smallest
* amount of VM allocatable in VxWorks.
*/
#define MMU_PAGE_BLOCK_SIZE 0x100000 /* 1 MByte */
#define MMU_ADRS_TO_L1D_INDEX_SHIFT 20
#define MMU_PTE_INDEX_MASK 0x000FF000 /* extract PTE index from Virt Addr */
#define MMU_PTE_INDEX_SHIFT 12 /* shift to make that into PTE index */
#define MMU_L1D_TO_BASE_SHIFT 10 /* to turn L1D to PT base addr */
#define MMU_L1DSECTION_TO_BASE_SHIFT 20 /* L1D section to PT base addr */
#define MMU_L1DSECTION_BA_MASK 0xFFF00000 /* phys bits 20-31 */
#define MMU_L1DSSECTIONLO_TO_BASE_SHIFT 24 /* bits 24-31 of supersection */
#define MMU_L1DSSECTIONHI_TO_BASE_SHIFT 32 /* bits 32-35 of supersection */
#define MMU_L1DSSECTIONHI2_TO_BASE_SHIFT 5 /* bits 36-39 of supersection */
#define MMU_L1DSSECTIONLO_BA_MASK 0xFF000000 /* phys bits 24-31 */
#define MMU_L1DSSECTIONHI_BA_MASK 0x00F00000 /* phys bits 32-35 */
#define MMU_L1DSSECTIONHI2_BA_MASK 0x000001E0 /* phys bits 36-39 */
/* optional extended physical address bit fields */
#define MMU_L1DSSECTION_EXTD_BA_MASK \
(MMU_L1DSSECTIONHI_BA_MASK | MMU_L1DSSECTIONHI2_BA_MASK)
/* supersection base address packing */
#define MMU_L1DSSECTION_BA_SET(physAddr, L1desc) \
(L1desc = (unsigned int)((L1desc & ~MMU_L1DSSECTION_EXTD_BA_MASK) | \
( (((unsigned long long)(physAddr)) & MMU_L1DSSECTIONLO_BA_MASK) | \
((((unsigned long long)(physAddr)) >> 12) & \
MMU_L1DSSECTIONHI_BA_MASK) | \
((((unsigned long long)(physAddr)) >> 31) & \
MMU_L1DSSECTIONHI2_BA_MASK) )))
/* supersection base address unpacking */
#define MMU_L1DSSECTION_BA_GET(ssectDesc) \
((unsigned long long) \
( (unsigned long long)(ssectDesc & MMU_L1DSSECTIONLO_BA_MASK) | \
((unsigned long long)(ssectDesc & MMU_L1DSSECTIONHI_BA_MASK) \
<< 12) | \
((unsigned long long)(ssectDesc & MMU_L1DSSECTIONHI2_BA_MASK) \
<< 31) ))
/* Address translation masks */
#define MMU_ADDR_PI_MASK 0x00000FFF /* extract page index from Virt Addr */
#define MMU_PTE_BA_MASK 0xFFFFF000 /* extract phys base address from PTE */
#define MMU_ADDR_SI_MASK 0x000FFFFF /* extr section index from Virt Addr */
#define MMU_PTE_SECA_MASK 0xFFF00000 /* extract section base from L1 desc */
#define MMU_ADDR_SSI_MASK 0x00FFFFFF /* supersection index from virt */
#define MMU_PTE_SSECA_MASK 0xFF000000 /* supersection base from L1 desc */
#define MMU_PTE_SSECAX_MASK 0x00F00000 /* supersection extended bits L1 */
#define MMU_PTE_SSECAX_SHIFT 12 /* supersection extended bits shift */
/* Level 1 descriptor bit fields */
#define MMU_L1PD_TYPE_MASK 0x00000003 /* type bits [0:1] */
#define MMU_L1PD_CB_MASK 0x0000000C /* CB bits [3:2] */
#define MMU_L1PD_XN_MASK 0x00000010 /* eXecute Never bit [4] */
#define MMU_L1PD_DOMAIN_MASK 0x000001E0 /* domain bits [8:5] */
#define MMU_L1PD_P_MASK 0x00000200 /* P bit [9] */
#define MMU_L1PD_AP_MASK 0x00000C00 /* AP bits [10:11] */
#define MMU_L1PD_TEX_MASK 0x00007000 /* TEX bits [14:12] */
#define MMU_L1PD_APX_MASK 0x00008000 /* APX bit [15] */
#define MMU_L1PD_S_MASK 0x00010000 /* Shared bit [16] */
#define MMU_L1PD_NG_MASK 0x00020000 /* not-Global bit [17] */
#define MMU_L1PD_PTE_MASK 0xFFFFFC00 /* extract phys L2 PTE addr from L1PD */
/* # of shifts (right) to get fields in Level 1 descriptor */
#define MMU_L1PD_CB_SHIFT 2
#define MMU_L1PD_XN_SHIFT 4
#define MMU_L1PD_DOMAIN_SHIFT 5
#define MMU_L1PD_P_SHIFT 9
#define MMU_L1PD_AP_SHIFT 10
#define MMU_L1PD_TEX_SHIFT 12
#define MMU_L1PD_APX_SHIFT 15
#define MMU_L1PD_S_SHIFT 16
#define MMU_L1PD_NG_SHIFT 17
/* Level 2 descriptor bit fields */
#define MMU_PTE_TYPE_MASK 0x00000003 /* PTE type bits [0:1] */
#define MMU_PTE_SECT_XN_MASK 0x00000001 /* eXecute Never bit [0] */
#define MMU_PTE_SECT_CB_MASK 0x0000000C /* CB bits [3:2] */
#define MMU_PTE_SECT_AP_MASK 0x00000030 /* AP bits [5:4] */
#define MMU_PTE_SECT_TEX_MASK 0x000001C0 /* TEX bits [8:6] */
#define MMU_PTE_SECT_APX_MASK 0x00000200 /* APX bit [9] */
#define MMU_PTE_SECT_S_MASK 0x00000400 /* Shared bit [10] */
#define MMU_PTE_SECT_NG_MASK 0x00000800 /* not-Global bit [11] */
/* adjustment to translate fields: Level 1 <-> Level 2 descriptors */
#define MMU_L1L2_SECT_NG_SHIFT 6 /* nG-bit shift convert L1 to L2 */
#define MMU_L1L2_SECT_S_SHIFT 6 /* S-bit shift convert L1 to L2 */
#define MMU_L1L2_SECT_TEX_SHIFT 6 /* TEX shift convert L1 to L2 */
#define MMU_L1L2_SECT_AP_SHIFT 6 /* AP, APX shift convert L1 to L2 */
#define MMU_L1L2_SECT_XN_SHIFT 4 /* XN-bit shift convert L1 to L2 */
#define MMU_L1L2_SECT_CB_SHIFT 0 /* CB shift convert L1 to L2 */
/* Section and Supersection type and size macros */
#define MMU_PTE_SSECT_TYPE 0x00040000 /* supersection bit [18] */
#define MMU_PTE_SECT_TYPE_MASK 0x00040000 /* which type of section? */
#define MMU_SECT_SIZE 0x100000 /* section = 1MB */
#define MMU_SSECT_SIZE 0x1000000 /* supersection = 16MB */
#define MMU_NUM_VM_PAGES_IN_A_SECT 0x100 /* 1MB = 256 * 4KB pages */
#define MMU_NUM_VM_PAGES_IN_A_SSECT 0x1000 /* 16MB = 4096 * 4KB pages */
#define MMU_NUM_SECTS_IN_A_SSECT 0x10 /* 16 sections/supersection */
/*
* The Domain Access Control Register specifies the way in which access
* rights are treated for each of sixteen domains. For each domain the
* current state can be:
*
* 00 no access: all accesses generate aborts
* 01 client: access rights specified in page tables are checked.
* 10 reserved
* 11 manager: accesses not checked against page tables: all access allowed.
*/
#define MMU_DACR_VAL_NORMAL 1 /* client of 0 */
#define MMU_DACR_VAL_UNPROTECT 0x03 /* manager of 0 */
/* Level 1 Descriptor types */
#define MMU_DESC_TYPE_FAULT 0 /* any access will cause a fault */
#define MMU_DESC_TYPE_PAGE 1
#define MMU_DESC_TYPE_SECTION 2
#define MMU_DEF_L1_PAGE 0x00000001 /* domain zero, Page descriptor */
/*
* Section descriptors, such as might be used to set up an intermediate
* set of page tables on processors such as SA-1100/SA-1500 where this
* needs to be done from BSP initialization, before vm(Base)Lib sets up
* a proper set of page tables.
*/
#define MMU_RAM_SECT_DESC 0xC1E /* R/W cacheable bufferable domain 0 */
#define MMU_MINICACHE_SECT_DESC 0xC1A /* R/W C+ B- domain 0 */
#define MMU_OTHER_SECT_DESC 0xC12 /* R/W C- B- domain 0 */
/* Level 2 Descriptor or Page Table Entry (PTE) types */
#define MMU_PTE_TYPE_FAULT 0 /* any access will cause a fault */
#define MMU_PTE_TYPE_LG_PAGE 1 /* Large page descriptor */
#define MMU_PTE_TYPE_SM_PAGE 2 /* Small page descriptor */
#define MMU_PTE_TYPE_EX_PAGE 3 /* Extended page descriptor */
/*
* The Translation Table Base register (TTBR) points to a table of Level 1
* Descriptors. these are either Invalid Section descriptors, Section
* Descriptors, or Page Table Descriptors. If Page Table Descriptors, they
* each point to a table of Level 2 Page Descriptors, or Page Table Entries
* (PTEs).
* The 32-bit (virtual) address space allows for 4096 M. Each Level 1
* Descriptor describes a 1 M area of memory. There are therefore 4096 Level
* 1 Descriptors, and each table of 256 Level 2 Page Descriptors (PTEs)
* describes 256 4 kbyte pages.
*/
#define MMU_NUM_L1_DESCS 4096
#define MMU_NUM_L2_DESCS 256
#define MMU_L1_TABLE_SIZE (MMU_NUM_L1_DESCS * sizeof(MMU_LEVEL_1_DESC))
/* No. of pages a Level 1 Descriptor table takes up */
#define MMU_L1_DESC_PAGES (MMU_L1_TABLE_SIZE / MMU_PAGE_SIZE)
/* Size of a Page Table */
#define MMU_PAGE_TABLE_SIZE (MMU_NUM_L2_DESCS * sizeof(PTE))
/* Number of possible ASIDs */
#define MMU_NUM_ASIDS 256
#define VXWORKS_KERNEL_ASID 0 /* reserved ASID for VxWorks kernel */
/* Section and supersection L1 definitions follow */
#undef INCLUDE_MMU_SUPERSECTION_SUPPORT /* support supersection descriptors */
#define INCLUDE_MMU_SUPERSECTION_SUPPORT
#undef MMU_DEF_L1_SECTION_PAGE
#define MMU_DEF_L1_SECTION_PAGE 0x00000002 /* Section page descriptor */
#undef MMU_DEF_L1_SUPERSECTION_PAGE
#define MMU_DEF_L1_SUPERSECTION_PAGE 0x00040002 /* supersection */
#undef MMU_DEF_L1_SECTION_PAGE_MASK
#define MMU_DEF_L1_SECTION_PAGE_MASK 0x00040003 /* mask */
#undef MMU_STATE_SECTION_MASK_WRITABLE
#define MMU_STATE_SECTION_MASK_WRITABLE 0x00000030 /* All APn bits */
/*
* Architecture-dependent MMU states. These are states settable for pages and
* here they correspond to settings in the Page Table Entries (PTEs).
*
* We set Valid/Invalid by setting a Fault second-level descriptor rather
* than by using the Access Permissions within a small page second-level
* descriptor. This is because we will want to use the Access Permissions to
* control supervisor mode access and we cannot then use the AP bits
* to disallow access as the SR bits in the MMU Control register must be set
* to 10 in order to control read/write access from Supervisor mode.
*/
#define MMU_STATE_INVALID_STATE 0xFFFFFFFF
#define MMU_STATE_MASK_VALID 0x00000002 /* 2nd lvl desc bit 1 only */
#define MMU_STATE_MASK_WRITABLE 0x00000230 /* All APn bits */
#define MMU_STATE_MASK_CACHEABLE 0x000005CC /* S, TEX[0:2] + CB bits */
#define MMU_STATE_VALID MMU_PTE_TYPE_SM_PAGE /* set to page type */
#define MMU_STATE_VALID_NOT MMU_PTE_TYPE_FAULT /* set to type fault */
#define MMU_STATE_MASK_PROTECTION 0x00000231 /* APX + APn + XN bits */
#define MMU_STATE_SUP_RO 0x00000210 /* APX: 1 AP: 01 */
#define MMU_STATE_SUP_RW 0x00000010 /* APX: 0 AP: 01 */
#define MMU_STATE_SUP_RO_USR_RO 0x00000220 /* APX: 1 AP: 10 */
#define MMU_STATE_SUP_RW_USR_RO 0x00000020 /* APX: 0 AP: 10 */
#define MMU_STATE_SUP_RW_USR_RW 0x00000030 /* APX: 0 AP: 11 */
#define MMU_STATE_WRITABLE MMU_STATE_SUP_RW
#define MMU_STATE_WRITABLE_NOT MMU_STATE_SUP_RO
#define MMU_STATE_AP_SUP_RO 0x1 /* AP field: 01 */
#define MMU_STATE_AP_SUP_RW 0x1 /* AP field: 01 */
#define MMU_STATE_AP_SUP_RO_USR_RO 0x2 /* AP field: 10 */
#define MMU_STATE_AP_SUP_RW_USR_RO 0x2 /* AP field: 10 */
#define MMU_STATE_AP_SUP_RW_USR_RW 0x3 /* AP field: 11 */
#define MMU_STATE_AP_USR_RO_SUP_RO MMU_STATE_AP_SUP_RO_USR_RO
#define MMU_STATE_AP_USR_RO_SUP_RW MMU_STATE_AP_SUP_RW_USR_RO
#define MMU_STATE_AP_USR_RW_SUP_RW MMU_STATE_AP_SUP_RW_USR_RW
/* The Execute-Never bit is an extra permission check on readable addresses */
#define MMU_STATE_EXE_NOT 0x00000001 /* Execute-Never, XN bit */
#define MMU_STATE_SUP_RO_XN (MMU_STATE_SUP_RO | MMU_STATE_EXE_NOT)
#define MMU_STATE_SUP_RW_XN (MMU_STATE_SUP_RW | MMU_STATE_EXE_NOT)
#define MMU_STATE_SUP_RO_USR_RO_XN (MMU_STATE_SUP_RO_USR_RO | MMU_STATE_EXE_NOT)
#define MMU_STATE_SUP_RW_USR_RO_XN (MMU_STATE_SUP_RW_USR_RO | MMU_STATE_EXE_NOT)
#define MMU_STATE_SUP_RW_USR_RW_XN (MMU_STATE_SUP_RW_USR_RW | MMU_STATE_EXE_NOT)
/*
* Memory Region Attributes -
* cache access, write buffer access, coherency control
*/
#define MMU_STATE_STRONGLY_ORDERED 0x0 /* strongly ordered, shared */
#define MMU_STATE_CACHEABLE_NOT 0x0 /* backward compatible */
#define MMU_STATE_DEVICE_SHARED 0x00000004 /* device type, shared */
/* (bufferable, not cacheable) */
/* outer & inner write-thru cachable, no write alloc */
#define MMU_STATE_NORMAL_WRITETHROUGH 0x00000008
#define MMU_STATE_CACHEABLE_WRITETHROUGH 0x00000008 /* backward compatible */
#define MMU_STATE_NORMAL_WRITEBACK 0x0000000C /* write-back, no alloc */
#define MMU_STATE_CACHEABLE_COPYBACK 0x0000000C /* backward compatible */
#define MMU_STATE_NORMAL_NONCACHEABLE 0x00000040 /* non-cached, sharable */
#define MMU_STATE_DEVICE_NONSHARED 0x00000080 /* device, non-shared */
#define MMU_STATE_COPYBACK_ALLOC 0x0000004C /* write-back, sharable */
/* Define the flags used by Cached Page Tables for the PTEs */
/*
* - For MPCore(Cortex-A9 and ARM11), inner and outer write-back
* write-allocate cacheable.
* - For UPCore(Cortex-A9 and ARM11), inner and outer write-back
* no write-allocate cacheable.
*/
#ifdef _WRS_CONFIG_SMP
/* s=1,tex=001,c,b=11 */
#define MMU_STATE_CACHE_PTE_A9_FLAGS (MMU_STATE_COPYBACK_ALLOC | \
MMU_STATE_SHARED)
#else
/* s=0,tex=000,c,b=11 */
#define MMU_STATE_CACHE_PTE_A9_FLAGS (MMU_STATE_NORMAL_WRITEBACK)
#endif /* _WRS_CONFIG_SMP */
/* - For Cortex-A15 MPCore, inner and outer write-back, no write-allocate. */
#define MMU_STATE_WRITEBACK_PTE_A15_MPCORE (MMU_STATE_NORMAL_WRITEBACK)
/* - For others use the standard settings. */
#define MMU_STATE_WRITETHROUGH_PTE_GENERIC (MMU_STATE_NORMAL_WRITETHROUGH)
/*
* The following outer/inner noncacheable policy is also used as
* the basis for the rest of the outer/inner cache policies.
* (See the MMU_ATTR_OUT_x_IN_x macros for SPL_4 below.)
*/
#define MMU_STATE_OUT_OFF_IN_OFF 0x00000100 /* out/inner non-cached */
/* outer cache policy (TEX[1:0]) >> shift, relative to MMU_ATTR_OUT_x_IN_x */
#define MMU_STATE_OUTER_CACHE_POLICY_SHIFT 24
/* inner cache policy (CB) >> shift, relative to MMU_ATTR_OUT_x_IN_x */
#define MMU_STATE_INNER_CACHE_POLICY_SHIFT 26
/*
* Set the default state to be copyback. CACHEABLE_WRITETHROUGH can also be
* selected on those cache designs that permit it.
*/
#define MMU_STATE_CACHEABLE MMU_STATE_CACHEABLE_COPYBACK
/*
* Shared memory attribute -
* accessible by multiple processors or bus masters and must be kept coherent
*/
#define MMU_STATE_SHARED 0x00000400 /* Shared bit */
#define MMU_STATE_WRITETHROUGH_SHARED \
(MMU_STATE_CACHEABLE_WRITETHROUGH | MMU_STATE_SHARED)
#define MMU_STATE_COPYBACK_SHARED \
(MMU_STATE_CACHEABLE_COPYBACK | MMU_STATE_SHARED)
#define MMU_STATE_NONCACHEABLE_SHARED \
(MMU_STATE_NORMAL_NONCACHEABLE | MMU_STATE_SHARED)
/*
* Global memory attribute -
* not-Global causes ASID to be associated with address translation
*/
#define MMU_STATE_NOT_GLOBAL 0x00000800 /* not-Global bit */
/*
* Architecture-specific attributes
*
* The following ARMv6-specific aliases are provided for ease of use.
*
* NOTE: MMU_ATTR_CACHE_GUARDED is used as MMU_ATTR_CACHE_IO (its former name).
*/
/* Strongly Ordered - same as MMU_ATTR_CACHE_OFF for backward compatibility */
#define MMU_ATTR_STRONGLY_ORDERED (MMU_ATTR_CACHE_OFF)
/* Shared Device */
#define MMU_ATTR_DEVICE_SHARED_MSK (MMU_ATTR_CACHE_MSK)
#define MMU_ATTR_DEVICE_SHARED (MMU_ATTR_CACHE_GUARDED | MMU_ATTR_CACHE_OFF | \
MMU_ATTR_CACHE_COHERENCY)
#define MMU_ATTR_BUFFERABLE MMU_ATTR_DEVICE_SHARED /* backward compatible */
/* Non-Shared Device */
#define MMU_ATTR_DEVICE_NONSHARED_MSK MMU_ATTR_DEVICE_SHARED_MSK
#define MMU_ATTR_DEVICE_NONSHARED (MMU_ATTR_CACHE_GUARDED | \
MMU_ATTR_CACHE_OFF)
/*
* Special Purpose Attributes:
* When setting any of these attributes, it is necessary to:
*
* 1. specify MMU_ATTR_SPL_MSK ORred with MMU_ATTR_CACHE_MSK in the mask
* argument to the routine, and:
* 2. specify the appropriate cache state ORed in to the state argument
* to the routine, unless the cache state is implied.
*
* So, to set a page as normal, noncacheable memory, it is necessary to
* specify both MMU_ATTR_SPL_0 and specify MMU_ATTR_CACHE_OFF in the
* state argument.
*
* To "unset" the special attributes, specify MMU_ATTR_CACHE_MSK in
* the mask parameter (without MMU_ATTR_SPL_MSK) and specify the
* cacheability required in the state argument.
*/
/* Normal, Noncacheable memory */
#define MMU_ATTR_NORMAL_NONCACHEABLE_MSK (MMU_ATTR_SPL_MSK | MMU_ATTR_CACHE_MSK)
#define MMU_ATTR_NORMAL_NONCACHEABLE (MMU_ATTR_SPL_0 | MMU_ATTR_CACHE_OFF)
#define MMU_ATTR_NORMAL_NONCACHEABLE_SHARED (MMU_ATTR_NORMAL_NONCACHEABLE | \
MMU_ATTR_CACHE_COHERENCY)
/*
* Outer and Inner Cache Write-Back, Write Allocate (same as XScale)
* -- this can also be ORed with MMU_ATTR_CACHE_COHERENCY to set as Shared
*/
#define MMU_ATTR_WRITEALLOCATE_MSK (MMU_ATTR_SPL_MSK | MMU_ATTR_CACHE_MSK)
#define MMU_ATTR_WRITEALLOCATE (MMU_ATTR_SPL_3 | MMU_ATTR_CACHE_COPYBACK)
#define MMU_ATTR_WRITEALLOCATE_SHARED (MMU_ATTR_WRITEALLOCATE | \
MMU_ATTR_CACHE_COHERENCY)
/*
* Individually Specified Outer and Inner Cache Policies
* -- ORed with TEX[1:0] and CB encodings for each, shifted to prevent
* conflicts with common MMU_ATTR_ protection, cache, valid and SPL bits:
* OFF - Noncacheable, Unbuffered
* WBWA - Write-Back cached, Write Allocate, Buffered
* WTNA - Write-Through cached, No Allocate on Write, Buffered
* WBNA - Write-Back cached, No Allocate on Write, Buffered
*
* -- these can also be ORed with MMU_ATTR_CACHE_COHERENCY to set as Shared,
* but since MMU_ATTR_CACHE_COHERENCY is invalid by itself
* MMU_ATTR_CACHE_OFF is added to all of them (and will be disregarded)
*/
#define MMU_ATTR_CACHE_POLICY_SHIFT 28 /* cache policy encoding << shift */
#define MMU_ATTR_CACHE_OUTER_POLICY_MSK 0xC0000000 /* outer policy code bits */
#define MMU_ATTR_CACHE_INNER_POLICY_MSK 0x30000000 /* inner policy code bits */
#define MMU_ATTR_OUT_X_IN_Y_MSK (MMU_ATTR_SPL_MSK | MMU_ATTR_CACHE_MSK)
#define MMU_ATTR_OUT_OFF_IN_OFF (MMU_ATTR_SPL_4 | MMU_ATTR_CACHE_OFF)
#define MMU_ATTR_OUT_OFF_IN_WBWA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0x1 << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_OFF_IN_WTNA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0x2 << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_OFF_IN_WBNA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0x3 << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WBWA_IN_OFF (MMU_ATTR_OUT_OFF_IN_OFF | \
(0x4 << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WBWA_IN_WBWA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0x5 << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WBWA_IN_WTNA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0x6 << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WBWA_IN_WBNA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0x7 << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WTNA_IN_OFF (MMU_ATTR_OUT_OFF_IN_OFF | \
(0x8 << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WTNA_IN_WBWA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0x9 << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WTNA_IN_WTNA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0xA << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WTNA_IN_WBNA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0xB << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WBNA_IN_OFF (MMU_ATTR_OUT_OFF_IN_OFF | \
(0xC << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WBNA_IN_WBWA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0xD << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WBNA_IN_WTNA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0xE << MMU_ATTR_CACHE_POLICY_SHIFT))
#define MMU_ATTR_OUT_WBNA_IN_WBNA (MMU_ATTR_OUT_OFF_IN_OFF | \
(0xF << MMU_ATTR_CACHE_POLICY_SHIFT))
/* MMU Control Register bit allocations */
#define MMUCR_M_ENABLE (1<<0) /* MMU enable */
#define MMUCR_A_ENABLE (1<<1) /* Address alignment fault enable */
#define MMUCR_C_ENABLE (1<<2) /* (data) cache enable */
#define MMUCR_W_ENABLE (1<<3) /* write buffer enable */
#define MMUCR_PROG32 (1<<4) /* PROG32 */
#define MMUCR_DATA32 (1<<5) /* DATA32 */
#define MMUCR_L_ENABLE (1<<6) /* Late abort on earlier CPUs */
#define MMUCR_BIGEND (1<<7) /* Big-endian (=1), little-endian (=0) */
#define MMUCR_SYSTEM (1<<8) /* System bit, modifies MMU protections */
#define MMUCR_ROM (1<<9) /* ROM bit, modifies MMU protections */
#define MMUCR_F (1<<10) /* Should Be Zero */
#define MMUCR_Z_ENABLE (1<<11) /* Branch prediction enable on 810 */
#define MMUCR_I_ENABLE (1<<12) /* Instruction cache enable */
#define MMUCR_V_ENABLE (1<<13) /* Exception vectors remap to 0xFFFF0000 */
#define MMUCR_ALTVECT MMUCR_V_ENABLE /* alternate vector select */
#define MMUCR_RR_ENABLE (1<<14) /* Round robin cache replacement enable */
#define MMUCR_ROUND_ROBIN MMUCR_RR_ENABLE /* round-robin placement */
#define MMUCR_DISABLE_TBIT (1<<15) /* disable TBIT */
#define MMUCR_ENABLE_DTCM (1<<16) /* Enable Data TCM */
#define MMUCR_ENABLE_ITCM (1<<18) /* Enable Instruction TCM */
#define MMUCR_UNALIGNED_ENABLE (1<<22) /* Enable unaligned access */
#define MMUCR_EXTENDED_PAGE (1<<23) /* Use extended PTE format */
#define MMUCR_VECTORED_INTERRUPT (1<<24) /* Enable VIC Interface */
#define MMUCR_EE (1<<25) /* Exception Endianness bit */
#define MMUCR_THUMB_EXCEPTIONS (1<<30) /* Exceptions are Thumb */
#define ADDR_TO_PAGE 12 /* shift phys address to PTE page base address*/
/* MMU TTBR register fields for v6 and v7a */
#define MMU_TTBR_BASE_ADDR_MASK 0xFFFFC000
#define MMU_TTBR_C_MASK 0x00000001
#define MMU_TTBR_RGN_MASK 0x00000018
#define MMU_TTBR_IRGN_MASK 0x00000041
#define MMU_TTBR_NOS_MASK 0x00000020
#define MMU_TTBR_S_MASK 0x00000002
#define MMU_TTBR_IMP_MASK 0x00000004
/* RGN field bits */
#define MMU_TTBR_RGN_NML_NC 0x00000000 /* Normal, outer not cached */
#define MMU_TTBR_RGN_NML_WB_WA 0x00000008 /* Normal, outer write-back,
write-allocate cached */
#define MMU_TTBR_RGN_NML_WT 0x00000010 /* Normal, outer write-thru cached */
#define MMU_TTBR_RGN_NML_WB 0x00000018 /* Normal, outer write-back, */
/* no write-allocate cached */
/* IRGN field bits */
#define MMU_TTBR_IRGN_NML_NC 0x00000000 /* Normal, inner not cached */
#define MMU_TTBR_IRGN_NML_WT 0x00000001 /* Normal, inner write-thru cached */
#define MMU_TTBR_IRGN_NML_WB_WA 0x00000040 /* Normal, inner write-back,
write-allocate cached */
#define MMU_TTBR_IRGN_NML_WB 0x00000041 /* Normal, inner write-back, */
/* no write-allocate cached */
/* C Bit fields */
#define MMU_TTBR_C_NML_NC 0x00000000 /* Normal, not cached */
#define MMU_TTBR_C_NML_C 0x00000001 /* Normal, cached */
/* S & NOS fields */
#define MMU_TTBR_S 0x00000002 /* Inner Shared */
#define MMU_TTBR_NOS 0x00000020 /* Not Outer Shared */
#ifdef _WRS_CONFIG_SMP
/*
* ARM Cortex-A9 MPCore and ARM11 MPCore do not support inner write-through
* cached page tables. Cortex-A9 MPCore L2 can support write-through cached page
* tables. Setup TTBR for normal memory, inner and outer write-back
* write-allocate cacheable.
*/
/* IRGN[0]=1,NOS=1,RGN=0b01,S=1 */
#define MMU_TTBR_CACHE_PTE_A9_FLAGS (MMU_TTBR_RGN_NML_WB_WA | \
MMU_TTBR_IRGN_NML_WB_WA | \
MMU_TTBR_S | \
MMU_TTBR_NOS)
#else
/*
* ARM Cortex-A9 UPCore and ARM11 UPCore.
* Setup TTBR for normal memory, inner and outer write-back
* no write-allocate cacheable.
*/
/* IRGN[0]=1,NOS=0,RGN=0b11,S=0,C=1 */
#define MMU_TTBR_CACHE_PTE_A9_FLAGS (MMU_TTBR_RGN_NML_WB | \
MMU_TTBR_IRGN_NML_WB)
#endif /* _WRS_CONFIG_SMP */
/*
* ARM Cortex-A15 MPCore does not support write-through for L1 and L2 cache.
* Here, setup TTBR for inner and outer write-back, no write-allocate cached.
*/
#define MMU_TTBR_CACHE_PTE_A15_MPCORE ( MMU_TTBR_IRGN_NML_WB | \
MMU_TTBR_RGN_NML_WB )
/*
* For ARM Cortex-A8, or generic ARMv7 & ARMv6 cores:
*
* Select the mask for the single core or MPCore format for the TTBR. By
* default we support the MPCore format because it is compatible with the UP
* format and it is safer to zero out all the bits which are unused. Select
* inner and outer write-through cached page tables.
*/
#ifdef _WRS_CONFIG_USE_MC_TTBR_FMT
#define MMU_TTBR_CACHE_PTE_GENERIC \
( MMU_TTBR_IRGN_NML_WT | MMU_TTBR_RGN_NML_WT )
#else /* _WRS_CONFIG_USE_MC_TTBR_FMT */
#define MMU_TTBR_CACHE_PTE_GENERIC \
( MMU_TTBR_C_NML_C | MMU_TTBR_RGN_NML_WT )
#endif /* _WRS_CONFIG_USE_MC_TTBR_FMT */
#ifndef _ASMLANGUAGE
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
/* little-endian */
/* First level page descriptors */
typedef struct
{
UINT type : 2; /* descriptor type, 1 => page */
UINT pad1 : 2; /* SBZ */
UINT pad2 : 1; /* SBO */
UINT domain : 4; /* domain number */
UINT pbit : 1; /* 'P' bit */
UINT addr : 22; /* base address of page table */
} PAGE_DESC_FIELD;
/* First level "section" descriptor */
typedef struct
{
UINT type : 2; /* descriptor type, 2 => section */
UINT bbit : 1; /* bufferable-bit */
UINT cbit : 1; /* cacheable-bit */
UINT xnbit : 1; /* XN-bit */
UINT domain : 4; /* domain number */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT ap : 2; /* AP */
UINT tex : 3; /* TEX */
UINT apx : 1; /* APX */
UINT sbit : 1; /* S-bit */
UINT nG : 1; /* nG-bit */
UINT super : 1; /* 1 => supersection */
UINT pad1 : 1; /* SBZ */
UINT addr : 12; /* base address of page table */
} SECTION_DESC_FIELD;
/* First level "supersection" descriptor */
typedef struct
{
UINT type : 2; /* descriptor type, 2 => section */
UINT bbit : 1; /* bufferable-bit */
UINT cbit : 1; /* cacheable-bit */
UINT xnbit : 1; /* XN-bit */
UINT addrHi2: 4; /* phys address 39:36 */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT ap : 2; /* AP */
UINT tex : 3; /* TEX */
UINT apx : 1; /* APX */
UINT sbit : 1; /* S-bit */
UINT nG : 1; /* nG-bit */
UINT super : 1; /* 1 => supersection */
UINT pad1 : 1; /* SBZ */
UINT addrHi : 4; /* phys address 35:32 */
UINT addrLo : 8; /* phys address 31:24 */
} SUPERSECTION_DESC_FIELD;
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
typedef struct
{
UINT type : 2; /* page type, 3 => extended small page */
UINT cb : 2; /* cacheable/bufferable bits */
UINT ap : 2; /* access permission */
UINT tex : 3; /* type extension field */
UINT apx : 1; /* access permission extension field */
UINT sbz : 2; /* should be zero */
UINT addr : 20; /* page base address */
} PTE_FIELD;
#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
/* big-endian */
/* First level page descriptors */
typedef struct
{
UINT addr : 22; /* base address of page table */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT domain : 4; /* domain number */
UINT pad2 : 1; /* SBO */
UINT pad1 : 2; /* SBZ */
UINT type : 2; /* descriptor type, 1 => page */
} PAGE_DESC_FIELD;
/* First level "section" descriptor */
typedef struct
{
UINT addr : 12; /* base address of page table */
UINT pad1 : 1; /* SBZ */
UINT super : 1; /* 1 => supersection */
UINT nG : 1; /* nG-bit */
UINT sbit : 1; /* S-bit */
UINT apx : 1; /* APX */
UINT tex : 3; /* AP */
UINT ap : 2; /* AP */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT domain : 4; /* domain number */
UINT xnbit : 1; /* XN-bit */
UINT cbit : 1; /* C-bit */
UINT bbit : 1; /* B-bit */
UINT type : 2; /* descriptor type, 2 => section */
} SECTION_DESC_FIELD;
/* First level "supersection" descriptor */
typedef struct
{
UINT addrLo : 8; /* phys address 31:24 */
UINT addrHi : 4; /* phys address 35:32 */
UINT pad1 : 1; /* SBZ */
UINT super : 1; /* 1 => supersection */
UINT nG : 1; /* nG-bit */
UINT sbit : 1; /* S-bit */
UINT apx : 1; /* APX */
UINT tex : 3; /* AP */
UINT ap : 2; /* AP */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT addrHi2: 4; /* phys address 39:36 */
UINT xnbit : 1; /* XN-bit */
UINT cbit : 1; /* C-bit */
UINT bbit : 1; /* B-bit */
UINT type : 2; /* descriptor type, 2 => section */
} SUPERSECTION_DESC_FIELD;
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
typedef struct
{
UINT addr : 20; /* page base address */
UINT sbz : 2; /* should be zero */
UINT apx : 1; /* access permission extension field */
UINT tex : 3; /* type extension field */
UINT ap : 2; /* access permission */
UINT cb : 2; /* cacheable/bufferable bits */
UINT type : 2; /* page type, 3 => extended small page */
} PTE_FIELD;
#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
/* First level descriptor access */
typedef union
{
PAGE_DESC_FIELD fields;
SECTION_DESC_FIELD sectionFields;
SUPERSECTION_DESC_FIELD supersectionFields;
UINT32 bits;
} MMU_LEVEL_1_DESC;
/* Second level descriptor access */
typedef union
{
PTE_FIELD fields;
UINT32 bits;
} PTE;
/*
* Structure for MMU translation table access - normally used to get a pointer
* to the first-level translation table.
* To support page table optimization, a second first-level table and a
* semaphore are needed.
* The initial, unoptimized set of page tables will be set as the active
* translation tables (via pLevel1Table) while optimization or deoptimization
* is in progress using the inactive second translation table (pAltLevel1Table).
* After each page table optimization or deoptimization operation has
* completed, the second translation table will be set as the active
* translation table. The initial set of page tables retain their
* links to level 2 pages, which may otherwise be lost after optimization.
* Any non-optimization changes to the active first-level table will also be
* made to the inactive first-level table.
* The semaphore is used to prevent corruption of the tables.
*/
typedef struct mmuTransTblStruct
{
MMU_LEVEL_1_DESC *pLevel1Table; /* active MMU table */
MMU_LEVEL_1_DESC *pAltLevel1Table; /* inactive MMU table */
VX_MUTEX_SEMAPHORE(mmuTransTblSem); /* MMU tables' semaphore */
UINT32 lockCnt; /* lock count */
atomic_t lockOwner; /* lock owner */
UINT8 asid; /* ASID/context id */
} MMU_TRANS_TBL;
/* Externally visible mmuLib, mmuMapLib and mmuALib2 routines */
IMPORT UINT32 mmuReadId (void);
IMPORT PHYS_ADDR mmuVirtToPhys (VIRT_ADDR addr);
IMPORT VIRT_ADDR mmuPhysToVirt (PHYS_ADDR addr);
IMPORT UINT32 (* mmuCrGet) (void);
IMPORT void (* mmuModifyCr) (UINT32 value, UINT32 mask);
IMPORT UINT32 mmuHardCrGet (void);
IMPORT UINT32 mmuSoftCrGet (void);
IMPORT void mmuModifyHardCr (UINT32 value, UINT32 mask);
IMPORT void mmuModifySoftCr (UINT32 value, UINT32 mask);
IMPORT UINT32 (* _func_mmuFaultAddrGet) (void);
IMPORT UINT32 (* _func_mmuFaultStatusGet) (void);
IMPORT UINT32 (* _func_mmuIFaultStatusGet) (void);
IMPORT UINT32 mmuIFsrGet (void); /* CP15_IFSR only available with MMUs */
IMPORT UINT32 mmuFarGet (void); /* CP15_FAR only available with MMUs */
IMPORT UINT32 mmuFsrGet (void); /* CP15_FSR only available with MMUs */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuArmArch6PalLibh */
vxworks-6.9/target/h/arch/arm/mmuArmLib.h
+107
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@@ -0,0 +1,107 @@
/* mmuArmLib.h - ARM MMU library header file */
/*
* Copyright (c) 1996-2001, 2003-2008, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
02a,29jul10,pad Moved extern C statement after include statements.
01z,04jun10,wqi corrected spelling mistake. (WIND00203804)
01y,11jul07,j_b add ARMMMU_11MPCORE support
01x,12jun08,j_b add Cortex-A MMU support
01w,13jul06,m_h MPU Support
01v,25jan06,m_h Manzano Support
01u,29mar05,jb Adding ARMARCH6 and 1136 support
01t,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01s,09dec04,jb Palifying mmu
See mmuArmPalLib.h for previous contents
01r,10aug04,scm adjust for removal of MPU support, add 926E...
01q,18sep03,scm BASE 6 port...
01p,04oct01,scm add extended small page table support for XScale...
01o,23jul01,scm change XScale name to conform to coding standards...
01n,11jul01,scm add support for XScale...
01m,29mar01,jpd removed externs for mmyPhysToVirt & mmuVirtToPhys (SPR #63512).
01l,19mar01,jpd redefine MMU_ATTR_BUFFERABLE and MMU_ATTR_CACHE_MINICACHE
(SPR #64788).
01k,16aug00,jpd no longer clear MMUCR Reserved/Should Be Zero bits (SPR #33608)
01j,14jun00,jpd reworked MMU_STATE_WRITETHROUGH definition.
01i,17feb00,jpd T3: prefixed defs with MMU_; added new defs; changed SR to 10.
01h,07sep99,jpd added ARM740T, ARM920T support.
01g,20jan99,cdp removed support for old ARM libraries;
add prefix to MMU_IDs.
01f,24nov98,jpd added ARM940T support, added other CPU ids; removed
mmuIntLock/Unlock as intIFLock/Unlock to be used instead;
cdp restructured for multiple cache/MMU libraries; big-endian.
01e,09mar98,jpd added MMUCTR_ definitions for ARM810 and extra cache states.
01d,20jan98,jpd added _func_armPhysToVirt() etc. function pointers.
01c,17sep97,jpd added MMU_INIT_VALUE and mmuIntLock/Unlock definitions.
01b,24jan97,jpd modified mmuAEnable definition.
01a,09may96,cdp created.
*/
#ifndef __INCmmuArmLibh
#define __INCmmuArmLibh
#if (ARMMMU != ARMMMU_NONE)
#if (ARMMMU == ARMMMU_710A)
#include "mmuArm710aLib.h"
#elif (ARMMMU == ARMMMU_720T)
#include "mmuArm720tLib.h"
#elif (ARMMMU == ARMMMU_810)
#include "mmuArm810Lib.h"
#elif (ARMMMU == ARMMMU_SA110)
#include "mmuArmSA110Lib.h"
#elif (ARMMMU == ARMMMU_SA1100)
#include "mmuArmSA1100Lib.h"
#elif (ARMMMU == ARMMMU_SA1500)
#include "mmuArmSA1500Lib.h"
#elif (ARMMMU == ARMMMU_920T)
#include "mmuArm920tLib.h"
#elif (ARMMMU == ARMMMU_926E)
#include "mmuArm926eLib.h"
#elif (ARMMMU == ARMMMU_XSCALE)
#include "mmuArmXSCALELib.h"
#elif (ARMMMU == ARMMMU_MANZANO)
#include "mmuArmManzanoLib.h"
#elif (ARMMMU == ARMMMU_1020E)
#include "mmuArm1020eLib.h"
#elif (ARMMMU == ARMMMU_1022E)
#include "mmuArm1022eLib.h"
#elif (ARMMMU == ARMMMU_1136JF)
#include "mmuArm1136jfLib.h"
#elif (ARMMMU == ARMMMU_CORTEXA8)
#include "mmuCortexA8Lib.h"
#elif (ARMMMU == ARMMMU_11MPCORE)
#include "mmuArm11MPCoreLib.h"
#elif (ARMMMU == ARMMPU_740T)
#include "mpuArm740tLib.h"
#elif (ARMMMU == ARMMPU_940T)
#include "mpuArm940tLib.h"
#elif (ARMMMU == ARMMPU_946E)
#include "mpuArm946eLib.h"
#else
#error "Unknown MMU specified"
#endif /* ARMMMU == ARMMMU_710A */
#endif /* (ARMMMU != ARMMMU_NONE) */
#ifdef __cplusplus
extern "C" {
#endif
/* Any expression using C statements must be defined here */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuArmLibh */
vxworks-6.9/target/h/arch/arm/mmuArmLpaeLib.h
+479
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@@ -0,0 +1,479 @@
/* mmuArmLpaeLib.h - ARM LPAE MMU library header file */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
17apr14,c_l add the write protection of L2 page table. (VXW6-73478)
01a,01jun13,zgl written
*/
#ifndef __INCmmuArmLpaeLibh
#define __INCmmuArmLpaeLibh
#ifndef _ASMLANGUAGE
/* includes */
#include <memLib.h>
#include <semLib.h>
#ifdef __cplusplus
extern "C" {
#endif
#endif /* _ASMLANGUAGE */
/* defines */
/* make mask, h = end bit, l = start bit */
#define MAKE_MASK_64(h,l) (((1ULL << (h + 1)) - 1) & ~((1ULL << l) - 1))
#define MAKE_MASK_32(h,l) (((1UL << (h + 1)) - 1) & ~((1UL << l) - 1))
/*
* The page size we will use. Ignore the sub-page, Large Page and Tiny
* Page features.
*/
#define MMU_PAGE_SIZE 4096
#define PAGE_SIZE MMU_PAGE_SIZE
#define MMU_ADRS_TO_L1D_INDEX_SHIFT 30
#define MMU_ADRS_TO_L2D_INDEX_SHIFT 21
#define MMU_PAGE_SIZE_SHIFT 12
#define MMU_LPAE_NO_BITS_PHYS_ADDR 40
/* get Level 2 index */
#define MMU_L2PD_INDEX_GET(vaddr) \
((vaddr >> MMU_ADRS_TO_L2D_INDEX_SHIFT) & (MMU_NUM_L2_DESCS - 1))
#define MMU_PTE_INDEX_MASK MAKE_MASK_32(20,12) /* extract PTE index from */
/* Virt Addr */
#define MMU_PTE_BA_MASK MAKE_MASK_64(39,12) /* extract phys base address */
#define MMU_PTE_INDEX_SHIFT 12 /* shift to make that into PTE index */
#define MMU_ADDR_PI_MASK 0x00000FFF /* extract page offset from Virt Addr */
/* extract phys L2 page table base addr from L1PD */
#define MMU_L1PD_L2TBL_MASK MAKE_MASK_64(39,12)
/* extract phys L3 page table base addr from L2PD */
#define MMU_L2PD_L3TBL_MASK MMU_L1PD_L2TBL_MASK
/* Level 1/2 Descriptor types */
#define MMU_DESC_TYPE_FAULT 0x0 /* any access will cause a fault */
#define MMU_DESC_TYPE_BLOCK 0x1 /* block descriptor */
#define MMU_DESC_TYPE_TABLE 0x3 /* page table descriptor */
/* defalt Descriptor types for Level 1/2 */
#define MMU_DEF_L1_PAGE MMU_DESC_TYPE_TABLE
#define MMU_DEF_L2_PAGE MMU_DEF_L1_PAGE
/* Level 3 Descriptor or Page Table Entry (PTE) types */
#define MMU_PTE_TYPE_FAULT 0x0 /* any access will cause a fault */
#define MMU_PTE_TYPE_PAGE 0x3 /* page descriptor */
#define MMU_PTE_AF (1 << 10) /* access flag bit */
/* No. of Descriptor for each page table level */
#define MMU_NUM_L1_DESCS 4
#define MMU_NUM_L2_DESCS 512
#define MMU_NUM_L3_DESCS 512
#define MMU_L1_TABLE_SIZE MMU_PAGE_SIZE
/* No. of pages a Level 1 Descriptor table takes up */
#define MMU_L1_DESC_PAGES (MMU_L1_TABLE_SIZE / MMU_PAGE_SIZE)
/* The amount described by a L1 Descriptor */
#define MMU_L1_DESC_RANGE (MMU_NUM_L2_DESCS * MMU_NUM_L3_DESCS * MMU_PAGE_SIZE)
/* Size of a Page Table */
#define MMU_PAGE_TABLE_SIZE MMU_PAGE_SIZE
/*
* The amount described by a L2 Descriptor, which equals the smallest
* amount of VM allocatable in VxWorks.
*/
#define MMU_L2_DESC_RANGE (MMU_NUM_L3_DESCS * MMU_PAGE_SIZE) /* 2 MBytes */
#define MMU_PAGE_BLOCK_SIZE MMU_L2_DESC_RANGE
/* Number of possible ASIDs */
#define MMU_NUM_ASIDS 256
#define VXWORKS_KERNEL_ASID 0 /* reserved ASID for VxWorks kernel */
/*
* Architecture-dependent MMU states. These are states settable for pages and
* here they correspond to settings in the Page Table Entries (PTEs).
*/
#define MMU_STATE_INVALID_STATE 0xFFFFFFFF
#define MMU_STATE_MASK_VALID 0x00000003 /* bits[1:0] for PTE state */
#define MMU_STATE_MASK_WRITABLE 0x000000C0 /* AP[2:1], bits[7:6] */
#define MMU_STATE_MASK_CACHEABLE 0x0000031C /* SH[1:0], AttrIndex[2:0], */
/* bits[9:8] and bits[4:2] */
#define MMU_STATE_VALID 0x3 /* 0b11 means valid */
#define MMU_STATE_VALID_NOT 0x0 /* 0b00 means NOT valid */
#define MMU_STATE_MASK_PROTECTION 0x000000C0 /* AP[2:1], bits[7:6] */
#define MMU_STATE_SUP_RO 0x00000080 /* AP: 10 */
#define MMU_STATE_SUP_RW 0x00000000 /* AP: 00 */
#define MMU_STATE_SUP_RO_USR_RO 0x000000C0 /* AP: 11 */
#define MMU_STATE_SUP_RW_USR_RO 0x00000040 /* AP: 01, not support, */
/* here we set same as RW */
#define MMU_STATE_SUP_RW_USR_RW 0x00000040 /* AP: 01 */
/* XN not support */
#define MMU_STATE_SUP_RO_XN MMU_STATE_SUP_RO
#define MMU_STATE_SUP_RW_XN MMU_STATE_SUP_RW
#define MMU_STATE_SUP_RO_USR_RO_XN MMU_STATE_SUP_RO_USR_RO
#define MMU_STATE_SUP_RW_USR_RO_XN MMU_STATE_SUP_RW_USR_RO
#define MMU_STATE_SUP_RW_USR_RW_XN MMU_STATE_SUP_RW_USR_RW
#define MMU_STATE_WRITABLE MMU_STATE_SUP_RW
#define MMU_STATE_WRITABLE_NOT MMU_STATE_SUP_RO
#define MMU_STATE_AP_SUP_RO 0x2 /* AP field: 10 */
#define MMU_STATE_AP_SUP_RW 0x0 /* AP field: 00 */
#define MMU_STATE_AP_SUP_RO_USR_RO 0x3 /* AP field: 11 */
#define MMU_STATE_AP_SUP_RW_USR_RO 0x1 /* AP field: 01, arm not support */
#define MMU_STATE_AP_SUP_RW_USR_RW 0x1 /* AP field: 01 */
#define MMU_STATE_AP_USR_RO_SUP_RO MMU_STATE_AP_SUP_RO_USR_RO
#define MMU_STATE_AP_USR_RO_SUP_RW MMU_STATE_AP_SUP_RW_USR_RO
#define MMU_STATE_AP_USR_RW_SUP_RW MMU_STATE_AP_SUP_RW_USR_RW
/*
* Memory Region Attributes -
* cache access, write buffer access, coherency control
*/
/*
* Memory Region Attributes - for LPAE
*
* n = AttrIndex[2:0]
*
* n MAIR
* 000 00000000 Strongly-ordered
* 001 01000100 Normal memory, Inner & Outer Non-cacheable
* 010 10101010 Normal memory, Write-Through, Read-Allocate
* 011 11101110 Normal memory, Write-Back, Read-Allocate
* 100 00000100 Device memory
*/
#define MMU_MAIR0_VALUE 0xEEAA4400
#define MMU_MAIR1_VALUE 0x00000004
#define MMU_STATE_AI_STRONGLY_ORDERED 0x0 /* n = 0b000, strongly ordered */
#define MMU_STATE_STRONGLY_ORDERED ((MMU_STATE_AI_STRONGLY_ORDERED << 2) | \
MMU_STATE_SHARED_OUTER)
#define MMU_STATE_CACHEABLE_NOT MMU_STATE_STRONGLY_ORDERED
#define MMU_STATE_AI_DEVICE 0x4 /* n = 0b100 */
#define MMU_STATE_DEVICE_SHARED ((MMU_STATE_AI_DEVICE << 2) | \
MMU_STATE_SHARED_OUTER)
/* device always shared in LPAE */
#define MMU_STATE_DEVICE_NONSHARED MMU_STATE_DEVICE_SHARED
/* outer & inner write-thru cachable, write alloc */
#define MMU_STATE_AI_NORMAL_WRITETHROUGH 0x2 /* n = 0b010, Write-Through */
#define MMU_STATE_NORMAL_WRITETHROUGH (MMU_STATE_AI_NORMAL_WRITETHROUGH << 2)
#define MMU_STATE_CACHEABLE_WRITETHROUGH MMU_STATE_NORMAL_WRITETHROUGH
/* outer & inner write-back cachable, write alloc */
#define MMU_STATE_AI_NORMAL_WRITEBACK 0x3 /* n = 0b011, Write-Back */
#define MMU_STATE_NORMAL_WRITEBACK (MMU_STATE_AI_NORMAL_WRITEBACK << 2)
#define MMU_STATE_CACHEABLE_COPYBACK MMU_STATE_NORMAL_WRITEBACK
#define MMU_STATE_COPYBACK_ALLOC MMU_STATE_NORMAL_WRITEBACK
/* outer & inner Non-cachable */
#define MMU_STATE_AI_NORMAL_NONCACHEABLE 0x1 /* n = 0b001, Non-cacheable */
#define MMU_STATE_NORMAL_NONCACHEABLE (MMU_STATE_AI_NORMAL_NONCACHEABLE << 2)
/*
* Set the default state to be copyback.
*/
#define MMU_STATE_CACHEABLE MMU_STATE_CACHEABLE_COPYBACK
/*
* Shared memory attribute -
* accessible by multiple processors or bus masters and must be kept coherent
*/
#define MMU_STATE_SHARED_OUTER (0x2 << 8) /* Outer Shareable */
#define MMU_STATE_SHARED_INNER (0x3 << 8) /* Inner Shareable */
#define MMU_STATE_SHARED MMU_STATE_SHARED_INNER
#define MMU_STATE_WRITETHROUGH_SHARED \
(MMU_STATE_CACHEABLE_WRITETHROUGH | MMU_STATE_SHARED)
#define MMU_STATE_COPYBACK_SHARED \
(MMU_STATE_CACHEABLE_COPYBACK | MMU_STATE_SHARED)
/*
* A memory region with a resultant memory type attribute of Normal, and a
* resultant cacheability attribute of Inner Non-cacheable, Outer Non-cacheable,
* must have a resultant shareability attribute of Outer Shareable, otherwise
* shareability is UNPREDICTABLE.
*/
#define MMU_STATE_NONCACHEABLE_SHARED \
(MMU_STATE_NORMAL_NONCACHEABLE | \
MMU_STATE_SHARED_OUTER)
/*
* Global memory attribute -
* not-Global causes ASID to be associated with address translation
*/
#define MMU_STATE_NOT_GLOBAL 0x00000800 /* not-Global, bit[11] */
/*
* Architecture-specific attributes
*
* The following ARMv7-specific aliases are provided for ease of use.
*
* NOTE: MMU_ATTR_CACHE_GUARDED is used as MMU_ATTR_CACHE_IO (its former name).
*/
/* Strongly Ordered - same as MMU_ATTR_CACHE_OFF for backward compatibility */
#define MMU_ATTR_STRONGLY_ORDERED (MMU_ATTR_CACHE_OFF)
/* Shared Device */
#define MMU_ATTR_DEVICE_SHARED_MSK (MMU_ATTR_CACHE_MSK)
#define MMU_ATTR_DEVICE_SHARED (MMU_ATTR_CACHE_GUARDED | MMU_ATTR_CACHE_OFF | \
MMU_ATTR_CACHE_COHERENCY)
#define MMU_ATTR_BUFFERABLE MMU_ATTR_DEVICE_SHARED /* backward compatible */
/* Normal, Noncacheable memory */
#define MMU_ATTR_NORMAL_NONCACHEABLE_MSK (MMU_ATTR_CACHE_MSK)
#define MMU_ATTR_NORMAL_NONCACHEABLE (MMU_ATTR_CACHE_OFF)
#define MMU_ATTR_NORMAL_NONCACHEABLE_SHARED (MMU_ATTR_NORMAL_NONCACHEABLE | \
MMU_ATTR_CACHE_COHERENCY)
/* Normal, Inner Cache Write-Back, Write Allocate */
#define MMU_ATTR_WRITEALLOCATE_MSK MMU_ATTR_CACHE_MSK
#define MMU_ATTR_WRITEALLOCATE MMU_ATTR_CACHE_COPYBACK
#define MMU_ATTR_WRITEALLOCATE_SHARED (MMU_ATTR_WRITEALLOCATE | \
MMU_ATTR_CACHE_COHERENCY)
/* MMU Control Register bit allocations */
#define MMUCR_M_ENABLE (1<<0) /* MMU enable */
#define MMUCR_A_ENABLE (1<<1) /* Address alignment fault enable */
#define MMUCR_C_ENABLE (1<<2) /* (data) cache enable */
#define MMUCR_W_ENABLE (1<<3) /* write buffer enable */
#define MMUCR_PROG32 (1<<4) /* PROG32 */
#define MMUCR_DATA32 (1<<5) /* DATA32 */
#define MMUCR_L_ENABLE (1<<6) /* Late abort on earlier CPUs */
#define MMUCR_BIGEND (1<<7) /* Big-endian (=1), little-endian (=0) */
#define MMUCR_SYSTEM (1<<8) /* System bit, modifies MMU protections */
#define MMUCR_ROM (1<<9) /* ROM bit, modifies MMU protections */
#define MMUCR_F (1<<10) /* Should Be Zero */
#define MMUCR_Z_ENABLE (1<<11) /* Branch prediction enable on 810 */
#define MMUCR_I_ENABLE (1<<12) /* Instruction cache enable */
#define MMUCR_V_ENABLE (1<<13) /* Exception vectors remap to 0xFFFF0000 */
#define MMUCR_ALTVECT MMUCR_V_ENABLE /* alternate vector select */
#define MMUCR_RR_ENABLE (1<<14) /* Round robin cache replacement enable */
#define MMUCR_ROUND_ROBIN MMUCR_RR_ENABLE /* round-robin placement */
#define MMUCR_DISABLE_TBIT (1<<15) /* disable TBIT */
#define MMUCR_ENABLE_DTCM (1<<16) /* Enable Data TCM */
#define MMUCR_HA_ENABLE (1<<17) /* Hardware Access flag enable */
#define MMUCR_ENABLE_ITCM (1<<18) /* Enable Instruction TCM */
#define MMUCR_UNALIGNED_ENABLE (1<<22) /* Enable unaligned access */
#define MMUCR_EXTENDED_PAGE (1<<23) /* Use extended PTE format */
#define MMUCR_VECTORED_INTERRUPT (1<<24) /* Enable VIC Interface */
#define MMUCR_EE (1<<25) /* Exception Endianness bit */
#define MMUCR_THUMB_EXCEPTIONS (1<<30) /* Exceptions are Thumb */
/* MMU TTBR 64 bit register fields for LPAE */
#define MMU_TTBR64_BA_MASK MAKE_MASK_64(39, 12)
#define MMU_TTBR64_ASID_SHIFT 48
/* MMU TTBCR register fields for LPAE */
#define MMU_TTBCR_IRGN_NC (0 << 8)
#define MMU_TTBCR_IRGN_WBWA (1 << 8)
#define MMU_TTBCR_IRGN_WT (2 << 8)
#define MMU_TTBCR_IRGN_WB (3 << 8)
#define MMU_TTBCR_ORGN_NC (0 << 10)
#define MMU_TTBCR_ORGN_OC_WBWA (1 << 10)
#define MMU_TTBCR_ORGN_OC_WT (2 << 10)
#define MMU_TTBCR_ORGN_OC_WB (3 << 10)
#define MMU_TTBCR_S (3 << 12)
#define MMU_TTBCR_S_OUTER (2 << 12)
#define MMU_TTBCR_EAE (1 << 31)
#ifdef _WRS_CONFIG_ENABLE_CACHED_PAGE_TBL
/* PTWs cacheable, inner WBWA not shareable, outer WBWA not shareable */
#define MMU_TTBCR_FLAGS_UP (MMU_TTBCR_IRGN_WBWA | MMU_TTBCR_ORGN_OC_WBWA)
/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
#define MMU_TTBCR_FLAGS_SMP (MMU_TTBCR_IRGN_WBWA | MMU_TTBCR_S | \
MMU_TTBCR_ORGN_OC_WBWA)
#else /* !_WRS_CONFIG_ENABLE_CACHED_PAGE_TBL */
/* PTWs not cacheable, inner not shareable, outer not shareable */
#define MMU_TTBCR_FLAGS_UP (MMU_TTBCR_IRGN_NC | MMU_TTBCR_ORGN_NC)
/* PTWs not cacheable, inner shareable, outer not shareable */
#define MMU_TTBCR_FLAGS_SMP (MMU_TTBCR_ORGN_NC | MMU_TTBCR_S | \
MMU_TTBCR_ORGN_NC)
#endif /* _WRS_CONFIG_ENABLE_CACHED_PAGE_TBL */
/* typedefs */
#ifndef _ASMLANGUAGE
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
/* little-endian */
/* Level 1/2 page descriptors */
typedef struct
{
UINT type : 2; /* descriptor type, 0b11 => page table */
UINT pad1 : 10; /* Ignored */
UINT addr : 20; /* base address of page table */
UINT addr40 : 8; /* base address of page table */
UINT pad2 : 12; /* UNK/SBZP */
UINT pad3 : 7; /* Ignored */
UINT pxn : 1; /* PXNTable */
UINT xn : 1; /* XNTable */
UINT ap : 2; /* APTable */
UINT ns : 1; /* NSTable */
} PAGE_DESC_FIELD;
/* Layout of Page Table Entries (PTEs) */
typedef struct
{
UINT type : 2; /* page type, 0b11 => page */
UINT ai : 3; /* AttrIndx[2:0] */
UINT ns : 1; /* non-secure bit */
UINT ap : 2; /* AP[2:1], access permission */
UINT sh : 2; /* SH[1:0], shareability field */
UINT af : 1; /* access flag */
UINT ng : 1; /* not global bit */
UINT addr : 20; /* phys address */
UINT addr40 : 8; /* phys address */
UINT pad1 : 12; /* UNK/SBZP */
UINT ch : 1; /* contiguous hint */
UINT pxn : 1; /* privileged execute-never bit */
UINT xn : 1; /* execute-never bit */
UINT pad2 : 9; /* ignored */
} PTE_FIELD;
#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
/* big-endian */
#error "LPAE for big-endian not support yet."
#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
/* First/second level descriptor access */
typedef union
{
PAGE_DESC_FIELD fields;
UINT bits[2];
UINT64 bits64;
} MMU_LEVEL_1_DESC, MMU_LEVEL_2_DESC;
/* Third level descriptor access */
typedef union
{
PTE_FIELD fields;
UINT bits[2];
UINT64 bits64;
} PTE;
/*
* Structure for MMU translation table access - normally used to get a pointer
* to the first-level translation table.
*/
typedef struct mmuTransTblStruct
{
MMU_LEVEL_1_DESC *pLevel1Table; /* active MMU table */
VX_MUTEX_SEMAPHORE(mmuTransTblSem); /* MMU tables' semaphore */
UINT32 lockCnt; /* lock count */
atomic_t lockOwner; /* lock owner */
UINT8 asid; /* ASID/context id */
} MMU_TRANS_TBL;
/* function declarations */
/* Externally visible mmuLib, mmuMapLib and mmuALib2 routines */
IMPORT UINT32 mmuReadId (void);
IMPORT PHYS_ADDR mmuVirtToPhys (VIRT_ADDR addr);
IMPORT VIRT_ADDR mmuPhysToVirt (PHYS_ADDR addr);
IMPORT UINT32 (* mmuCrGet) (void);
IMPORT void (* mmuModifyCr) (UINT32 value, UINT32 mask);
IMPORT UINT32 mmuHardCrGet (void);
IMPORT void mmuModifyHardCr (UINT32 value, UINT32 mask);
IMPORT UINT32 (* _func_mmuFaultAddrGet) (void);
IMPORT UINT32 (* _func_mmuFaultStatusGet) (void);
IMPORT UINT32 (* _func_mmuIFaultStatusGet) (void);
IMPORT UINT32 mmuIFsrGet (void);
IMPORT UINT32 mmuFarGet (void);
IMPORT UINT32 mmuFsrGet (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuArmLpaeLibh */
vxworks-6.9/target/h/arch/arm/mmuArmManzanoLib.h
+78
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@@ -0,0 +1,78 @@
/* mmuArmManzano.h - Manzano (XScale varient) MMU library header file */
/* Copyright (c) 1998-2006 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement. No license to Wind River intellectual property rights
* is granted herein. All rights not licensed by Wind River are reserved
* by Wind River.
*/
/*
modification history
--------------------
012,22feb06,m_h Manzano Support
011,25jan06,m_h created.
*/
#ifndef __INCmmuArmManzanoLibh
#define __INCmmuArmManzanoLibh
/* Enable support for supersection descriptors */
#undef INCLUDE_MMU_SUPERSECTION_SUPPORT
#define INCLUDE_MMU_SUPERSECTION_SUPPORT
#ifdef INCLUDE_MMU_SUPERSECTION_SUPPORT
/* Supersections require "section" functionality */
#undef INCLUDE_MMU_SECTION_SUPPORT
#define INCLUDE_MMU_SECTION_SUPPORT
#endif /* INCLUDE_MMU_SUPERSECTION_SUPPORT */
#undef INCLUDE_MMU_SBIT_SUPPORT
#define INCLUDE_MMU_SBIT_SUPPORT
#include "arch/arm/mmuArmXSCALELib.h"
#ifndef _ASMLANGUAGE
#if defined(__STDC__) || defined(__cplusplus)
IMPORT void mmuMANZANOLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
IMPORT void mmuMANZANOTtbrSet (MMU_LEVEL_1_DESC *);
IMPORT MMU_LEVEL_1_DESC * mmuMANZANOTtbrGet ( void);
IMPORT void mmuMANZANODacrSet (UINT32 dacrVal);
IMPORT void mmuMANZANOTLBIDFlushEntry (void *addr);
IMPORT void mmuMANZANOTLBIDFlushAll (void);
IMPORT void mmuMANZANOAEnable (UINT32 cacheState);
IMPORT void mmuMANZANOADisable (void);
IMPORT STATUS mmuMANZANOPBitSet ( void * virtAddr, UINT32 size);
IMPORT STATUS mmuMANZANOPBitClear ( void * virtAddr, UINT32 size);
IMPORT STATUS mmuMANZANOPBitGet ( void * virtAddr );
IMPORT STATUS mmuMANZANOAcrGet (void );
IMPORT void mmuMANZANOAcrSet (UINT32 acrVal);
#else /* __STDC__ */
IMPORT void mmuMANZANOLibInstall ();
IMPORT void mmuMANZANOTtbrSet ();
IMPORT MMU_LEVEL_1_DESC * mmuMANZANOTtbrGet ();
IMPORT void mmuMANZANODacrSet ();
IMPORT void mmuMANZANOTLBIDFlushEntry ();
IMPORT void mmuMANZANOTLBIDFlushAll ();
IMPORT void mmuMANZANOAEnable ();
IMPORT void mmuMANZANOADisable ();
IMPORT STATUS mmuMANZANOPBitSet ();
IMPORT STATUS mmuMANZANOPBitClear ();
IMPORT STATUS mmuMANZANOPBitGet ();
IMPORT STATUS mmuMANZANOAcrGet ();
IMPORT void mmuMANZANOAcrSet ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#endif /* __INCmmuArmManzanoLibh */
vxworks-6.9/target/h/arch/arm/mmuArmPalLib.h
+611
View File
@@ -0,0 +1,611 @@
/* mmuArmPalLib.h - ARM MMU library header file */
/*
* Copyright (c) 1996-2007, 2009-2010, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
02i,02mar12,rec WIND00318272 - POSIX signals conformance
02h,09jan12,rec WIND00196578 - remove unused reference _func_armPageSource
02g,29apr10,pad Moved extern C statement after include statements.
02f,03nov09,j_b add INCLUDE_MMU_SUBPAGE_SUPPORT, undef INCLUDE_MMU_TEX_SUPPORT
02e,23oct07,to added lockCnt and lockOwner to MMU_TRANS_TBL
02d,21sep07,to define MMU_PAGE_SIZE_SHIFT
02c,21sep07,j_b add _func_mmuFaultAddrGet prototype
02b,09feb07,j_b add mmuFarGet prototype
02a,20sep06,j_b add page optimization support
01z,12sep06,m_h fix vert-to-phys translation problem in upper bits
WIND00059266
01y,28mar06,m_h Coherancy Support (s-bit)
01x,01mar06,m_h Section Support in non-XScale ARM
01w,03jan06,m_h Manzano Support
01v,24jun05,scm correct PAGE_DESC_FIELD for missing BE pad3 field, (SPR 110348)
01u,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01t,31jan05,jb Adding OTHER_SECT_DESC to resolve bsp reference
01s,09dec04,jb Palifying mmu, extracted from mmuArmLib.h, 01r
*/
/*
History from mmuArmLib.h
01r,10aug04,scm adjust for removal of MPU support, add 926E...
01q,18sep03,scm BASE 6 port...
01p,04oct01,scm add extended small page table support for XScale...
01o,23jul01,scm change XScale name to conform to coding standards...
01n,11jul01,scm add support for XScale...
01m,29mar01,jpd removed externs for mmyPhysToVirt & mmuVirtToPhys (SPR #63512).
01l,19mar01,jpd redefine MMU_ATTR_BUFFERABLE and MMU_ATTR_CACHE_MINICACHE
(SPR #64788).
01k,16aug00,jpd no longer clear MMUCR Reserved/Should Be Zero bits (SPR #33608)
01j,14jun00,jpd reworked MMU_STATE_WRITETHROUGH definition.
01i,17feb00,jpd T3: prefixed defs with MMU_; added new defs; changed SR to 10.
01h,07sep99,jpd added ARM740T, ARM920T support.
01g,20jan99,cdp removed support for old ARM libraries;
add prefix to MMU_IDs.
01f,24nov98,jpd added ARM940T support, added other CPU ids; removed
mmuIntLock/Unlock as intIFLock/Unlock to be used instead;
cdp restructured for multiple cache/MMU libraries; big-endian.
01e,09mar98,jpd added MMUCTR_ definitions for ARM810 and extra cache states.
01d,20jan98,jpd added _func_armPhysToVirt() etc. function pointers.
01c,17sep97,jpd added MMU_INIT_VALUE and mmuIntLock/Unlock definitions.
01b,24jan97,jpd modified mmuAEnable definition.
01a,09may96,cdp created.
*/
#ifndef __INCmmuArmPalLibh
#define __INCmmuArmPalLibh
#ifndef _ASMLANGUAGE
#include <memLib.h>
#include <semLib.h>
#ifdef __cplusplus
extern "C" {
#endif
#endif /* _ASMLANGUAGE */
/*
* MMUs are not fitted to all processors, and so the definitions below
* should not need to be included for processors without MMUs.
*/
#if (ARMMMU != ARMMMU_NONE)
/*
* The page size we will use. Ignore the sub-page, Large Page and Tiny
* Page features.
*/
#define MMU_PAGE_SIZE 4096
#define MMU_PAGE_SIZE_SHIFT 12
#undef INCLUDE_MMU_SUBPAGE_SUPPORT
#define INCLUDE_MMU_SUBPAGE_SUPPORT
#undef INCLUDE_MMU_TEX_SUPPORT
/*
* The amount described by a Level 1 Descriptor, which equals the smallest
* amount of VM allocatable in VxWorks.
*/
#define MMU_PAGE_BLOCK_SIZE 0x100000 /* 1 MByte */
#define MMU_ADRS_TO_L1D_INDEX_SHIFT 20
#define MMU_PTE_INDEX_MASK 0x000FF000 /* extract PTE index from Virt Addr */
#define MMU_PTE_INDEX_SHIFT 12 /* shift to make that into PTE index */
#define MMU_L1D_TO_BASE_SHIFT 10 /* to turn L1D to PT base addr */
#define MMU_L1DSECTION_TO_BASE_SHIFT 20 /* L1D section to PT base addr */
#define MMU_L1DSECTION_BA_MASK 0xFFF00000 /* phys bits 20-31 */
#define MMU_L1DSSECTIONLO_TO_BASE_SHIFT 24 /* bits 24-31 of supersection */
#define MMU_L1DSSECTIONHI_TO_BASE_SHIFT 32 /* bits 32-35 of supersection */
#define MMU_L1DSSECTIONLO_BA_MASK 0xFF000000 /* phys bits 24-31 */
#define MMU_L1DSSECTIONHI_BA_MASK 0x00F00000 /* phys bits 32-35 */
#define MMU_ADDR_PI_MASK 0x00000FFF /* extract page index from Virt Addr */
#define MMU_PTE_BA_MASK 0xFFFFF000 /* extract phys base address from PTE */
#define MMU_ADDR_SI_MASK 0x000FFFFF /* extr section index from Virt Addr */
#define MMU_PTE_SECA_MASK 0xFFF00000 /* extract section base from L1 desc */
#define MMU_ADDR_SSI_MASK 0x00FFFFFF /* supersection index from virt */
#define MMU_PTE_SSECA_MASK 0xFF000000 /* supersection base from L1 desc */
#define MMU_PTE_SSECAX_MASK 0x00F00000 /* supersection extended bits L1 */
#define MMU_PTE_SSECAX_SHIFT 12 /* supersection extended bits L1 */
#define MMU_PTE_TYPE_MASK 0x00000003 /* bits [0:1] */
#define MMU_L1PD_PTE_MASK 0xFFFFFC00 /* extract phys PTE addr from L1PD */
#define MMU_L1PD_TYPE_MASK 0x00000003 /* type bits [0:1] */
#define MMU_L1PD_CB_MASK 0x0000000C /* CB bits [3:2] */
#define MMU_L1PD_AP_MASK 0x00000C00 /* AP bits [10:11] */
#define MMU_L1PD_P_MASK 0x00000200 /* P bit [9] */
#define MMU_L1PD_TEX_MASK 0x00007000 /* TEX bits [14:12] */
#define MMU_L1PD_S_MASK 0x00010000 /* S bit (coherancy) [16] */
#define MMU_PTE_SECT_CB_MASK 0x0000000C /* CB bits [3:2] */
#define MMU_PTE_SECT_AP_MASK 0x00000030 /* AP bits [5:4] */
#define MMU_PTE_SECT_TEX_MASK 0x000001C0 /* TEX bits [8:6] */
#define MMU_PTE_SECT_S_MASK 0x00000200 /* S-bit (coherancy) [9] */
#define MMU_L1L2_SECT_CB_SHIFT 0 /* CB shift convert L1 to L2 */
#define MMU_L1L2_SECT_AP_SHIFT 6 /* AP shift convert L1 to L2 */
#define MMU_L1L2_SECT_TEX_SHIFT 6 /* TEX shift convert L1 to L2 */
#define MMU_L1L2_SECT_S_SHIFT 7 /* S-bit shift convert L1 to L2 */
#define MMU_PTE_SSECT_TYPE 0x00040000 /* supersection bit [18] */
#define MMU_PTE_SECT_TYPE_MASK 0x00040000 /* which type of section? */
#define MMU_NUM_VM_PAGES_IN_A_SECT 0x100
#define MMU_NUM_VM_PAGES_IN_A_SSECT 0x1000
#define MMU_NUM_SECTS_IN_A_SSECT 0x10 /* 16 sections/supersection */
#define MMU_SECT_SIZE 0x100000 /* section = 1MB */
#define MMU_SSECT_SIZE 0x1000000 /* supersection = 16MB */
#define MMU_L1PD_AP_SHIFT 10
#define MMU_L1PD_CB_SHIFT 2
#define MMU_L1PD_P_SHIFT 9
#define MMU_L1PD_S_SHIFT 16
#define MMU_L1PD_DOMAIN_MASK 0x000001E0 /* domain bits 5-8 */
#define MMU_L1PD_DOMAIN_SHIFT 5 /* shift to make domain field in L1PD */
/*
* The Domain Access Control Register specifies the way in which access
* rights are treated for each of sixteen domains. For each domain the
* current state can be:
*
* 00 no access: all accesses generate aborts
* 01 client: access rights specified in page tables are checked.
* 10 reserved
* 11 manager: accesses not checked against page tables: all access allowed.
*/
#define MMU_DACR_VAL_NORMAL 1 /* client of 0 */
#define MMU_DACR_VAL_UNPROTECT 0x03 /* manager of 0 */
/* Level 1 Descriptor types */
#define MMU_DESC_TYPE_FAULT 0 /* any access will cause a fault */
#define MMU_DESC_TYPE_PAGE 1
#define MMU_DESC_TYPE_SECTION 2
#define MMU_DEF_L1_PAGE 0x00000011 /* domain zero, Page descriptor */
/*
* Section descriptors, such as might be used to set up an intermediate
* set of page tables on processors such as SA-1100/SA-1500 where this
* needs to be done from BSP initialization, before vm(Base)Lib sets up
* a proper set of page tables.
*/
#define MMU_RAM_SECT_DESC 0xC1E /* R/W cacheable bufferable domain 0 */
#define MMU_MINICACHE_SECT_DESC 0xC1A /* R/W C+ B- domain 0 */
#define MMU_OTHER_SECT_DESC 0xC12 /* R/W C- B- domain 0 */
/* Level 2 Descriptor or Page Table Entry (PTE) types */
#define MMU_PTE_TYPE_FAULT 0 /* any access will cause a fault */
#define MMU_PTE_TYPE_LG_PAGE 1 /* Large page descriptor */
#define MMU_PTE_TYPE_SM_PAGE 2 /* Small page descriptor */
#define MMU_PTE_TYPE_EX_PAGE 3 /* Extended page descriptor */
/*
* The Translation Table Base register (TTBR) points to a table of Level 1
* Descriptors. these are either Invalid Section descriptors, Section
* Descriptors, or Page Table Descriptors. If Page Table Descriptors, they
* each point to a table of Level 2 Page Descriptors, or Page Table Entries
* (PTEs).
* The 32-bit (virtual) address space allows for 4096 M. Each Level 1
* Descriptor describes a 1 M area of memory. There are therefore 4096 Level
* 1 Descriptors, and each table of 256 Level 2 Page Descriptors (PTEs)
* describes 256 4 kbyte pages.
*/
#define MMU_NUM_L1_DESCS 4096
#define MMU_NUM_L2_DESCS 256
#define MMU_L1_TABLE_SIZE (MMU_NUM_L1_DESCS * sizeof(MMU_LEVEL_1_DESC))
/* No. of pages a Level 1 Descriptor table takes up */
#define MMU_L1_DESC_PAGES (MMU_L1_TABLE_SIZE / MMU_PAGE_SIZE)
/* Size of a Page Table */
#define MMU_PAGE_TABLE_SIZE (MMU_NUM_L2_DESCS * sizeof(PTE))
/* Section and supersection L1 definitions follow */
#undef MMU_DEF_L1_SECTION_PAGE
#define MMU_DEF_L1_SECTION_PAGE 0x00000002 /* Section page descriptor */
#undef MMU_DEF_L1_SUPERSECTION_PAGE
#define MMU_DEF_L1_SUPERSECTION_PAGE 0x00040002 /* supersection */
#undef MMU_DEF_L1_SECTION_PAGE_MASK
#define MMU_DEF_L1_SECTION_PAGE_MASK 0x00040003 /* mask */
#undef MMU_STATE_SECTION_MASK_WRITABLE
#define MMU_STATE_SECTION_MASK_WRITABLE 0x00000030 /* All APn bits */
/*
* Architecture-dependent MMU states. These are states settable for pages and
* here they correspond to settings in the Page Table Entries (PTEs).
*
* We set Valid/Invalid by setting a Fault second-level descriptor rather
* than by using the Access Permissions within a small page second-level
* descriptor. This is because we will want to use the Access Permissions to
* control supervisor mode access and we cannot then use the AP bits
* to disallow access as the SR bits in the MMU Control register must be set
* to 10 in order to control read/write access from Supervisor mode.
*/
#define MMU_STATE_INVALID_STATE 0xFFFFFFFF
#define MMU_STATE_MASK_VALID 0x03 /* 2nd level desc type */
#define MMU_STATE_MASK_WRITABLE 0x00000FF0 /* All APn bits */
#define MMU_STATE_MASK_CACHEABLE 0x0000000C /* CB bits */
#define MMU_STATE_MASK_BUFFERABLE 0x00000004
#define MMU_STATE_MASK_MEM_COHERENCY 0x00000200 /* Manzano S-bit */
#define MMU_STATE_MEM_COHERENCY 0x00000200 /* Manzano S-bit */
#ifdef INCLUDE_MMU_SBIT_SUPPORT
#define MMU_STATE_MASK_CACHEABLE_S 0x0000020C /* CB&S bits */
#else /*INCLUDE_MMU_SBIT_SUPPORT*/
#define MMU_STATE_MASK_CACHEABLE_S 0x0000000C /* CB bits */
#endif /*INCLUDE_MMU_SBIT_SUPPORT*/
#define MMU_STATE_VALID MMU_PTE_TYPE_SM_PAGE /* set to page type */
#define MMU_STATE_VALID_NOT MMU_PTE_TYPE_FAULT /* set to type fault */
#define MMU_STATE_WRITABLE 0x00000FF0 /* APn bits to 11 */
#define MMU_STATE_WRITABLE_NOT 0x0 /* APn bits to 00 */
#define MMU_STATE_MASK_PROTECTION 0x00000FF0 /* APn bits */
#define MMU_STATE_SUP_RO 0x00000000 /* AP: 00 */
#define MMU_STATE_SUP_RW 0x00000550 /* AP: 01 */
#define MMU_STATE_USR_RO_SUP_RW 0x00000AA0 /* AP: 10 */
#define MMU_STATE_USR_RW_SUP_RW 0x00000FF0 /* AP: 11 */
#define MMU_STATE_AP_SUP_RO 0x0 /* AP field: 00 */
#define MMU_STATE_AP_SUP_RW 0x1 /* AP field: 01 */
#define MMU_STATE_AP_USR_RO_SUP_RW 0x2 /* AP field: 10 */
#define MMU_STATE_AP_USR_RW_SUP_RW 0x3 /* AP field: 11 */
/* Write-through mode is only available on some CPUs */
#define MMU_STATE_CACHEABLE_WRITETHROUGH 0x8
#define MMU_STATE_CACHEABLE_COPYBACK 0xC /* write back */
/*
* Set the default state to be copyback. CACHEABLE_WRITETHROUGH can also be
* selected on those cache designs that permit it.
*/
#define MMU_STATE_CACHEABLE MMU_STATE_CACHEABLE_COPYBACK
#define MMU_STATE_CACHEABLE_NOT 0x0
#define MMU_STATE_BUFFERABLE 0x4 /* bufferable, not cacheable */
#define MMU_STATE_BUFFERABLE_NOT 0x0 /* will also set not cacheable*/
/*
* Under VxWorks AE 1.1, when setting either of the attributes SPL_0 or SPL_1,
* using vmPgAttrSet(), it is necessary to:
*
* 1. specify MMU_ATTR_SPL_MSK ORred with MMU_ATTR_CACHE_MSK in the mask
* argument to the routine, and:
* 2. specify the appropriate cache state ORred in to the state argument
* to the routine.
*
* So, to set a page as bufferable not cacheable, it is necessary to
* specify both MMU_ATTR_SPL_0 and specify MMU_ATTR_CACHE_OFF in the
* state argument. To mark a page as cacheable in the minicache,
* MMU_ATTR_SPL_1 and MMU_ATTR_CACHE_COPYBACK must be specified in the
* state argument. In both cases, specify MMU_ATTR_SPL_MSK ORred with
* MMU_ATTR_CACHE_MSK in the mask argument.
*
* These restrictions were not present in VxWorks AE 1.0.
*
* To "unset" the special attibutes SPL_0 or SPL_1, specify
* MMU_ATTR_CACHE_MSK in the mask parameter (without MMU_ATTR_SPL_MSK),
* and specify the cacheability required in the state argument.
*
* We provide the following aliases on ARM, to make life easier.
*/
#define MMU_ATTR_BUFFERABLE (MMU_ATTR_SPL_0)
/* MMU Control Register bit allocations */
#define MMUCR_M_ENABLE (1<<0) /* MMU enable */
#define MMUCR_A_ENABLE (1<<1) /* Address alignment fault enable */
#define MMUCR_C_ENABLE (1<<2) /* (data) cache enable */
#define MMUCR_W_ENABLE (1<<3) /* write buffer enable */
#define MMUCR_PROG32 (1<<4) /* PROG32 */
#define MMUCR_DATA32 (1<<5) /* DATA32 */
#define MMUCR_L_ENABLE (1<<6) /* Late abort on earlier CPUs */
#define MMUCR_BIGEND (1<<7) /* Big-endian (=1), little-endian (=0) */
#define MMUCR_SYSTEM (1<<8) /* System bit, modifies MMU protections */
#define MMUCR_ROM (1<<9) /* ROM bit, modifies MMU protections */
#define MMUCR_F (1<<10) /* Should Be Zero */
#define MMUCR_Z_ENABLE (1<<11) /* Branch prediction enable on 810 */
#define MMUCR_I_ENABLE (1<<12) /* Instruction cache enable */
#define MMUCR_V_ENABLE (1<<13) /* Exception vectors remap to 0xFFFF0000 */
#define MMUCR_ALTVECT MMUCR_V_ENABLE /* alternate vector select */
#define MMUCR_RR_ENABLE (1<<14) /* Round robin cache replacement enable */
#define MMUCR_ROUND_ROBIN MMUCR_RR_ENABLE /* round-robin placement */
#define MMUCR_DISABLE_TBIT (1<<15) /* disable TBIT */
/* The following definitions are now deprecated and may be withdrawn */
#ifdef MMU_ARM_ALLOW_DEPRECATED
#define LEVEL_1_DESC MMU_LEVEL_1_DESC
#define PAGE_SIZE MMU_PAGE_SIZE
#define PAGE_BLOCK_SIZE MMU_PAGE_BLOCK_SIZE
#define PTE_INDEX_MASK MMU_PTE_INDEX_MASK
#define PTE_INDEX_SHIFT MMU_PTE_INDEX_SHIFT
#define L1D_TO_BASE_SHIFT MMU_L1D_TO_BASE_SHIFT
#define ADDR_PI_MASK MMU_ADDR_PI_MASK
#define NUM_L1_DESCS MMU_NUM_L1_DESCS
#define NUM_L2_DESCS MMU_NUM_L2_DESCS
#define L1_TABLE_SIZE MMU_L1_TABLE_SIZE
#define L1_DESC_PAGES MMU_L1_DESC_PAGES
#define PAGE_TABLE_SIZE MMU_PAGE_TABLE_SIZE
#define DESC_TYPE_PAGE MMU_DESC_TYPE_PAGE
#define DEF_L1_PAGE MMU_DEF_L1_PAGE
#define PTE_TYPE_FAULT MMU_PTE_TYPE_FAULT
#define PTE_TYPE_SM_PAGE MMU_PTE_TYPE_SM_PAGE
#define RAM_SECT_DESC MMU_RAM_SECT_DESC
#define MINICACHE_SECT_DESC MMU_MINICACHE_SECT_DESC
#define OTHER_SECT_DESC MMU_OTHER_SECT_DESC
#else /* MMU_ARM_ALLOW_DEPRECATED */
/* Some BSPs still reference PAGE_SIZE */
#define PAGE_SIZE MMU_PAGE_SIZE
/* Some BSPs still reference OTHER_SECT_DESC */
#define OTHER_SECT_DESC MMU_OTHER_SECT_DESC
#endif /* MMU_ARM_ALLOW_DEPRECATED */
#define ADDR_TO_PAGE 12 /* shift phys address to PTE page base address */
#ifndef _ASMLANGUAGE
/* If using standard ARM MMU structures */
#ifndef MMU_ARCHITECTURE_DEFINES_STRUCTURES
/* Default ARMARCH4/5 ARM MMU Structures */
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
/* little-endian */
/* First level page descriptors */
typedef struct
{
UINT type : 2; /* descriptor type, 1 => page */
UINT pad1 : 2; /* SBZ */
UINT pad2 : 1; /* SBO */
UINT domain : 4; /* domain number */
UINT pad3 : 1; /* SBZ */
UINT addr : 22; /* base address of page table */
} PAGE_DESC_FIELD;
/* First level "section" descriptor */
typedef struct
{
UINT type : 2; /* descriptor type, 2 => section */
UINT bbit : 1; /* bufferable-bit */
UINT cbit : 1; /* cacheable-bit */
UINT pad1 : 1; /* SBO */
UINT domain : 4; /* domain number */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT ap : 2; /* AP */
UINT tex : 3; /* AP */
UINT pad2 : 1; /* SBO */
UINT sbit : 1; /* S-bit */
UINT pad3 : 1; /* SBO */
UINT super : 1; /* 1 => supersection */
UINT pad4 : 1; /* SBO */
UINT addr : 12; /* base address of page table */
} SECTION_DESC_FIELD;
/* First level "supersection" descriptor */
typedef struct
{
UINT type : 2; /* descriptor type, 2 => section */
UINT bbit : 1; /* bufferable-bit */
UINT cbit : 1; /* cacheable-bit */
UINT pad1 : 1; /* SBO */
UINT addrHi2: 4; /* phys address 39:36 */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT ap : 2; /* AP */
UINT tex : 3; /* TEX */
UINT pad2 : 1; /* SBO */
UINT sbit : 1; /* S-bit */
UINT pad3 : 1; /* SBO */
UINT super : 1; /* 1 => supersection */
UINT pad4 : 1; /* SBO */
UINT addrHi : 4; /* phys address 35:32 */
UINT addrLo : 8; /* phys address 31:24 */
} SUPERSECTION_DESC_FIELD;
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
typedef struct
{
UINT type : 2; /* page type, 2 => small page */
UINT cb : 2; /* cacheable/bufferable bits */
UINT ap0 : 2; /* access permission, sub-page 0 */
UINT ap1 : 2; /* access permission, sub-page 1 */
UINT ap2 : 2; /* access permission, sub-page 2 */
UINT ap3 : 2; /* access permission, sub-page 3 */
UINT addr : 20; /* page base address */
} PTE_FIELD;
#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
/* big-endian */
/* First level descriptors */
typedef struct
{
UINT addr : 22; /* descriptor type, 1 => page */
UINT pad3 : 1; /* SBZ */
UINT domain : 4; /* domain number */
UINT pad2 : 1; /* SBO */
UINT pad1 : 2; /* SBZ */
UINT type : 2; /* base address of page table */
} PAGE_DESC_FIELD;
/* First level "section" descriptor */
typedef struct
{
UINT addr : 12; /* base address of page table */
UINT pad4 : 1; /* SBO */
UINT super : 1; /* 1 => supersection */
UINT pad3 : 1; /* SBO */
UINT sbit : 1; /* S-bit */
UINT pad2 : 1; /* SBO */
UINT tex : 3; /* AP */
UINT ap : 2; /* AP */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT domain : 4; /* domain number */
UINT pad1 : 1; /* SBO */
UINT c : 1; /* c-bit */
UINT b : 1; /* b-bit */
UINT type : 2; /* descriptor type, 2 => section */
} SECTION_DESC_FIELD;
/* First level "supersection" descriptor */
typedef struct
{
UINT addrLo : 8; /* phys address 31:24 */
UINT addrHi : 4; /* phys address 35:32 */
UINT pad4 : 1; /* SBO */
UINT super : 1; /* 1 => supersection */
UINT pad3 : 1; /* SBO */
UINT sbit : 1; /* S-bit */
UINT pad2 : 1; /* SBO */
UINT tex : 3; /* AP */
UINT ap : 2; /* AP */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT addrHi2: 4; /* phys address 39:36 */
UINT pad1 : 1; /* SBO */
UINT c : 1; /* c-bit */
UINT b : 1; /* b-bit */
UINT type : 2; /* descriptor type, 2 => section */
} SUPERSECTION_DESC_FIELD;
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
typedef struct
{
UINT addr : 20; /* page base address */
UINT ap3 : 2; /* access permission, sub-page 3 */
UINT ap2 : 2; /* access permission, sub-page 2 */
UINT ap1 : 2; /* access permission, sub-page 1 */
UINT ap0 : 2; /* access permission, sub-page 0 */
UINT cb : 2; /* cacheable/bufferable bits */
UINT type : 2; /* page type, 2 => small page */
} PTE_FIELD;
#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
/* First level descriptor access */
typedef union
{
PAGE_DESC_FIELD fields;
SECTION_DESC_FIELD sectionFields;
SUPERSECTION_DESC_FIELD supersectionFields;
UINT32 bits;
} MMU_LEVEL_1_DESC;
/* Second level descriptor access */
typedef union
{
PTE_FIELD fields;
UINT32 bits;
} PTE;
/*
* Structure for MMU translation table access - normally used to get a pointer
* to the first-level translation table.
* To support page table optimization, a second first-level table and a
* semaphore are needed.
* The initial, unoptimized set of page tables will be set as the active
* translation tables (via pLevel1Table) while optimization or deoptimization
* is in progress using the inactive second translation table (pAltLevel1Table).
* After each page table optimization or deoptimization operation has
* completed, the second translation table will be set as the active
* translation table. The initial set of page tables retain their
* links to level 2 pages, which may otherwise be lost after optimization.
* Any non-optimization changes to the active first-level table will also be
* made to the inactive first-level table.
* The semaphore is used to prevent corruption of the tables.
*/
typedef struct mmuTransTblStruct
{
MMU_LEVEL_1_DESC *pLevel1Table; /* active MMU table */
MMU_LEVEL_1_DESC *pAltLevel1Table; /* inactive MMU table */
VX_MUTEX_SEMAPHORE(mmuTransTblSem); /* MMU tables' semaphore */
UINT32 lockCnt; /* lock count */
atomic_t lockOwner; /* lock owner */
} MMU_TRANS_TBL;
#endif /* MMU_ARCHITECTURE_DEFINES_STRUCTURES */
/* Externally visible mmuLib, mmuMapLib and mmuALib2 routines */
IMPORT UINT32 mmuReadId (void);
IMPORT PHYS_ADDR mmuVirtToPhys (VIRT_ADDR addr);
IMPORT VIRT_ADDR mmuPhysToVirt (PHYS_ADDR addr);
IMPORT UINT32 (* mmuCrGet) (void);
IMPORT void (* mmuModifyCr) (UINT32 value, UINT32 mask);
IMPORT UINT32 mmuHardCrGet (void);
IMPORT UINT32 mmuSoftCrGet (void);
IMPORT void mmuModifyHardCr (UINT32 value, UINT32 mask);
IMPORT void mmuModifySoftCr (UINT32 value, UINT32 mask);
IMPORT UINT32 (* _func_mmuFaultAddrGet) (void);
IMPORT UINT32 (* _func_mmuFaultStatusGet) (void);
IMPORT UINT32 mmuFarGet (void); /* CP15_FAR only available with MMUs */
IMPORT UINT32 mmuFsrGet (void); /* CP15_FSR only available with MMUs */
#endif /* _ASMLANGUAGE */
#endif /* (ARMMMU != ARMMMU_NONE) */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuArmPalLibh */
vxworks-6.9/target/h/arch/arm/mmuArmXSCALELib.h
+459
View File
@@ -0,0 +1,459 @@
/* mmuArmXSCALELib.h - XScale MMU library header file */
/*
* Copyright (c) 2000, 2001, 2003-2007, 2009-2010 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01l,29jul10,pad Moved extern C statement after include statements.
01k,03nov09,j_b add INCLUDE_MMU_TEX_SUPPORT, undef INCLUDE_MMU_SUBPAGE_SUPPORT
01j,23oct07,to added lockCnt and lockOwner to MMU_TRANS_TBL
01i,13sep06,j_b add page optimization support
01h,29mar06,m_h Coherancy (S-bit) support
01g,03jan06,m_h Manzano Support
01f,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01e,10feb05,jb Reverting to ROM mode for shared data/libraries
01d,09dec04,jb Palify Arm MMU
01c,08sep03,scm add P-bit support...
01b,23jul01,scm change XScale name to conform to coding standards...
01a,31aug00,scm created.
*/
#ifndef __INCmmuArmXSCALELibh
#define __INCmmuArmXSCALELibh
#include <memLib.h>
#include <semLib.h>
#define MMU_ID_XSCALE 0x052000
/* Enable support for section descriptors */
#undef INCLUDE_MMU_SECTION_SUPPORT
#define INCLUDE_MMU_SECTION_SUPPORT
/* Let the Pal code know Xscale has unique structures */
#define MMU_ARCHITECTURE_DEFINES_STRUCTURES
#include "mmuArmPalLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Xscale specific definitions follow */
#undef INCLUDE_MMU_SUBPAGE_SUPPORT
#undef INCLUDE_MMU_TEX_SUPPORT
#define INCLUDE_MMU_TEX_SUPPORT
#undef MMU_DEF_L1_PAGE
#define MMU_DEF_L1_PAGE 0x00000001 /* domain zero, Page descriptor */
#undef MMU_STATE_MASK_WRITABLE
#define MMU_STATE_MASK_WRITABLE 0x00000030 /* All APn bits */
#define MMU_STATE_X_BIT 0x00000040
#define MMU_STATE_S_BIT 0x00000200 /* S-bit coherancy */
#define MMU_STATE_MASK_EX_BUFFERABLE (MMU_STATE_X_BIT | MMU_STATE_MASK_BUFFERABLE)
#define MMU_STATE_MASK_EX_CACHEABLE (MMU_STATE_X_BIT | MMU_STATE_MASK_CACHEABLE)
#undef MMU_STATE_VALID
#define MMU_STATE_VALID MMU_PTE_TYPE_EX_PAGE /* set to page type */
#undef MMU_STATE_WRITABLE
#define MMU_STATE_WRITABLE 0x00000030 /* APn bits to 11 */
#undef MMU_STATE_MASK_PROTECTION
#define MMU_STATE_MASK_PROTECTION 0x00000030 /* APn bits */
#undef MMU_STATE_SUP_RO
#define MMU_STATE_SUP_RO 0x00000000 /* AP: 00 */
#undef MMU_STATE_SUP_RW
#define MMU_STATE_SUP_RW 0x00000010 /* AP: 01 */
#undef MMU_STATE_USR_RO_SUP_RW
#define MMU_STATE_USR_RO_SUP_RW 0x00000020 /* AP: 10 */
#undef MMU_STATE_USR_RW_SUP_RW
#define MMU_STATE_USR_RW_SUP_RW 0x00000030 /* AP: 11 */
/* only AP bits valid on extended small page tables are AP0 */
#ifdef INCLUDE_MMU_SBIT_SUPPORT
#define MMU_MSK_UNUSED_AP 0xfffff23f
#else /*INCLUDE_MMU_SBIT_SUPPORT*/
#define MMU_MSK_UNUSED_AP 0xfffff03f
#endif /*INCLUDE_MMU_SBIT_SUPPORT*/
#define MMU_MSK_CHK_APS 0x00000fc0
#define MMU_MSK_X_BIT 0x00000040
/* Section and supersection L1 definitions follow */
#undef MMU_DEF_L1_SECTION_PAGE
#define MMU_DEF_L1_SECTION_PAGE 0x00000002 /* Section page descriptor */
#undef MMU_DEF_L1_SUPERSECTION_PAGE
#define MMU_DEF_L1_SUPERSECTION_PAGE 0x00040002 /* supersection */
#undef MMU_DEF_L1_SECTION_PAGE_MASK
#define MMU_DEF_L1_SECTION_PAGE_MASK 0x00040003 /* mask */
#undef MMU_STATE_SECTION_MASK_WRITABLE
#define MMU_STATE_SECTION_MASK_WRITABLE 0x00000030 /* All APn bits */
/* optional extended physical address bit fields */
#define MMU_L1DSSECTION_EXTD_BA_MASK MMU_L1DSSECTIONHI_BA_MASK
/* Supersection base address packing */
#define MMU_L1DSSECTION_BA_SET(physAddr, ssectDesc) \
(ssectDesc = (ssectDesc & ~MMU_L1DSSECTION_EXTD_BA_MASK) | \
( (((unsigned long long)(physAddr)) & MMU_L1DSSECTIONLO_BA_MASK) | \
((((unsigned long long)(physAddr)) >> 12) & \
MMU_L1DSSECTIONHI_BA_MASK) ))
/* Supersection base address unpacking */
#define MMU_L1DSSECTION_BA_GET(ssectDesc) \
((unsigned long long) \
( (unsigned long long)(ssectDesc & MMU_L1DSSECTIONLO_BA_MASK) | \
((unsigned long long)(ssectDesc & MMU_L1DSSECTIONHI_BA_MASK) \
<< 12) ))
/* The X-bit is the LSB of TEX: bit-12 of the section or supersection L1 */
#define MMU_STATE_SECTION_X_BIT 0x00001000
#define MMU_STATE_MASK_SECTION_EX_BUFFERABLE \
(MMU_STATE_SECTION_X_BIT | MMU_STATE_MASK_BUFFERABLE)
#define MMU_STATE_MASK_SECTION_EX_CACHEABLE \
(MMU_STATE_SECTION_X_BIT | MMU_STATE_MASK_CACHEABLE)
#define MMU_SECTION_MSK_X_BIT 0x00001000
#define MMU_STATE_CACHEABLE_MINICACHE 0x48 /* allocate in minicache, X=1, CB=10 */
/* the mini data cache attributes to the Auxiliary Control Reg */
/* used by mmuSetMDBits... */
#define MD_COPYBACK 0x00000000
#define MD_WRITEALLOCATE 0x00000010
#define MD_WRITETHRU 0x00000020
#define MMU_STATE_CACHEABLE_EX_COPYBACK (MMU_STATE_X_BIT | MMU_STATE_CACHEABLE_COPYBACK)
#define MMU_STATE_EX_CACHEABLE MMU_STATE_CACHEABLE_EX_COPYBACK
#define MMU_STATE_EX_CACHEABLE_NOT 0x0
/* bufferable, not cacheable, no coalesce */
#define MMU_STATE_EX_BUFFERABLE (MMU_STATE_X_BIT | MMU_STATE_BUFFERABLE)
#define MMU_STATE_EX_BUFFERABLE_NOT 0x0 /* will also set not cacheable, no coalesce */
#define MMU_ATTR_CACHE_MINICACHE (MMU_ATTR_SPL_1 | MMU_ATTR_CACHE_COPYBACK)
/*
* two new states with extended small page tables, bufferable no coalesce, and
* write back with read/write allocate...
*/
#define MMU_ATTR_NO_COALESCE (MMU_ATTR_SPL_2 | MMU_ATTR_CACHE_OFF) /* Cache -- no coalesce into buffers */
#define MMU_ATTR_WRITEALLOCATE (MMU_ATTR_SPL_3 | MMU_ATTR_CACHE_COPYBACK) /* Cache -- write allocate */
/* cache states determined by MD-bits of Auxilliary Control Register */
#define MMU_ATTR_CACHE_MINICACHE_CB (MMU_ATTR_SPL_1 | MMU_ATTR_CACHE_COPYBACK)
#define MMU_ATTR_CACHE_MINICACHE_WA (MMU_ATTR_SPL_1 | MMU_ATTR_WRITEALLOCATE)
#define MMU_ATTR_CACHE_MINICACHE_WT (MMU_ATTR_SPL_1 | MMU_ATTR_CACHE_WRITETHRU)
/* Write-through mode is only available on some CPUs */
#define MMU_STATE_CACHEABLE_WRITETHROUGH 0x8
/*
* Values to be used when mmuEnable() is called. This will be after the MMU has
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
* cache enable settings have been chosen.
*
* M 1 Enable MMU
* A 0 Disable address alignment fault
* C X ((D-)Cache Enable) Controlled by cacheLib
* W X (Write Buffer) Controlled by cacheLib
* P 1 (PROG32) should be set before this
* D 1 (DATA32) should be set before this
* L 1 (Late abort on earlier CPUs) ignore
* B X (Big/Little-endian) should be set before this
* S 1 (System)
* R 0 (ROM)
* F 0 Should be Zero
* Z X (Branch prediction enable on 810) Controlled by cacheLib
* I X (I-cache enable) Controlled by cacheLib
*
* For time being, do not enable the address alignment fault, as GCC
* currently generates unaligned accesses in its code, and switching this
* on will cause immediate faults. So, do not put it into the enable
* mask.
*
* We used to clear all the Reserved/Should Be Zero bits when the
* MMU/MPU was enabled, by including one bits for them in the definition
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
* the definitions of the bits within the MMU Control Register. The MMU
* Control register is initialised within romInit()/sysInit(), as the BSP
* is the only place where the particular details of the CPU/MMU are
* actually known. In general, it will be appropriate for the BSP to
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
* MMU is enabled, we will only change the bits we are particularly
* concerned about, by using a Read-Modify-Write strategy.
*/
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
#define MMUCR_MODE MMUCR_ROM /* This MUST remain as ROM for shared libraries */
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE)
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_MODE)
#else
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_BIGEND | MMUCR_MODE)
#endif
#ifndef _ASMLANGUAGE
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
/* little-endian */
/* First level page descriptors */
typedef struct
{
UINT type : 2; /* descriptor type, 1 => page */
UINT pad1 : 2; /* SBZ */
UINT pad2 : 1; /* SBO */
UINT domain : 4; /* domain number */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT addr : 22; /* base address of page table */
} PAGE_DESC_FIELD;
/* First level "section" descriptor */
typedef struct
{
UINT type : 2; /* descriptor type, 2 => section */
UINT bbit : 1; /* bufferable-bit */
UINT cbit : 1; /* cacheable-bit */
UINT pad1 : 1; /* SBO */
UINT domain : 4; /* domain number */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT ap : 2; /* AP */
UINT tex : 3; /* TEX */
UINT pad2 : 1; /* SBO */
UINT sbit : 1; /* S-bit */
UINT pad3 : 1; /* SBO */
UINT super : 1; /* 1 => supersection */
UINT pad4 : 1; /* SBO */
UINT addr : 12; /* base address of page table */
} SECTION_DESC_FIELD;
/* First level "supersection" descriptor */
typedef struct
{
UINT type : 2; /* descriptor type, 2 => section */
UINT bbit : 1; /* bufferable-bit */
UINT cbit : 1; /* cacheable-bit */
UINT pad1 : 1; /* SBO */
UINT addrHi2: 4; /* SBZ [phys address 39:36] */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT ap : 2; /* AP */
UINT tex : 3; /* TEX */
UINT pad2 : 1; /* SBO */
UINT sbit : 1; /* S-bit */
UINT pad3 : 1; /* SBO */
UINT super : 1; /* 1 => supersection */
UINT pad4 : 1; /* SBO */
UINT addrHi : 4; /* phys address 35:32 */
UINT addrLo : 8; /* phys address 31:24 */
} SUPERSECTION_DESC_FIELD;
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
typedef struct
{
UINT type : 2; /* page type, 3 => extended small page */
UINT cb : 2; /* cacheable/bufferable bits */
UINT ap : 2; /* access permission */
UINT tex : 4; /* type extension field */
UINT sbz : 2; /* should be zero */
UINT addr : 20; /* page base address */
} PTE_FIELD;
#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
/* big-endian */
/* First level page descriptors */
typedef struct
{
UINT addr : 22; /* base address of page table */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT domain : 4; /* domain number */
UINT pad2 : 1; /* SBO */
UINT pad1 : 2; /* SBZ */
UINT type : 2; /* descriptor type, 1 => page */
} PAGE_DESC_FIELD;
/* First level "section" descriptor */
typedef struct
{
UINT addr : 12; /* base address of page table */
UINT pad4 : 1; /* SBO */
UINT super : 1; /* 1 => supersection */
UINT pad3 : 1; /* SBO */
UINT sbit : 1; /* S-bit */
UINT pad2 : 1; /* SBO */
UINT tex : 3; /* AP */
UINT ap : 2; /* AP */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT domain : 4; /* domain number */
UINT pad1 : 1; /* SBO */
UINT c : 1; /* c-bit */
UINT b : 1; /* b-bit */
UINT type : 2; /* descriptor type, 2 => section */
} SECTION_DESC_FIELD;
/* First level "supersection" descriptor */
typedef struct
{
UINT addrLo : 8; /* phys address 31:24 */
UINT addrHi : 4; /* phys address 35:32 */
UINT pad4 : 1; /* SBO */
UINT super : 1; /* 1 => supersection */
UINT pad3 : 1; /* SBO */
UINT sbit : 1; /* S-bit */
UINT pad2 : 1; /* SBO */
UINT tex : 3; /* AP */
UINT ap : 2; /* AP */
UINT pbit : 1; /* XSCALE 'P' bit */
UINT addrHi2: 4; /* SBZ [phys address 39:36] */
UINT pad1 : 1; /* SBO */
UINT c : 1; /* c-bit */
UINT b : 1; /* b-bit */
UINT type : 2; /* descriptor type, 2 => section */
} SUPERSECTION_DESC_FIELD;
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
typedef struct
{
UINT addr : 20; /* page base address */
UINT sbz : 2; /* should be zero */
UINT tex : 4; /* type extension field */
UINT ap : 2; /* access permission */
UINT cb : 2; /* cacheable/bufferable bits */
UINT type : 2; /* page type, 3 => extended small page */
} PTE_FIELD;
#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
/* First level descriptor access */
typedef union
{
PAGE_DESC_FIELD fields;
SECTION_DESC_FIELD sectionFields;
SUPERSECTION_DESC_FIELD supersectionFields;
UINT32 bits;
} MMU_LEVEL_1_DESC;
/* Second level descriptor access */
typedef union
{
PTE_FIELD fields;
UINT32 bits;
} PTE;
/*
* Structure for MMU translation table access - normally used to get a pointer
* to the first-level translation table.
* To support page table optimization, a second first-level table and a
* semaphore are needed.
* The initial, unoptimized set of page tables will be set as the active
* translation tables (via pLevel1Table) while optimization or deoptimization
* is in progress using the inactive second translation table (pAltLevel1Table).
* After each page table optimization or deoptimization operation has
* completed, the second translation table will be set as the active
* translation table. The initial set of page tables retain their
* links to level 2 pages, which may otherwise be lost after optimization.
* Any non-optimization changes to the active first-level table will also be
* made to the inactive first-level table.
* The semaphore is used to prevent corruption of the tables.
*/
typedef struct mmuTransTblStruct
{
MMU_LEVEL_1_DESC *pLevel1Table; /* active MMU table */
MMU_LEVEL_1_DESC *pAltLevel1Table; /* inactive MMU table */
VX_MUTEX_SEMAPHORE(mmuTransTblSem); /* MMU tables' semaphore */
UINT32 lockCnt; /* lock count */
atomic_t lockOwner; /* lock owner */
} MMU_TRANS_TBL;
#if defined(__STDC__) || defined(__cplusplus)
IMPORT void mmuArmXSCALELibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
IMPORT void mmuArmXSCALETtbrSet (MMU_LEVEL_1_DESC *);
IMPORT MMU_LEVEL_1_DESC * mmuArmXSCALETtbrGet ( void);
IMPORT void mmuArmXSCALEDacrSet (UINT32 dacrVal);
IMPORT void mmuArmXSCALETLBIDFlushEntry (void *addr);
IMPORT void mmuArmXSCALETLBIDFlushAll (void);
IMPORT void mmuArmXSCALEAEnable (UINT32 cacheState);
IMPORT void mmuArmXSCALEADisable (void);
IMPORT STATUS mmuArmXSCALEPBitSet ( void * virtAddr, UINT32 size);
IMPORT STATUS mmuArmXSCALEPBitClear ( void * virtAddr, UINT32 size);
IMPORT STATUS mmuArmXSCALEPBitGet ( void * virtAddr );
IMPORT STATUS mmuArmXSCALEAcrGet (void );
IMPORT void mmuArmXSCALEAcrSet (UINT32 acrVal);
#else /* __STDC__ */
IMPORT void mmuArmXSCALELibInstall ();
IMPORT void mmuArmXSCALETtbrSet ();
IMPORT MMU_LEVEL_1_DESC * mmuArmXSCALETtbrGet ();
IMPORT void mmuArmXSCALEDacrSet ();
IMPORT void mmuArmXSCALETLBIDFlushEntry ();
IMPORT void mmuArmXSCALETLBIDFlushAll ();
IMPORT void mmuArmXSCALEAEnable ();
IMPORT void mmuArmXSCALEADisable ();
IMPORT STATUS mmuArmXSCALEPBitSet ();
IMPORT STATUS mmuArmXSCALEPBitClear ();
IMPORT STATUS mmuArmXSCALEPBitGet ();
IMPORT STATUS mmuArmXSCALEAcrGet ();
IMPORT void mmuArmXSCALEAcrSet ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuArmXSCALELibh */
vxworks-6.9/target/h/arch/arm/mmuCortexA8Lib.h
+163
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/* mmuCortexA8Lib.h - Cortex-A8 MMU library header file */
/*
* Copyright (c) 2008, 2010-2012, 2013 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01j,19aug13,zgl LPAE support (WIND00357632)
01i,17jul12,j_b fix mmuCortexA8AcrGet API
01h,20dec11,jdw Add missing APIs to clear up warnings related to ttbr APIs
01g,25aug10,my_ Remove MMUCR_BIGEND in MMU_INIT_VALUE and add
MMUCR_EE in MMU_INIT_VALUE (WIND00229795)
01f,29apr10,pad Moved extern C statement after include statements.
01e,09feb10,j_b update mmuCortexA8TtbrSet for ASID support
01d,25aug10,my_ make EE bit default in BE8 mode (WIND00228157)
01c,05aug10,j_b enable branch prediction by default (CQID: 222896)
01b,05aug10,m_h Thumb-mode exception handling for Thumb-2
01a,11jun08,j_b Created from mmuArm1136jfLib.h, rev 01a
*/
#ifndef __INCmmuCortexALibh
#define __INCmmuCortexALibh
#include "memLib.h"
#ifndef _WRS_CONFIG_ARM_LPAE
#include <arch/arm/mmuArmArch6PalLib.h>
#else /* _WRS_CONFIG_ARM_LPAE */
#include <arch/arm/mmuArmLpaeLib.h>
#endif /* !_WRS_CONFIG_ARM_LPAE */
#ifdef __cplusplus
extern "C" {
#endif
/* Cortex-A Specific definitions follow */
/*
* Values to be used when mmuEnable() is called. This will be after the MMU has
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
* cache enable settings have been chosen.
* See "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition"
* (ARM DDI 0406) and "Cortex-A8 Processor Technical Reference Manual"
* (ARM DDI 0344) for details.
*
* M 1 Enable MMU
* A 0 Disable address alignment fault
* C X ((D-)Cache Enable) Controlled by cacheLib
* - 1 (Write Buffer - obsolete) Reserved; SBO
* - 1 (PROG32 - obsolete) Reserved; SBO
* - 1 (DATA32 - obsolete) Reserved; SBO
* - 1 (Late abort - obsolete) Reserved; SBO
* B 0 (Big/Little-endian - obsolete) Reserved; SBZ
* - 0 (System - obsolete) Reserved; SBZ
* - 0 (ROM - obsolete) Reserved; SBZ
* SW 0 (SWP/SWPB Enable - unsupported) SBZ; Reserved for Multiprocessing
* Z 1 (Branch prediction enable)
* I X (I-cache enable) Controlled by cacheLib
* V 0 (Vector table location: Normal/High Address)
* RR 0 (Random/Round-Robin cache replacement - unsupported) SBZ
* - 0 (Load instructions to PC set T bit - obsolete) SBZ
* - 1 (Data TCM enable - obsolete) SBO
* HA 0 (Hardware Access flag enable - unsupported) SBZ
* - 1 (Instruction TCM enable - obsolete) SBO
* - 0 Reserved; SBZ
* - 0 Reserved; SBZ
* FI 0 (Fast Interrupt enable - unsupported) SBZ
* U 1 (Unaligned access enable); SBO
* - 1 (extended PTE format enable - obsolete) SBO
* VE 0 (VEctored Interrupt - unsupported) SBZ
* EE 0 Exception Endian set to Little-Endian
* - 0 Reserved; SBZ
* NMFI 0 Disable NMFI behavior for FIQs
* TRE 0 Disable TEX Remap
* AFE 0 Disable Access Flag
* TE X if Thumb-2 enable Thumb Exceptions
* - 0 Reserved; SBZ
*
* For time being, do not enable the address alignment fault, as GCC
* currently generates unaligned accesses in its code, and switching this
* on will cause immediate faults. So, do not put it into the enable
* mask.
*
* We used to clear all the Reserved/Should Be Zero bits when the
* MMU/MPU was enabled, by including one bits for them in the definition
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
* the definitions of the bits within the MMU Control Register. The MMU
* Control register is initialised within romInit()/sysInit(), as the BSP
* is the only place where the particular details of the CPU/MMU are
* actually known. In general, it will be appropriate for the BSP to
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
* MMU is enabled, we will only change the bits we are particularly
* concerned about, by using a Read-Modify-Write strategy.
*/
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE)
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE)
#if (ARM_THUMB2)
#define MMU_EXCEPTION_MODE MMUCR_THUMB_EXCEPTIONS
#else /* (ARM_THUMB2) */
#define MMU_EXCEPTION_MODE 0x0
#endif /* (ARM_THUMB2) */
/* Control Register SBO bits */
#define MMU_MUST_SET_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_W_ENABLE | MMUCR_ENABLE_DTCM | \
MMUCR_ENABLE_ITCM | MMUCR_UNALIGNED_ENABLE | \
MMUCR_EXTENDED_PAGE | MMU_EXCEPTION_MODE)
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
#define MMU_INIT_VALUE (MMU_MUST_SET_VALUE | MMUCR_Z_ENABLE)
#else
#define MMU_INIT_VALUE (MMU_MUST_SET_VALUE | MMUCR_Z_ENABLE | MMUCR_EE)
#endif
#ifndef _ASMLANGUAGE
IMPORT void mmuCortexA8LibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
#ifndef _WRS_CONFIG_ARM_LPAE
IMPORT void mmuCortexA8TtbrSet (MMU_LEVEL_1_DESC *pTable, UINT32 asid);
IMPORT MMU_LEVEL_1_DESC * mmuCortexA8TtbrGet (void);
IMPORT void mmuCortexA8TtbrSetAll (UINT32 ttbr, UINT32 asid);
IMPORT UINT32 mmuCortexA8TtbrGetAll (void);
IMPORT void mmuCortexA8DacrSet (UINT32 dacrVal);
#else /* _WRS_CONFIG_ARM_LPAE */
IMPORT void mmuCortexA8TtbrSet64 (UINT64 ttbr);
IMPORT UINT64 mmuCortexA8TtbrGet64 (void);
IMPORT void mmuCortexA8MairSet(UINT32 mair0Val, UINT32 mair1Val);
IMPORT void mmuCortexA8TtbcrSet (UINT32 ttbcr);
IMPORT UINT32 mmuCortexA8TtbcrGet (void);
#endif /* !_WRS_CONFIG_ARM_LPAE */
IMPORT void mmuCortexA8TLBIDFlushEntry (VIRT_ADDR *addr);
IMPORT void mmuCortexA8TLBIDFlushAll (void);
IMPORT void mmuCortexA8AEnable (UINT32 cacheState);
IMPORT void mmuCortexA8ADisable (void);
IMPORT STATUS mmuCortexA8PBitSet (VIRT_ADDR virtAddr, UINT32 size);
IMPORT STATUS mmuCortexA8PBitClear (VIRT_ADDR virtAddr, UINT32 size);
IMPORT STATUS mmuCortexA8PBitGet (VIRT_ADDR virtAddr);
IMPORT UINT32 mmuCortexA8AcrGet (void);
IMPORT void mmuCortexA8AcrSet (UINT32 acrVal);
IMPORT STATUS mmuCortexA8ITcmrGet (void);
IMPORT void mmuCortexA8ITcmrSet (UINT32 acrVal);
IMPORT STATUS mmuCortexA8DTcmrGet (void);
IMPORT void mmuCortexA8DTcmrSet (UINT32 acrVal);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuCortexALibh */
vxworks-6.9/target/h/arch/arm/mpuArm940tLib.h
+92
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/* mpuArm940tLib.h - ARM 940T MPU library header file */
/* Copyright (c) 1998-2006, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement. No license to Wind River intellectual property rights
* is granted herein. All rights not licensed by Wind River are reserved
* by Wind River.
*/
/*
modification history
--------------------
01e,29apr10,pad Moved extern C statement after include statements.
01d,27jul06,m_h vxWorks 6.x palification
01c,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01b,10aug04,scm adjust for MPU removal...
01a,24nov98,cdp created.
*/
#ifndef __INCmpuArm940tLibh
#define __INCmpuArm940tLibh
#define MMU_ID_ARM940T 0x059400
#include "mpuArmPalLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
#define MMUCR_MODE MMUCR_ROM /* This MUST remain ROM for shared libraries */
#define MMUCR_L4_ENABLE (1<<15) /* L4 enable, ARMv4 behavior */
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE)
/*
* Values to be used when the MPU Control Register is initialised from
* within romInit.s or sysALib.s (before the MPU is enabled). Note that
* on 710A, this is also used to initialise the soft-copy of the MPU CR
* that we need to keep (in order to emulate Read-Modify-Write
* operations). So, the BSP *MUST* initialise the MPU CR with the value
* contained here, or else trouble will ensue. This restriction does
* not apply to non-710A BSPs, but caution must be exercised in choosing a
* value different to that defined here.
*/
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
/* W bit should Be One */
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_MODE)
#else /* _BYTE_ORDER == _LITTLE_ENDIAN now _BIG_ENDIAN */
/* big endian */
/* W bit should Be One */
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_BIGEND | MMUCR_MODE)
#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
#ifndef _ASMLANGUAGE
IMPORT void mpuArm940tLibInstall (void);
IMPORT STATUS mpuArm940tShowInstall (void);
IMPORT void mpuArm940tPrrSet (const MPU_REGION_REG *pRegs);
IMPORT void mpuArm940tPrrGet (MPU_REGION_REG *pRegs);
IMPORT void mpuArm940tCcrSet (UINT32 val);
IMPORT UINT32 mpuArm940tCcrGet (void);
IMPORT void mpuArm940tWbcrSet (UINT32 val);
IMPORT UINT32 mpuArm940tWbcrGet (void);
IMPORT void mpuArm940tPrSet (UINT32 val);
IMPORT UINT32 mpuArm940tPrGet (void);
IMPORT void mpuArm940tAEnable (UINT32 cacheState);
IMPORT void mpuArm940tADisable (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmpuArm940tLibh */
vxworks-6.9/target/h/arch/arm/mpuArm946eLib.h
+93
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@@ -0,0 +1,93 @@
/* mpuArm946eLib.h - ARM 946E MPU library header file */
/* Copyright (c) 1998-2006, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement. No license to Wind River intellectual property rights
* is granted herein. All rights not licensed by Wind River are reserved
* by Wind River.
*/
/*
modification history
--------------------
01f,29apr10,pad Moved extern C statement after include statements.
01e,13jul06,m_h MPU not MMU
01d,22may06,m_h Palify
01c,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
01b,10aug04,scm adjust for MPU removal...
01a,19jul00,jpd created, based on mmuArm940tLib.h.
*/
#ifndef __INCmpuArm946eLibh
#define __INCmpuArm946eLibh
#define MMU_ID_ARM946E 0x059460
#include "mpuArmPalLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
#define MMUCR_MODE MMUCR_ROM /* This MUST remain ROM for shared libraries */
#define MMUCR_L4_ENABLE (1<<15) /* L4 enable, ARMv4 behavior */
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE)
/*
* Values to be used when the MMU Control Register is initialised from
* within romInit.s or sysALib.s (before the MMU is enabled). Note that
* on 710A, this is also used to initialise the soft-copy of the MMU CR
* that we need to keep (in order to emulate Read-Modify-Write
* operations). So, the BSP *MUST* initialise the MMU CR with the value
* contained here, or else trouble will ensue. This restriction does
* not apply to non-710A BSPs, but caution must be exercised in choosing a
* value different to that defined here.
*/
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
/* W bit should Be One */
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_MODE)
#else /* _BYTE_ORDER == _LITTLE_ENDIAN now _BIG_ENDIAN */
/* big endian */
/* W bit should Be One */
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
MMUCR_BIGEND | MMUCR_MODE)
#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
#ifndef _ASMLANGUAGE
IMPORT void mpuArm946eLibInstall (void);
IMPORT STATUS mpuArm946eShowInstall (void);
IMPORT void mpuArm946ePrrSet (const MPU_REGION_REG *pRegs);
IMPORT void mpuArm946ePrrGet (MPU_REGION_REG *pRegs);
IMPORT void mpuArm946eCcrSet (UINT32 val);
IMPORT UINT32 mpuArm946eCcrGet (void);
IMPORT void mpuArm946eWbcrSet (UINT32 val);
IMPORT UINT32 mpuArm946eWbcrGet (void);
IMPORT void mpuArm946ePrSet (UINT32 val);
IMPORT UINT32 mpuArm946ePrGet (void);
IMPORT void mpuArm946eAEnable (UINT32 cacheState);
IMPORT void mpuArm946eADisable (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmpuArm946eLibh */
vxworks-6.9/target/h/arch/arm/mpuArmPalLib.h
+229
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/* mmuArmPalLib.h - ARM MPU library header file */
/* Copyright (c) 2006, 2007, 2010, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement. No license to Wind River intellectual property rights
* is granted herein. All rights not licensed by Wind River are reserved
* by Wind River.
*/
/*
modification history
--------------------
01e,16mar12,rec WIND00318272 - POSIX signals conformance
01d,29apr10,pad Moved extern C statement after include statements.
01c,21sep07,j_b add _func_mmuFaultAddrGet prototype
01b,13jul06,m_h Generic MPU definitions
01a,13jul06,m_h Created from mmuArmPalLib.h and vxWorks 5.5 mmuArmLib.h
*/
#ifndef __INCmpuArmPalLibh
#define __INCmpuArmPalLibh
#ifndef _ASMLANGUAGE
#include <memLib.h>
#ifdef __cplusplus
extern "C" {
#endif
#endif /* _ASMLANGUAGE */
#define MPU_NUM_REGIONS 8
#ifndef _ASMLANGUAGE
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
typedef struct
{
UINT enable : 1; /* 1 => region enabled */
UINT size : 5; /* size */
UINT pad : 6; /* padding */
UINT base : 20; /* region base address */
} MPU_REGION_FIELDS;
#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
/* Big-Endian */
typedef struct
{
UINT base : 20; /* region base address */
UINT pad : 6; /* padding */
UINT size : 5; /* size */
UINT enable : 1; /* 1 => region enabled */
} MPU_REGION_FIELDS;
#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
typedef union
{
MPU_REGION_FIELDS fields;
UINT32 bits;
} MPU_REGION_REG;
typedef struct mpuTransTblStruct
{
MPU_REGION_REG regs[MPU_NUM_REGIONS];
} MPU_TRANS_TBL;
#endif /* _ASMLANGUAGE */
/*
* Architecture-dependent MPU states. These are states settable for regions.
*/
/* The size must be larger than 0x0A so zero in these fields
* is an invalid MPU state is it is enabled (bit-0 = 1)
*/
#define MMU_STATE_INVALID_STATE 0xFFFFFFFF
#define MPU_REGION_BASE_MASK 0xFFFFF000
#define MPU_REGION_SIZE_MASK 0x0000003E
#define MPU_REGION_SIZE_MAX 0x0000003E
#define MMU_STATE_MASK_CACHEABLE 0xC0 /* CB bits */
#define MMU_STATE_MASK_BUFFERABLE 0x40
#define MMU_STATE_MASK_VALID 0x100 /* allows 4 AP bits */
#define MMU_STATE_VALID 0x100 /* Full Access */
#define MMU_STATE_VALID_NOT 0x000 /* No access */
#ifdef MPU_USE_EXTENDED_PERMISSIONS
#define MMU_STATE_NUM_AP_BITS 4
#define MMU_STATE_MASK_PROTECTION 0xF
#else /*MPU_USE_EXTENDED_PERMISSIONS*/
#define MMU_STATE_NUM_AP_BITS 2
#define MMU_STATE_MASK_PROTECTION 0x3
#endif /*MPU_USE_EXTENDED_PERMISSIONS*/
/* cacheable and bufferable states are not real physical bit definitions */
#ifdef ARMCACHE_HAS_WRITETHROUGH
/* Write-through mode is not available on all CPUs */
#define MMU_STATE_CACHEABLE_WRITETHROUGH 0x80
#endif /*ARMCACHE_HAS_WRITETHROUGH*/
#define MMU_STATE_CACHE_BIT 0x80
#define MMU_STATE_CACHEABLE_COPYBACK 0xC0
/*
* Set the default state to be copyback. CACHEABLE_WRITETHROUGH can also be
* selected on 740T/946E.
*/
#define MMU_STATE_CACHEABLE MMU_STATE_CACHEABLE_COPYBACK
#define MMU_STATE_CACHEABLE_NOT 0x0
#define MMU_STATE_BUFFERABLE 0x40 /* bufferable, not cacheable */
#define MMU_STATE_BUFFERABLE_NOT 0x0 /* will also set not cacheable*/
/*
* We need a size for a region that means the entire address
* space. It is perfectly reasonable to wish to define such a region
* and it is of course, not expressible within a UINT. So, define a
* special size.
*/
#define MMU_ENTIRE_SPACE 0
#define MMU_STATE_SUP_RW 0x01
#define MMU_STATE_USR_RO_SUP_RW 0x02
#define MMU_STATE_USR_RW_SUP_RW 0x03
#define MMU_STATE_SUP_RO 0x05
#define MMU_STATE_USR_RO_SUP_RO 0x06
/*
* When setting either of the attributes SPL_0 or SPL_1 it is necessary to:
*
* 1. specify MMU_ATTR_SPL_MSK ORred with MMU_ATTR_CACHE_MSK in the mask
* argument to the routine, and:
* 2. specify the appropriate cache state ORred in to the state argument
* to the routine.
*
* So, to set a page as bufferable not cacheable, it is necessary to
* specify both MMU_ATTR_SPL_0 and specify MMU_ATTR_CACHE_OFF in the
* state argument. To mark a page as cacheable in the minicache,
* MMU_ATTR_SPL_1 and MMU_ATTR_CACHE_COPYBACK must be specified in the
* state argument. In both cases, specify MMU_ATTR_SPL_MSK ORred with
* MMU_ATTR_CACHE_MSK in the mask argument.
*
* To "unset" the special attibutes SPL_0 or SPL_1, specify
* MMU_ATTR_CACHE_MSK in the mask parameter (without MMU_ATTR_SPL_MSK),
* and specify the cacheability required in the state argument.
*
* We provide the following alias on ARM, to make life easier.
*/
#define MMU_ATTR_BUFFERABLE (MMU_ATTR_SPL_0)
/* MMU Control Register bit allocations */
#define MMUCR_M_ENABLE (1<<0) /* MMU enable */
#define MMUCR_A_ENABLE (1<<1) /* Address alignment fault enable */
#define MMUCR_C_ENABLE (1<<2) /* (data) cache enable */
#define MMUCR_W_ENABLE (1<<3) /* write buffer enable */
#define MMUCR_PROG32 (1<<4) /* PROG32 */
#define MMUCR_DATA32 (1<<5) /* DATA32 */
#define MMUCR_L_ENABLE (1<<6) /* Late abort on earlier CPUs */
#define MMUCR_BIGEND (1<<7) /* Big-endian (=1), little-endian (=0) */
#define MMUCR_SYSTEM (1<<8) /* System bit, modifies MMU protections */
#define MMUCR_ROM (1<<9) /* ROM bit, modifies MMU protections */
#define MMUCR_F (1<<10) /* Should Be Zero */
#define MMUCR_Z_ENABLE (1<<11) /* Branch prediction enable on 810 */
#define MMUCR_I_ENABLE (1<<12) /* Instruction cache enable */
#define MMUCR_V_ENABLE (1<<13) /* Exception vectors remap to 0xFFFF0000 */
#define MMUCR_ALTVECT MMUCR_V_ENABLE /* alternate vector select */
#define MMUCR_RR_ENABLE (1<<14) /* Round robin cache replacement enable */
#define MMUCR_ROUND_ROBIN MMUCR_RR_ENABLE /* round-robin placement */
#define MMUCR_DISABLE_TBIT (1<<15) /* disable TBIT */
#define MMUCR_DSRAM_EN (1<<16) /* D-SRAM enable */
#define MMUCR_DSRAM_LOADMODE (1<<17) /* D-SRAM load mode select */
#define MMUCR_ISRAM_EN (1<<18) /* I-SRAM enable */
#define MMUCR_ISRAM_LOADMODE (1<<19) /* I-SRAM load mode select */
#ifndef _ASMLANGUAGE
/* Externally visible mpuLib routines */
IMPORT UINT32 mmuReadId (void);
IMPORT UINT32 (* mmuCrGet) (void);
IMPORT void (* mmuModifyCr) (UINT32 value, UINT32 mask);
IMPORT UINT32 mmuHardCrGet (void);
IMPORT UINT32 mmuSoftCrGet (void);
IMPORT void mmuModifyHardCr (UINT32 value, UINT32 mask);
IMPORT void mmuModifySoftCr (UINT32 value, UINT32 mask);
IMPORT UINT32 (* _func_mmuFaultAddrGet) (void);
IMPORT UINT32 (* _func_mmuFaultStatusGet) (void);
#if (CPU == ARMARCH6) || (CPU==ARMARCH7) || (CPU==ARMARCH7_T2)
IMPORT UINT32 (* _func_mmuIFaultStatusGet) (void);
#endif /* ARMARCH6 || ARMARCH7 || ARMARCH7_T2 */
IMPORT void mpuPrrSet (const MPU_REGION_REG *pRegs);
IMPORT void mpuPrrGet (MPU_REGION_REG *pRegs);
IMPORT void mpuCcrSet (UINT32 val);
IMPORT UINT32 mpuCcrGet (void);
IMPORT void mpuWbcrSet (UINT32 val);
IMPORT UINT32 mpuWbcrGet (void);
IMPORT void mpuPrSet (UINT32 val);
IMPORT UINT32 mpuPrGet (void);
IMPORT void mpuAEnable (UINT32 cacheState);
IMPORT void mpuADisable (void);
IMPORT UINT32 mpuGetEnable (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmpuArmPalLibh */
vxworks-6.9/target/h/arch/arm/mpuGlobalMap.h
+91
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@@ -0,0 +1,91 @@
/* mpuGlobalMap.h - arch "independent" header MPU functionality */
/*
* Copyright (c) 2006 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01b,13jul06,m_h Arch "independent" MPU definitions normally found in vmLib.h
(actually vmLibP.h)
01a,13jul06,m_h written.
*/
#ifndef __INCmpuGlobalMaph
#define __INCmpuGlobalMaph
#include <private/vmLibP.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
typedef struct mpuTransTblStruct * MPU_TRANS_TBL_ID;
typedef STATUS (*MPUGLOBALPAGEMAPFUNCPTR)(VIRT_ADDR, PHYS_ADDR, UINT, BOOL);
typedef STATUS (*MPUTRANSLATEFUNCPTR)(struct mpuTransTblStruct *,
VIRT_ADDR, PHYS_ADDR *);
typedef STATUS (*MPUPHYSTRANSLATEFUNCPTR)(struct mpuTransTblStruct *,
PHYS_ADDR, VIRT_ADDR *);
typedef struct
{
FUNCPTR mpuLibInit;
MPU_TRANS_TBL_ID (*mpuTransTblCreate) ();
FUNCPTR mpuTransTblDelete;
FUNCPTR mpuEnable;
FUNCPTR mpuStateSetRegion;
FUNCPTR mpuStateGet;
MPUGLOBALPAGEMAPFUNCPTR mpuGlobalPageMap;
MPUTRANSLATEFUNCPTR mpuTranslate;
VOIDFUNCPTR mpuCurrentSet;
FUNCPTR mpuAttrTranslate;
FUNCPTR mpuShow;
} MPU_LIB_FUNCS;
#define MPU_ENABLE (*(mpuLibFuncs.mpuEnable))
#define MPU_TRANS_TBL_CREATE (*(mpuLibFuncs.mpuTransTblCreate))
#define MPU_STATE_SET_REGION (*(mpuLibFuncs.mpuStateSetRegion))
#define MPU_CURRENT_SET (*(mpuLibFuncs.mpuCurrentSet))
#define MPU_GLOBAL_PAGE_MAP (*(mpuLibFuncs.mpuGlobalPageMap))
#define MPU_ATTR_TRANSLATE (*(mpuLibFuncs.mpuAttrTranslate))
#define MPU_TRANSLATE (*(mpuLibFuncs.mpuTranslate))
#define MPU_TRANS_TBL_DELETE (*(mpuLibFuncs.mpuTransTblDelete))
#define MPU_SHOW (*(mpuLibFuncs.mpuShow))
IMPORT MPU_LIB_FUNCS mpuLibFuncs;
IMPORT void mpuLibInstall (void);
IMPORT STATUS
mpuGlobalMapInit (PHYS_MEM_DESC * pMemDescArray,
int numDescArrayElements,
BOOL enable,
int cacheDefault);
IMPORT STATUS
mpuStateSet (void *addr, int len, UINT stateMask, UINT state);
IMPORT STATUS mpuShow (void);
#endif /*_ASMLANGUAGE*/
#ifdef __cplusplus
}
#endif
#endif /* __INCmpuGlobalMaph */
vxworks-6.9/target/h/arch/arm/private/smpArmP.h
+410
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@@ -0,0 +1,410 @@
/* private/smpArmP.h - ARM/XScale-specific definitions for SMP support */
/*
* Copyright (c) 2007-2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Any compilation using definitions from this file will not *
* be binary-compatible between the UP and SMP environments. *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*/
/*
modification history
--------------------
01r,10sep12,ggm updated for tes.
01q,02dec11,jdw Add _fpStatus per WIND00129622
01p,30nov10,j_b add unified FIQ/IRQ handling support
01o,29jul10,pad Moved extern C statement after include statements.
01n,07jul10,jdw Add _WRS_ARCH_HAS_OBJ_SAFE
01m,21may10,m_h Thumb-2 Support
01l,15may09,gls moved VX_INSTR_BARRIER() to vxAtomicArchLibCommon.h
01k,25feb09,j_b merge ARM SMP support:
03feb09,j_b define _WRS_SNOOP_NEEDS_DMA_MALLOC_SUPPORT so
cacheAimArch6DmaMalloc/Free are used with CACHE_SNOOP_ENABLE
04oct07,j_b define _WRS_ARCH_REQUIRES_CACHE_TEXT_UPDATE_CPC
31aug07,m_h Fix _ARM_PER_CPU_* macros for CPU != 0
18jun07,m_h syntax error non-SMP _ARM_CPU_INDEX_GET
01j,18sep08,gls added _WRS_KERNEL_LOCK_VAR_ALIGN
01i,27aug08,jpb Renamed VSB header file
01h,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
01g,20jun08,zl replaced _WRS_ASM() with _WRS_BARRIER()
01f,10jan08,gls added VX_INSTR_BARRIER()
01e,09may07,lei renamed reschedNeeded to reschedMode.
01d,09may07,m_h Fix per-CPU SMP macros, cleanup kernel global offsets
01c,03may07,m_h SMP definitions
01b,20apr07,m_h SMP Private definitions
01a,04apr07,m_h written.
*/
#ifndef __INCsmpArmPh
#define __INCsmpArmPh
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _WRS_CONFIG_SMP
/*
* ARM has been adapted to use the new object safe count feature for SMP.
* When all architectures have been adapted this can be removed from
* the code.
*/
#define _WRS_ARCH_HAS_OBJ_SAFE
/*
* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
* XSCALE, etc), representing the maximum cache line size of the variants of
* the respective arch.
*
* For ARM this is 128 bytes.
*/
#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
/*
* ARM11 MPCore does not support cache coherency with DMA agents or
* shared memory, so uncached memory must be returned by cacheDmaMalloc()
* (via cacheAimArch6DmaMalloc) when CACHE_SNOOP_ENABLE is defined
* (ex., in SMP mode).
* See usage in target\src\os\mm\cacheLib.c:cacheFuncsSet().
*/
#define _WRS_SNOOP_NEEDS_DMA_MALLOC_SUPPORT
/* Trigger software cacheTextUpdate CPC */
#define _WRS_ARCH_REQUIRES_CACHE_TEXT_UPDATE_CPC
/* ARM specific extension fields to the WIND_VARS struct */
#ifndef _ASMLANGUAGE
typedef struct wind_vars_arch
{
long cpu_intNestingLevel;
long cpu_maxIntNestingLevel;
UINT32 cpu_cacheArchState;
char * cpu_undefSaveArea;
char * cpu_abortSaveArea;
char * cpu_swiSaveArea;
char * cpu_irqStack;
UINT32 cpu_fpStatus;
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
long cpu_fiqNestingLevel;
long cpu_maxFiqNestingLevel;
char * cpu_fiqStack;
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
} WIND_VARS_ARCH;
#define _WRS_WIND_VARS_ARCH WIND_VARS_ARCH cpu_archVars
/* macro to access the arch-specific fields of the vxKernelVars struct */
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
_WRS_KERNEL_GLOBAL_ACCESS (archVars.cpu_##glob)
#define _WRS_WIND_VARS_ARCH_SET(cpuid,glob,var) \
_WRS_KERNEL_CPU_GLOBAL_SET(cpuid,archVars.cpu_##glob,var)
#define _WRS_WIND_VARS_ARCH_GET(cpuid,glob) \
_WRS_KERNEL_CPU_GLOBAL_GET(cpuid,archVars.cpu_##glob)
#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_SET(archVars.cpu_##glob,var)
#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_GET(archVars.cpu_##glob,var)
/* TODO optimization work needed in regsArm.h (etc) */
#undef _WRS_ARCH_SUPPORTS_VX_CPU_STATE_INIT
#else /* !_ASMLANGUAGE */
/* offsets required for assembly macros */
#define WIND_VARS_ARCH_BASE (_WRS_WIND_VARS_OFFSET_archVars)
#endif /* _ASMLANGUAGE */
/*
* _WRS_WIND_VARS_ALIGN sets the alignment constraint for vxKernelVars. The
* value must be: a power of two no smaller than sizeof(vxKernelVars), and a
* multiple of the cache line size (which is 32) on every ARM variant that
* supports SMP.
*/
#define _WRS_WIND_VARS_ALIGN 128
#define _WRS_WIND_VARS_ALIGN_SHIFT 7
/*
* _ARM_ATOMIC_OPS_SEPARATION defines the minimum desirable separation between
* words on which SMP-atomic operations (including spinlock) will be
* performed. This is the cache line size on ARM MP.
*/
#define _ARM_ATOMIC_OPS_SEPARATION _CPU_CACHE_ALIGN_SIZE
# ifdef _CPU_CACHE_ALIGN_SIZE
/*
* Validate _WRS_WIND_VARS_ALIGN vs current build's _CPU_CACHE_ALIGN_SIZE
*
* If any SMP-enabled variant fails this test, _WRS_WIND_VARS_ALIGN must be
* increased. Since this limit also applies to any subsequent arch-only
* release against the same generic binary release, it may be desirable to
* allow for growth.
*/
# if (_CPU_CACHE_ALIGN_SIZE > _WRS_WIND_VARS_ALIGN)
#error Must increase "_WRS_WIND_VARS_ALIGN" to at least _CPU_CACHE_ALIGN_SIZE
# endif /* _CPU_CACHE_ALIGN_SIZE > _WRS_WIND_VARS_ALIGN */
/*
* Sanity check on _ARM_ATOMIC_OPS_SEPARATION
*
* A miss here generates a warning instead of an error, since it is merely
* likely (not inevitable) that the lwarx/stwcx. granularity matches the
* cache line size; also the performance penalty is less. (Two instances of
* vxKernelVars within the same cache line will cause continual interference,
* but two atoms within the same reservation granule will only occasionally
* cause additional trips around the lwarx/stwcx. loop due to loss of the
* reservation to an unrelated store.)
*/
# if (_CPU_CACHE_ALIGN_SIZE > _ARM_ATOMIC_OPS_SEPARATION)
#warning Check "_ARM_ATOMIC_OPS_SEPARATION" setting; it likely should be at least _CPU_CACHE_ALIGN_SIZE
# endif /* _CPU_CACHE_ALIGN_SIZE > _ARM_ATOMIC_OPS_SEPARATION */
# endif /* _CPU_CACHE_ALIGN_SIZE */
/*
* Just call the (assembly) function for now, but to optimize
* performance this should eventually become a C-callable
* _WRS_ASM construct (whose syntax varies depending on TOOL).
*/
#define _WRS_CPU_INDEX_GET() vxCpuIndexGet()
#else /* _WRS_CONFIG_SMP */
/* macro to access the arch-specific fields */
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
_WRS_KERNEL_GLOBAL_ACCESS (glob)
#define _WRS_WIND_VARS_ARCH_SET(ignored,glob,var) \
_WRS_KERNEL_CPU_GLOBAL_SET(ignored,glob,var)
#define _WRS_WIND_VARS_ARCH_GET(ignored,glob) \
_WRS_KERNEL_CPU_GLOBAL_GET(ignored,archVars.cpu_##glob)
#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_SET(glob,var)
#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_GET(glob,var)
#define _WRS_CPU_INDEX_GET() 0
#endif /* _WRS_CONFIG_SMP */
#ifdef _ASMLANGUAGE
#include <private/windLibP.h>
# ifdef _WRS_CONFIG_SMP
#include <private/kernelLockLibP.h>
/*
* Sticking a "#" in the middle of a complex #define generates garbage
* passed to the assembler which results in a syntax error. ARM_HASH is
* used by this file in order to tell the assembler to use an immediate
* value.
*/
#define ARM_HASH #
#define _ARM_WIND_VARS_OFFSET(label) _WRS_WIND_VARS_OFFSET_##label
#define _ARM_WIND_VARS_OFFSET_reschedMode \
#_WRS_WIND_VARS_OFFSET_reschedMode
/* ARM specific per-CPU globals */
#define _WRS_WIND_VARS_OFFSET_intNestingLevel \
(_WRS_WIND_VARS_OFFSET_archVars+0x0)
#define _WRS_WIND_VARS_OFFSET_maxIntNestingLevel \
(_WRS_WIND_VARS_OFFSET_archVars+0x4)
#define _WRS_WIND_VARS_OFFSET_cacheArchState \
(_WRS_WIND_VARS_OFFSET_archVars+0x8)
#define _WRS_WIND_VARS_OFFSET_undefSaveArea \
(_WRS_WIND_VARS_OFFSET_archVars+0xC)
#define _WRS_WIND_VARS_OFFSET_abortSaveArea \
(_WRS_WIND_VARS_OFFSET_archVars+0x10)
#define _WRS_WIND_VARS_OFFSET_swiSaveArea \
(_WRS_WIND_VARS_OFFSET_archVars+0x14)
#define _WRS_WIND_VARS_OFFSET_irqStack \
(_WRS_WIND_VARS_OFFSET_archVars+0x18)
#define _WRS_WIND_VARS_OFFSET_fpStatus \
(_WRS_WIND_VARS_OFFSET_archVars+0x1C)
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
#define _WRS_WIND_VARS_OFFSET_fiqNestingLevel \
(_WRS_WIND_VARS_OFFSET_archVars+0x20)
#define _WRS_WIND_VARS_OFFSET_maxFiqNestingLevel \
(_WRS_WIND_VARS_OFFSET_archVars+0x24)
#define _WRS_WIND_VARS_OFFSET_fiqStack \
(_WRS_WIND_VARS_OFFSET_archVars+0x28)
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
#define _ARM_CPU_ID_MASK #0xF
#define ARM_WIND_VARS_ALIGN_SHIFT #(_WRS_WIND_VARS_ALIGN_SHIFT)
/* Using CPU ID, get the index into the CPU's vxKernelVars */
/* Note: reading CPU ID requires CPU privileged mode */
#define _ARM_CPU_INDEX_GET(r) \
MRC p15, 0, r, c0, c0, 5 ; \
AND r, r, _ARM_CPU_ID_MASK
/* place the address of label into register r */
#define _ARM_PER_CPU_ADRS_GET(r, scratch, label) \
_ARM_CPU_INDEX_GET(r) ; \
LDR scratch, L$_vxKernelVars ; \
ADD scratch, scratch, r, LSL ARM_WIND_VARS_ALIGN_SHIFT ; \
ADD r, scratch, ARM_HASH _ARM_WIND_VARS_OFFSET(label) ; \
/*
* In some configurations (e.g. Thumb-2) there are special restrictions on
* usage of the sp register. Also there appears to be a defect in some
* versions of the Wind River assembler related to similar use of the lr
* register. So use these macros for setting up sp or lr.
*/
#define _ARM_PER_CPU_ADRS_GET_SPLR(r_sp, scratch, label) \
_ARM_PER_CPU_ADRS_GET(r_sp, scratch, label)
/* place the value at label into register r */
#define _ARM_PER_CPU_VALUE_GET_SPLR(r_sp, scratch, label) \
_ARM_PER_CPU_VALUE_GET(r_sp, scratch, label)
/* place the value at label into register r */
#define _ARM_PER_CPU_VALUE_GET(r,scratch,label) \
_ARM_CPU_INDEX_GET(r) ; \
LDR scratch, L$_vxKernelVars ; \
ADD scratch, scratch, r, LSL ARM_WIND_VARS_ALIGN_SHIFT ; \
ADD scratch, scratch, ARM_HASH _ARM_WIND_VARS_OFFSET(label) ; \
LDR r, [scratch]
/* place value at label in rv, also place address at label in ra */
#define _ARM_PER_CPU_VALUE_AND_ADRS_GET(rv,ra,label) \
_ARM_CPU_INDEX_GET(rv) ; \
LDR ra, L$_vxKernelVars ; \
ADD ra, ra, rv, LSL ARM_WIND_VARS_ALIGN_SHIFT ; \
ADD ra, ra, ARM_HASH _ARM_WIND_VARS_OFFSET(label) ; \
LDR rv, [ra]
/*
* ro = register to store kernel lock owner
* ri = register to store cpu index
*
* typedef struct smpLock
* {
* volatile int state; /@ state of lock (free/taken) @/
* volatile int owner; /@ CPU which owns the lock @/
* int count; /@ recursive ownership nesting count @/
* int options; /@ options applicable to this lock @/
*/
#define _ARM_KERNEL_LOCK_OWNER_AND_INDEX_GET(ro, ri) \
_ARM_CPU_INDEX_GET(ri) ; \
LDR ro, L$_kernelStateLock ; \
ADD ro, ro, ARM_HASH _WRS_KERNEL_LOCK_OFFSET_cpuIndex ; \
LDR ro, [ro] /* kernel spin lock owner */ ; \
# else /* _WRS_CONFIG_SMP */
#define IMM0 #0
/* Macro unconditionally returns 0 when built for UP */
#define _ARM_CPU_INDEX_GET(r) MOV r, IMM0
/*
* WARNING: UP build assumes that scratch register is not used.
* There is only one scratch register available in
* excEnterCommon
*/
/* place the address of label into register r */
#define _ARM_PER_CPU_ADRS_GET(r, scratch, label) \
LDR r, L$_##label
/* place the value at label into register r */
#define _ARM_PER_CPU_VALUE_GET(r, scratch, label) \
LDR r, L$_##label ; \
LDR r, [r]
/* place value at label in ra, also place address at label in rv */
#define _ARM_PER_CPU_VALUE_AND_ADRS_GET(rv,ra,label) \
LDR ra, L$_##label ; \
LDR rv, [ra]
/*
* In some configurations (e.g. Thumb-2) there are special restrictions on
* usage of the sp register. Also there appears to be a defect in some
* versions of the Wind River assembler related to similar use of the lr
* register. So use these macros for setting up sp or lr.
*/
# if (ARM_THUMB2)
/* place the address of label into register r */
#define _ARM_PER_CPU_ADRS_GET_SPLR(r_sp, scratch, label) \
LDR scratch, L$_##label ; \
MOV r_sp, scratch
/* place the value at label into register r */
#define _ARM_PER_CPU_VALUE_GET_SPLR(r_sp, scratch, label) \
LDR scratch, L$_##label ; \
LDR r_sp, [scratch]
# else /* (ARM_THUMB2) */
/* place the address of label into register r */
#define _ARM_PER_CPU_ADRS_GET_SPLR(r_sp, scratch, label) \
_ARM_PER_CPU_ADRS_GET(r_sp, scratch, label)
/* place the value at label into register r */
#define _ARM_PER_CPU_VALUE_GET_SPLR(r_sp, scratch, label) \
_ARM_PER_CPU_VALUE_GET(r_sp, scratch, label)
# endif /* (ARM_THUMB2) */
# endif /* _WRS_CONFIG_SMP */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCsmpArmPh */
vxworks-6.9/target/h/arch/arm/private/vxPortableArchP.h
+75
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@@ -0,0 +1,75 @@
/* vxPortableArchP.h - ARM portable library configuration */
/*
* Copyright (c) 2007, 2009-2010, 2013, 2017 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01g,28jul17,swu undef _WRS_PORTABLE_vxCpuPhysIndexGet for armv7-a (VXW6-86373)
01f,24apr13,yjw undef _WRS_PORTABLE_schedLib for armv7-m
01e,29oct10,j_b undefine _WRS_PORTABLE_vxCpuIdGet
01d,08jun09,j_b undef _WRS_PORTABLE_schedLib for uniprocessor
01c,11jul07,to undef _WRS_PORTABLE_vxAtomicLib if ldrex/strex are supported
01b,06jul07,to undef _WRS_PORTABLE_vxCpuIndexGet
01a,04may07,zl created
*/
#ifndef __INCvxPortableArchPh
#define __INCvxPortableArchPh
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file is included from <private/vxPortableP.h>. It may undefine
* portable library definitions in order to enable architecture specific
* implementation of a library or routine.
*/
/* the following can be overridden with PORTABLE */
#ifndef PORTABLE
#undef _WRS_PORTABLE_bLib
#undef _WRS_PORTABLE_dllLib
#undef _WRS_PORTABLE_ffsLib
#ifdef _WRS_CPU_HAS_CLZ_INSTR
# undef _WRS_PORTABLE_ffsTbl
#endif
#ifndef _WRS_CONFIG_SMP
# undef _WRS_PORTABLE_schedLib
#endif
#endif /* !PORTABLE */
/* the following cannot be overridden with PORTABLE */
#if (CPU == ARMARCH7M)
# undef _WRS_PORTABLE_schedLib
#endif
#if (CPU == ARMARCH7)
# undef _WRS_PORTABLE_vxCpuPhysIndexGet
#endif
#if (ARM_HAS_LDREX_STREX == TRUE)
#undef _WRS_PORTABLE_vxAtomicLib
#endif
#undef _WRS_PORTABLE_vxCpuIdGet
#undef _WRS_PORTABLE_vxCpuIndexGet
#ifdef __cplusplus
}
#endif
#endif /* __INCvxPortableArchPh */
vxworks-6.9/target/h/arch/arm/private/vxdbgArmLibP.h
+98
View File
@@ -0,0 +1,98 @@
/* vxdbgArmLibP.h - private ARM VxDBG library header file */
/*
* Copyright (c) 2007-2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable Wind
* River license agreement.
*/
/*
modification history
--------------------
01h,24apr12,jdw Update for ARM-M
01g,09feb11,rlp Defined VXDBG_INT_LOCK_LEVEL_COMPUTE macro for both UP and
SMP (CQ:WIND00253870).
01f,29apr10,pad Moved extern C statement after include statements.
01e,25feb09,j_b merge ARM SMP support:
12nov07,jmp Added support for VxDBG cpu control library.
01d,27aug08,jpb Renamed VSB header file
01c,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
01b,26oct07,rlp Added the VXDBG_INT_LOCK_LEVEL_COMPUTE macro (CQ:WIND00109321).
01a,11oct07,rlp Written
*/
#ifndef __INCvxdbgArmLibPh
#define __INCvxdbgArmLibPh
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* This macro returns the <level> parameter modified with the interrupt lock
* level defined into the <value> parameter. The <level> parameter must be
* previously get with either intCpuLock() or intRegsLock() API.
*/
#if (CPU == ARMARCH7M)
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
((level & ~PRIMASK_PM) | (value & PRIMASK_PM))
#else /* CPU == ARMARCH7M */
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
((level & ~I_BIT) | (value & I_BIT))
#endif /* CPU == ARMARCH7M */
#ifdef _WRS_CONFIG_SMP
/* return TRUE if interrupts are locked in specified register set. */
#define VXDBG_INT_REGS_IS_LOCKED(pRegs) (((pRegs->cpsr & I_BIT) == \
I_BIT) ? TRUE : FALSE)
/*
* _WRS_VXDBG_CPU_CTRL_VARS_ALIGN sets the alignment constraint for
* vxdbgCpuCtrlVars array.
* The value must be:
* a power of two no smaller than sizeof(vxdbgCpuCtrlVars), and
* a multiple of the cache line size on every ARM variant that supports SMP.
*/
#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN 128
#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN_SHIFT 7
#define ARM_VXDBG_CPU_CTRL_VARS_ALIGN_SHIFT \
#(_WRS_VXDBG_CPU_CTRL_VARS_ALIGN_SHIFT)
#ifdef _CPU_CACHE_ALIGN_SIZE
/*
* Validate _WRS_VXDBG_CPU_CTRL_VARS_ALIGN vs current build's
* _CPU_CACHE_ALIGN_SIZE
*
* If any SMP-enabled variant fails this test, _WRS_VXDBG_CPU_CTRL_VARS_ALIGN
* must be increased. Since this limit also applies to any subsequent arch-only
* release against the same generic binary release, it may be desirable to
* allow for growth.
*/
#if (_CPU_CACHE_ALIGN_SIZE > _WRS_VXDBG_CPU_CTRL_VARS_ALIGN)
#error Must increase "_WRS_VXDBG_CPU_CTRL_VARS_ALIGN" to at least _CPU_CACHE_ALIGN_SIZE
#endif /* _CPU_CACHE_ALIGN_SIZE > _WRS_VXDBG_CPU_CTRL_VARS_ALIGN */
#endif /* _CPU_CACHE_ALIGN_SIZE */
/* externals */
#ifndef _ASMLANGUAGE
extern void intVxdbgCpuRegsGet (void);
#endif /* _ASMLANGUAGE */
#endif /* _WRS_CONFIG_SMP */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxdbgArmLibPh */
vxworks-6.9/target/h/arch/arm/regsArm.h
+107
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@@ -0,0 +1,107 @@
/* regsArm.h - ARM registers */
/*
* Copyright (c) 1996, 1998, 2003, 2004, 2007, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01i,09may12,j_b enable ARMARCH7M-specific header usage
01h,03may12,j_b revert to remove ARMARCH7M-specific header usage
01g,01may12,j_b Update for ARMv7M
01f,18jun07,m_h Adding definition for WIND_CPU_STATE
01e,25aug04,scm add lrReg alternative name
01d,18mar04,scm add usr mode rtp support...
01c,07may03,pes PAL conditional compilation cleanup.
01b,15apr98,kkk added reg_pc, reg_sp, and reg_fp.
01a,08may96,cdp written, based on I86 version
*/
#ifndef __INCregsArmh
#define __INCregsArmh
#if (CPU == ARMARCH7M)
#include "arch/arm/arm-m/regsArm-m.h"
#else /* (CPU == ARMARCH7M) */
#ifdef __cplusplus
extern "C" {
#endif
#define GREG_NUM 15 /* has 15 32-bit general registers */
#ifndef _ASMLANGUAGE
/* REG_SET - ARM Register set
* Note that the exception stack frame relies on the order of items
* in this so don't change this without changing the ESF and the stub
* in excALib which creates it.
*/
typedef struct /* REG_SET - ARM register set */
{
ULONG r[GREG_NUM]; /* general purpose registers 0-14 */
INSTR *pc; /* program counter */
ULONG cpsr; /* current PSR */
ULONG ttbase; /* Trans Table Base */
} REG_SET;
typedef struct wind_cpu_state
{
REG_SET regs;
} WIND_CPU_STATE;
#define fpReg r[11] /* frame pointer */
#define spReg r[13] /* stack pointer */
#define lrReg r[14] /* link reg pointer */
#define reg_pc pc /* program counter */
#define reg_lr lrReg /* link reg pointer */
#define reg_sp spReg /* stack pointer */
#define reg_fp fpReg /* frame pointer */
#endif /* _ASMLANGUAGE */
#define ARM_REG_SIZE 4
#define REG_SET_G_REG_BASE 0x00 /* data reg's base offset to REG_SET */
#define REG_SET_G_REG_OFFSET(n) (REG_SET_G_REG_BASE + (n)*ARM_REG_SIZE)
#define REG_SET_PC_OFFSET (REG_SET_G_REG_OFFSET(GREG_NUM))
#define REG_SET_CPSR_OFFSET (REG_SET_PC_OFFSET + ARM_REG_SIZE)
#define REG_SET_TTBASE_OFFSET (REG_SET_CPSR_OFFSET + ARM_REG_SIZE)
#define PC_OFFSET REG_SET_PC_OFFSET
/* PAL additions */
/* moved here from h/private/taskLibP.h */
#define WIND_TCB_R0 WIND_TCB_REGS
#define WIND_TCB_R1 (WIND_TCB_R0+4*1)
#define WIND_TCB_R4 (WIND_TCB_R0+4*4)
#define WIND_TCB_R5 (WIND_TCB_R0+4*5)
#define WIND_TCB_SP (WIND_TCB_R0+4*13)
#define WIND_TCB_PC (WIND_TCB_R0+4*15)
#define WIND_TCB_CPSR (WIND_TCB_PC+4)
#define WIND_TCB_TTBASE (WIND_TCB_CPSR+4)
/* End PAL */
#ifdef __cplusplus
}
#endif
#endif /* (CPU == ARMARCH7M) */
#endif /* __INCregsArmh */
vxworks-6.9/target/h/arch/arm/sigArmCodes.h
+26
View File
@@ -0,0 +1,26 @@
/* sigArmCodes.h - ARM signal facility library header file */
/* Copyright 1996-1997 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,09may96,cdp created
*/
#ifndef __INCsigArmCodesh
#define __INCsigArmCodesh
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCsigArmCodesh */
vxworks-6.9/target/h/arch/arm/syscallArgsarm.h
+870
View File
@@ -0,0 +1,870 @@
/* Aligned for arm - no alignment needed */
/* THIS FILE IS AUTO_GENERATED. PLEASE DO NOT EDIT. */
#ifndef _ASMLANGUAGE
#include <vxWorks.h>
#include <taskLib.h>
#include <rtpLib.h>
#include <sdLib.h>
#include <shlLib.h>
#include <signal.h>
#include <socket.h>
#include <time.h>
#include <setjmp.h>
#include <ioLib.h>
#include <private/semSysCall.h>
#include <private/objLibP.h>
#include <private/rtpLibP.h>
#include <private/mqPxSysCall.h>
#include <private/pxObjSysCall.h>
#include <private/semPxSysCall.h>
#include <private/taskSysCall.h>
#include <private/timerSysCall.h>
#include <private/eventSysCall.h>
#include <sys/resource.h>
#include <sys/types.h>
#include <base/b_trace_attr_t.h>
#include <base/b_trace_id_t.h>
#include <base/b_trace_event_id_t.h>
#include <base/b_pthread_t.h>
struct _exitScArgs
{
int status;
};
struct _creatScArgs
{
const char * name;
mode_t flag;
};
struct _openScArgs
{
const char * name;
int flags;
int mode;
};
struct _closeScArgs
{
int fd;
};
struct _readScArgs
{
int fd;
void * buffer;
size_t maxbytes;
};
struct _writeScArgs
{
int fd;
const void * buffer;
size_t nbytes;
};
struct _ioctlScArgs
{
int fd;
int function;
_Vx_ioctl_arg_t arg;
};
struct dupScArgs
{
int fd;
};
struct dup2ScArgs
{
int fd;
int fd2;
};
struct pipeScArgs
{
int filedes[2];
};
struct removeScArgs
{
const char * name;
};
struct selectScArgs
{
int width;
fd_set * readFds;
fd_set * writeFds;
fd_set * excFds;
struct timeval * timeout;
};
struct socketScArgs
{
int domain;
int type;
int protocol;
};
struct bindScArgs
{
int s;
struct sockaddr * name;
int namelen;
};
struct listenScArgs
{
int s;
int backlog;
};
struct acceptScArgs
{
int s;
struct sockaddr * addr;
int *addrlen;
};
struct connectScArgs
{
int s;
struct sockaddr * name;
int namelen;
};
struct sendtoScArgs
{
int s;
caddr_t buf;
int bufLen;
int flags;
struct sockaddr * to;
int tolen;
};
struct sendScArgs
{
int s;
const char * buf;
int bufLen;
int flags;
};
struct sendmsgScArgs
{
int s;
struct msghdr * mp;
int flags;
};
struct recvfromScArgs
{
int s;
char * buf;
int bufLen;
int flags;
struct sockaddr *from;
int * pFromLen;
};
struct recvScArgs
{
int s;
char * buf;
int bufLen;
int flags;
};
struct recvmsgScArgs
{
int s;
struct msghdr * mp;
int flags;
};
struct setsockoptScArgs
{
int s;
int level;
int optname;
char * optval;
int optlen;
};
struct getsockoptScArgs
{
int s;
int level;
int optname;
char * optval;
int * optlen;
};
struct getsocknameScArgs
{
int s;
struct sockaddr *name;
int * namelen;
};
struct getpeernameScArgs
{
int s;
struct sockaddr *name;
int *namelen;
};
struct shutdownScArgs
{
int s;
int how;
};
struct mmapScArgs
{
void * addr;
size_t len;
int prot;
int flags;
int fildes;
off64_t off;
};
struct munmapScArgs
{
void * addr;
size_t len;
};
struct mprotectScArgs
{
void * addr;
size_t len;
int prot;
};
struct killScArgs
{
OBJ_HANDLE rtpId;
int signo;
};
struct sigpendingScArgs
{
sigset_t * pSet;
};
struct sigprocmaskScArgs
{
int how;
const sigset_t * pSet;
sigset_t * pOset;
};
struct _sigqueueScArgs
{
OBJ_HANDLE rtpId;
int signo;
const union sigval * pValue;
int sigCode;
};
struct _sigsuspendScArgs
{
const sigset_t * pSet;
};
struct _sigtimedwaitScArgs
{
const sigset_t * pSet;
struct siginfo * pInfo;
const struct timespec * pTime;
};
struct _sigactionScArgs
{
int signo;
const struct sigaction * pAct;
struct sigaction * pOact;
void * retAddr;
};
struct chdirScArgs
{
const char * name;
};
struct _getcwdScArgs
{
char * buffer;
int length;
};
struct _waitpidScArgs
{
OBJ_HANDLE childRtpId;
int * pStatus;
int options;
};
struct sysctlScArgs
{
int * pName;
u_int nameLen;
void * pOld;
size_t * pOldLen;
void * pNew;
size_t newLen;
};
struct _schedPxInfoGetScArgs
{
BOOL * pTimeSlicingOn;
ULONG * pTimeSlicePeriod;
};
struct sigaltstackScArgs
{
stack_t * ss;
stack_t * oss;
};
struct unlinkScArgs
{
const char * name;
};
struct linkScArgs
{
const char * name;
const char * newname;
};
struct _fsyncScArgs
{
int fd;
};
struct _fdatasyncScArgs
{
int fd;
};
struct renameScArgs
{
const char * oldname;
const char * newname;
};
struct fpathconfScArgs
{
int fd;
int name;
};
struct pathconfScArgs
{
const char * path;
int name;
};
struct accessScArgs
{
const char * path;
int amode;
};
struct chmodScArgs
{
const char * path;
mode_t mode;
};
struct pxTraceCreationScArgs
{
int cmd;
pid_t pid;
trace_attr_t * attr;
int fd;
trace_id_t * trid;
};
struct pxTraceCtlScArgs
{
int cmd;
trace_id_t trid;
struct trace_event_set_t * filter;
int how;
pthread_t thread_id;
void * pc;
void * ptr_out;
};
struct pxTraceEventScArgs
{
int cmd;
int id_in;
char * data;
size_t data_len;
pthread_t thread_id;
void * pc;
trace_event_id_t * id_out;
};
struct pxTraceEventNameQueryScArgs
{
int cmd;
trace_id_t trid;
int id_in1;
int id_in2;
char * name;
trace_event_id_t * id_out;
int * unavailable;
};
struct pxTraceLogScArgs
{
int cmd;
trace_id_t trid_in;
int fd;
trace_id_t *trid_out;
};
struct pxTraceEventGetScArgs
{
int cmd;
trace_id_t trid;
size_t num_bytes;
struct timespec * timeout;
struct posix_trace_event_info * event;
void * data;
size_t * data_len;
int * unavailable;
};
struct eventReceiveScArgs
{
UINT32 events;
UINT32 options;
_Vx_ticks_t timeout;
UINT32 * pEvtsReceived;
};
struct eventSendScArgs
{
int taskId;
UINT32 events;
};
struct eventCtlScArgs
{
OBJ_HANDLE handle;
VX_EVT_CTL_CMD command;
void * pArg;
size_t * pArgSize;
};
struct msgQSendScArgs
{
OBJ_HANDLE handle;
char * buffer;
size_t nBytes;
_Vx_ticks_t timeout;
int priority;
};
struct msgQReceiveScArgs
{
OBJ_HANDLE handle;
char * buffer;
size_t maxNBytes;
_Vx_ticks_t timeout;
};
struct _msgQOpenScArgs
{
const char * name;
size_t maxMsgs;
size_t maxMsgLength;
int options;
int mode;
void * context;
};
struct objDeleteScArgs
{
OBJ_HANDLE handle;
int options;
};
struct objInfoGetScArgs
{
OBJ_HANDLE handle;
void * pInfo;
size_t * pInfoSize;
int level;
};
struct _semTakeScArgs
{
OBJ_HANDLE handle;
_Vx_ticks_t timeout;
};
struct _semGiveScArgs
{
OBJ_HANDLE handle;
};
struct _semOpenScArgs
{
const char * name;
SEM_TYPE type;
int initState;
int options;
int mode;
void * context;
};
struct semCtlScArgs
{
OBJ_HANDLE handle;
VX_SEM_CTL_CMD command;
void * pArg;
size_t * pArgSize;
};
struct _taskOpenScArgs
{
struct vx_task_open_sc_args * pArgs;
};
struct taskCtlScArgs
{
int tid;
VX_TASK_CTL_CMD command;
void * pArg;
size_t * pArgSize;
};
struct taskDelayScArgs
{
_Vx_ticks_t ticks;
};
struct rtpSpawnScArgs
{
const char * rtpFileName;
const char ** argv;
const char ** envp;
int priority;
size_t uStackSize;
int options;
int taskOptions;
};
struct rtpInfoGetScArgs
{
OBJ_HANDLE rtpId;
RTP_DESC * rtpStruct;
};
struct taskKillScArgs
{
OBJ_HANDLE taskHandle;
int signo;
};
struct _taskSigqueueScArgs
{
OBJ_HANDLE taskHandle;
int signo;
const union sigval * pValue;
int sigCode;
};
struct _timer_openScArgs
{
const char * name;
int mode;
clockid_t clockId;
struct sigevent * evp;
void * context;
};
struct timerCtlScArgs
{
TIMER_CTL_CMD cmdCode;
OBJ_HANDLE timerHandle;
void * pArgs;
size_t pArgSize;
};
struct pxOpenScArgs
{
PX_OBJ_TYPE type;
const char * name;
int objOpenMode;
void * attr;
};
struct pxCloseScArgs
{
OBJ_HANDLE handle;
};
struct pxUnlinkScArgs
{
PX_OBJ_TYPE type;
const char * name;
};
struct pxCtlScArgs
{
OBJ_HANDLE handle;
PX_CTL_CMD_CODE cmdCode;
void * pArgs;
size_t * pArgSize;
};
struct pxMqReceiveScArgs
{
OBJ_HANDLE handle;
char * pMsg;
size_t msgLen;
unsigned int * pMsgPrio;
PX_WAIT_OPTION waitOption;
const struct timespec * time_out;
};
struct pxMqSendScArgs
{
OBJ_HANDLE handle;
const char * pMsg;
size_t msgLen;
unsigned int msgPrio;
PX_WAIT_OPTION waitOption;
const struct timespec * time_out;
};
struct pxSemWaitScArgs
{
OBJ_HANDLE handle;
PX_WAIT_OPTION waitOption;
const struct timespec * time_out;
};
struct pxSemPostScArgs
{
OBJ_HANDLE handle;
};
struct pipeDevCreateScArgs
{
const char * name;
size_t nMessages;
size_t nBytes;
};
struct pipeDevDeleteScArgs
{
const char * name;
BOOL force;
};
struct _sdCreateScArgs
{
char * name;
int options;
size_t size;
off64_t physAddress;
MMU_ATTR attr;
void ** pVirtAddress;
};
struct _sdOpenScArgs
{
char * name;
int options;
int mode;
size_t size;
off64_t physAddress;
MMU_ATTR attr;
void ** pVirtAddress;
};
struct sdDeleteScArgs
{
OBJ_HANDLE handle;
int options;
};
struct sdMapScArgs
{
OBJ_HANDLE handle;
MMU_ATTR attr;
int options;
};
struct sdUnmapScArgs
{
OBJ_HANDLE handle;
int options;
};
struct sdProtectScArgs
{
OBJ_HANDLE handle;
MMU_ATTR attr;
};
struct _edrErrorInjectScArgs
{
int kind;
const char *fileName;
int lineNumber;
REG_SET *regset;
void *addr;
const char *msg;
};
struct wvEventScArgs
{
int eventId;
const char * pData;
unsigned int dataSize;
};
struct rtpVarAddScArgs
{
void ** pVar;
void * value;
};
struct sdInfoGetScArgs
{
OBJ_HANDLE handle;
SD_DESC * pSdStruct;
};
struct _shlOpenScArgs
{
const char * name;
int options;
};
struct _shlUnlockScArgs
{
SHL_ID shlId;
};
struct _shlCloseScArgs
{
SHL_ID shlId;
};
struct _shlGetScArgs
{
SHL_ID shlId;
SHLINFO *pInfo;
};
struct _shlPutScArgs
{
SHL_ID shlId;
const SHLINFO *pInfo;
};
struct objUnlinkScArgs
{
const char * name;
enum windObjClassType classType;
};
struct getprlimitScArgs
{
int idtype;
OBJ_HANDLE handle;
int resource;
struct rlimit *rlp;
};
struct setprlimitScArgs
{
int idtype;
OBJ_HANDLE handle;
int resource;
struct rlimit *rlp;
};
struct _mctlScArgs
{
void * addr;
size_t len;
int function;
void * arg;
};
struct _taskOpenWithGuardScArgs
{
struct vx_task_open_guard_sc_args * pArgs;
};
struct clockCtlScArgs
{
clockid_t clock_id;
CLOCK_CTL_CMD cmdCode;
void * pArgStruct;
size_t * pArgSize;
};
struct _semRTakeScArgs
{
OBJ_HANDLE handle;
_Vx_ticks_t timeout;
};
struct _semWTakeScArgs
{
OBJ_HANDLE handle;
_Vx_ticks_t timeout;
};
struct _semExchangeScArgs
{
OBJ_HANDLE giveHandle;
OBJ_HANDLE takeHandle;
_Vx_ticks_t timeout;
};
struct wvRtpEventScArgs
{
int eventId;
const char * pData;
unsigned int dataSize;
};
struct _selectScArgs
{
int width;
fd_set * readFds;
fd_set * writeFds;
fd_set * excFds;
struct timeval * timeout;
};
struct _sigtimedwait2ScArgs
{
const sigset_t * pSet;
struct siginfo * pInfo;
const struct timespec * pTime;
};
#endif /* _ASMLANGUAGE */
vxworks-6.9/target/h/arch/arm/syscallArm.h
+95
View File
@@ -0,0 +1,95 @@
/* syscallArm.h - ARM specific System Call Infrastructure header */
/*
* Copyright (c) 2003, 2005, 2007 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01g,03dec09,cww Moved ARM specific macros from syscallLibP.h
01f,04may07,zl updated portable library build configuration.
01e,04mar05,scm _SYSCALL_USER_SP_CHECK break signals alt stack option...
01d,23feb05,scm re-assign "spare" to user link reg...
01c,19nov03,cjj replaced pStackLimit by pStackEnd in _SYSCALL_USER_SP_CHECK
01b,14oct03,scm enhanced, flushed out, and debugging.
01a,03oct03,jb written.
*/
/*
DESCRIPTION
This header contains ARM specific definitions and constants used by
the System Call Infrastructure library.
*/
#ifndef __INCsyscallArmh
#define __INCsyscallArmh
#ifndef _ASMLANGUAGE
#include <taskLib.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#define SYSCALL_ENTRY_FRAME_SIZE 52
#define _SYSCALL_USER_SP_CHECK(sp)
/* typedefs */
#ifndef _ASMLANGUAGE
/*
* The SYSCALL_ENTRY_STATE structure defines the saved machine state
* when the system call trap is taken. This information is architecture
* specific, and is used by the system call dispatcher to restart system
* calls that have been interrupted by the occurance of signals.
* System call restart is achieved by restoring the saved state at the
* time of the system call trap, and re-issuing the system call.
* Arguments to the system call are saved on the kernel stack, and
* the address of that array is passed as an argument to the dispatcher.
* The layout of this structure must exactly match the ordering of members
* of the system call entry frame in src/arch/arm/syscallALib.s.
*/
typedef struct syscall_entry_state
{
ULONG args[8]; /* argument list (r0-r3 and sp[0]-sp[3]) */
ULONG scn; /* System Call Number (SCN) in r12 */
ULONG statusReg; /* saved Status Register (spsr) */
INSTR *pc; /* Trap return address (lr) */
ULONG *pUStack; /* user-mode stack pointer */
ULONG usrLnk; /* user-mode link register */
} SYSCALL_ENTRY_STATE;
#define ARM_RTP_STACK_OFFSET 12 /* ARM pushes r2, SCn, and lr onto */
/* stack prior to signal handling */
#define SYSCALL_USER_SP_GET(tid) (char *) \
(((SYSCALL_ENTRY_STATE *) ((((WIND_TCB *)(tid))->pExcStackBase) - \
(sizeof(SYSCALL_ENTRY_STATE)+ARM_RTP_STACK_OFFSET)))->pUStack)
#define SYSCALL_USER_PC_GET(tid) (void *) \
(((SYSCALL_ENTRY_STATE *) ((((WIND_TCB *)(tid))->pExcStackBase) - \
(sizeof(SYSCALL_ENTRY_STATE)+ARM_RTP_STACK_OFFSET)))->pc)
#define SYSCALL_USER_SCN_GET(tid) (int) \
(((SYSCALL_ENTRY_STATE *) ((((WIND_TCB *)(tid))->pExcStackBase) - \
(sizeof(SYSCALL_ENTRY_STATE)+ARM_RTP_STACK_OFFSET)))->scn)
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCsyscallArmh */
vxworks-6.9/target/h/arch/arm/vfpArmLib.h
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/* vfpArmLib.h - Arm Version of Vector Floating-Point Include File */
/*
* Copyright (c) 2005, 2009-2013 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01f,22aug13,mpc Add VFP support for ARMARCH7M
01e,09oct12,jdw Add support to configure Round To Zero mode in FPSCR
01d,25jul11,jdw Add support for VFPv3-D32 for ARMARCH7
01c,29apr10,pad Moved extern C statement after include statements.
01b,15may09,mdo Assembler is fixed
01a,29jun05,scm VFP written
*/
#ifndef __INCvfpArmLibh
#define __INCvfpArmLibh
#include <vxWorks.h>
#include <regs.h>
#include <esf.h>
#if (CPU == ARMARCH7M)
#include <arch/arm/arm-m/vfpArmLib.h>
#else
#ifdef __cplusplus
extern "C" {
#endif
/* VFP System Registers */
/* FPSID (Floating Point System ID Register) bit definitions */
/* READ ONLY register, RESET State:0x410120b3, Access Mode:Any */
#define FPSID_IMPLEMENTOR_MSK 0xFF000000
#define FPSID_ARM_LTD 0x41000000 /* ARM Limited */
#define FPSID_SW_MSK (1<<23)
#define FPSID_SW FPSID_SW_MSK
#define FPSID_HW 0x00000000
#define FPSID_FORMATR_MSK 0x00600000
#define FPSID_STNDRD_F1 0x00000000
#define FPSID_STNDRD_F2 (1<<21)
#define FPSID_RSRVD_F (1<<22)
#define FPSID_NONSTDRD_F 0x00600000
#define FPSID_SNG_MSK (1<<20)
#define FPSID_SNG_ONLY FPSID_SNG_MSK
#define FPSID_ARCH_MSK 0x000F0000
#define FPSID_VFP1 0x00000000
#define FPSID_VFP2 0x00010000 /* VFPv2 */
#define FPSID_PRTNUM_MSK 0x0000FF00
#define FPSID_VFP11 0x00002000 /* VFP11 */
#define FPSID_VARIANT_MSK 0x000000F0
#define FPSID_ARM11_VFP 0x000000B0 /* ARM 11 VFP */
#define FPSID_REV_MSK 0x0000000F
/* FPSCR (Floating Status and Control Register) bit definitions */
/* READ/WRITE register, RESET State:0x00000000, Access Mode:Any */
/*
* At the time of implementation bits 27-25,19,15-13, and 7-5,
* are described as DNM (DO NOT MODIFY), one must employ
* read/modify/write techniques when handling the FPSCR in order
* to ensure that these bits are not modified...
*/
#define FPSCR_N_BIT (1<<31) /* less than result */
#define FPSCR_Z_BIT (1<<30) /* equal result */
#define FPSCR_C_BIT (1<<29) /* equal, greater than, or unordered result */
#define FPSCR_V_BIT (1<<28) /* unordered result */
#define FPSCR_DN_BIT (1<<25) /* Default NaN mode control */
#define FPSCR_DN_MSK FPSCR_DN_BIT
#define FPSCR_DN_ENABLE FPSCR_DN_BIT
#define FPSCR_DN_DISABLE 0x00000000
#define FPSCR_FZ_BIT (1<<24) /* flush to zero mode control */
#define FPSCR_FZ_MSK FPSCR_FZ_BIT
#define FPSCR_FZ_ENABLE FPSCR_FZ_BIT
#define FPSCR_FZ_DISABLE 0x00000000
/* Trap Enable Bits */
#define FPSCR_IDE_BIT (1<<15) /* Input Subnormal */
#define FPSCR_IXE_BIT (1<<12) /* Inexact */
#define FPSCR_UFE_BIT (1<<11) /* Underflow */
#define FPSCR_OFE_BIT (1<<10) /* Overflow */
#define FPSCR_DZE_BIT (1<<9) /* Division By Zero */
#define FPSCR_IOE_BIT (1<<8) /* Invalid Operation */
/* Cumulative Exception Bits */
#define FPSCR_IDC_BIT (1<<7) /* Input Subnormal */
#define FPSCR_IXC_BIT (1<<4) /* Inexact */
#define FPSCR_UFC_BIT (1<<3) /* Underflow */
#define FPSCR_OFC_BIT (1<<2) /* Overflow */
#define FPSCR_DZC_BIT (1<<1) /* Division By Zero */
#define FPSCR_IOC_BIT (1<<0) /* Invalid Operation */
#define FPSCR_RMODES_MSK 0x00C00000
#define FPSCR_RN 0x00000000
#define FPSCR_RP 0x00400000
#define FPSCR_RM 0x00800000
#define FPSCR_RZ 0x00C00000
#define FPSCR_STRIDE_MSK 0x00300000
#define FPSCR_LEN_MSK 0x00070000
/* FPEXC (Floating Exception Register) bit definitions */
/* READ/WRITE register, RESET State:0x00000000, Access Mode:Privileged */
#define FPEXC_EX_BIT (1<<31) /* status bit */
#define FPEXC_EN_BIT (1<<30) /* global enable bit */
#define FPEXC_FP2V_BIT (1<<28) /* FPINST2 instruction valid bit */
/* Vector Iteration */
#define FPEXC_VECITR_MSK 0x00000700
#define FPEXC_VECITR_1 0x00000000
#define FPEXC_VECITR_2 0x00000100
#define FPEXC_VECITR_3 0x00000200
#define FPEXC_VECITR_4 0x00000300
#define FPEXC_VECITR_5 0x00000400
#define FPEXC_VECITR_6 0x00000500
#define FPEXC_VECITR_7 0x00000600
#define FPEXC_VECITR_8 0x00000700
#define FPEXC_INV_BIT (1<<7) /* Input Exception bit */
#define FPEXC_UFC_BIT (1<<3) /* Potential Underflow bit */
#define FPEXC_OFC_BIT (1<<2) /* Potential Overflow bit */
#define FPEXC_IOC_BIT (1<<0) /* Potential Invalid Operation bit */
/* VFP11 Specific System Registers */
/* FPINST (Floating Point Instruction Register) bit definitions */
/* READ/WRITE register, RESET State:0xEE000A00, Access Mode:Privileged */
/*
* FPINST register contains the exceptional instruction
*/
/* FPINST2 (Floating Point Instruction Register 2) bit definitions */
/* READ/WRITE register, RESET State:Unpredictable, Access Mode:Privileged */
/*
* FPINST2 register contains the instruction that was issued to the VFP11
* coprocessor before the exception was detected
*/
/* MFVFR0 (Media and VFP Feature Register 0) bit definitions */
/* READ ONLY register, RESET State:0x11111111, Access Mode:Any */
/* MFVFR1 (Media and VFP Feature Register 1) bit definitions */
/* READ ONLY register, RESET State:0x00000000, Access Mode:Any */
/* initialization parameters */
/*
* The VFP coprocessor allows the Round To Zero mode to be used to perform
* faster VFP computations, but is not strictly IEEE-754 compliant. The
* default for ARM is to enable Round To Zero mode. See the ARM Architecture
* Reference Manual for more information.
*/
#ifdef _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO
#define FPSCR_INIT FPSCR_DN_MSK
#else /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
#define FPSCR_INIT (FPSCR_DN_MSK | FPSCR_FZ_BIT)
#endif /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
#define _VFP_ALIGN_SIZE 8 /* 64 bit */
#define VFPREG_SET VFP_CONTEXT
/* FP_CONTEXT structure offsets */
#define VFP_FPSID 0x00
#define VFP_FPSCR 0x04
#define VFP_FPEXC 0x08
#define VFP_FPINST 0x0C
#define VFP_FPINST2 0x10
#define VFP_MVVFR0 0x14
#define VFP_MVVFR1 0x18
#define VFP_PAD -
#define VFP_GPR 0x20 /* OFFSET(FP_CONTEXT, vfp_gpr[0]) */
#define VFP_GPR_OFFSET(n) (VFP_GPR + (n)*4) /* vfp_gpr[n]) */
/* VFP_REG_SET - ARM VFP register set */
#ifdef _WRS_CONFIG_ENABLE_VFPV3_D32
/*
* VFPv3-D32 / NEON
* 64 single precision or 32 double precision general purpose
*/
#define VFP_DGPR_NUM 32 /* 32-double precision general purpose */
#define VFP_SGPR_NUM 64 /* 64-single precision general purpose */
#else /* _WRS_CONFIG_ENABLE_VFPV3_D32 */
/*
* VFPv3-D16
* 32 single precision or 16 double precision general purpose
*/
#define VFP_DGPR_NUM 16 /* 16-double precision general purpose */
#define VFP_SGPR_NUM 32 /* 32-single precision general purpose */
#endif /* _WRS_CONFIG_ENABLE_VFPV3_D32 */
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
# define HREG 1
# define LREG 0
#else /* _BYTE_ORDER != _LITTLE_ENDIAN */
# define HREG 0
# define LREG 1
#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
#ifndef _ASMLANGUAGE
typedef union
{
double u64;
UINT32 u32[2];
} VFP_UNION64D;
typedef struct vfpContext /* VFP Context */
{
UINT32 fpsid; /* system ID register : 4 */
UINT32 fpscr; /* status and control register : 4 */
UINT32 fpexc; /* exception register : 4 */
UINT32 fpinst; /* instruction register : 4 */
UINT32 fpinst2; /* instruction register 2 : 4 */
UINT32 mfvfr0; /* media and VFP feature Register 0: 4 */
UINT32 mfvfr1; /* media and VFP feature Register 1: 4 */
UINT32 pad;
UINT32 vfp_gpr[VFP_SGPR_NUM]; /* general purpose registers : 128 or 256 */
/* TOTAL : 156 or 284 */
} WRS_PACK_ALIGN(_VFP_ALIGN_SIZE) VFP_CONTEXT;
/* function declarations */
IMPORT void vfpArchInit (void);
IMPORT void vfpArchTaskCreateInit (VFP_CONTEXT *pDspContext);
IMPORT void vfpSave (VFP_CONTEXT *);
IMPORT void vfpRestore (VFP_CONTEXT *);
IMPORT STATUS vfpProbe (void);
IMPORT STATUS vfpProbeTrap (void);
IMPORT STATUS vfpEnable (void);
IMPORT STATUS vfpDisable (void);
IMPORT VFP_CONTEXT * vfpCtxCreate (int);
IMPORT STATUS vfpCtxDelete (VFP_CONTEXT *);
IMPORT void vfpCtxShow (VFP_CONTEXT *);
void vfpRegsToCtx (VFPREG_SET *, VFP_CONTEXT *);
void vfpCtxToRegs (VFP_CONTEXT *, VFPREG_SET *);
#ifdef _WRS_HW_VFP_SUPPORT
IMPORT int vfpIsEnabled (void);
IMPORT int vfpHasException (void);
IMPORT STATUS vfpProbeSup (void);
IMPORT UINT32 vfpFpSidGet (void);
IMPORT UINT32 vfpFpScrGet (void);
IMPORT void vfpFpScrSet (UINT32);
#endif
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* CPU == ARMARCH7M */
#endif /* __INCvfpArmLibh */
vxworks-6.9/target/h/arch/arm/vxAtomicArchLib.h
+38
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@@ -0,0 +1,38 @@
/* vxAtomicArchLib.h - ARM specific atomic library header */
/*
* Copyright (c) 2007-2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01e,29apr10,pad Moved extern C statement after include statements.
01d,15may09,gls made memory barriers available in user space
01d,25feb09,j_b merge ARM SMP support:
05mar08,j_b fix gnu inline assembly declarations
15feb08,j_b add inline _dsb (Data Synchronization Barrier)
09jul07,to added memory barrier macros for ARMARCH6
01c,16jun08,zl use _WRS_BARRIER() for memory barrier implementations
01b,07may07,m_h Atomic Operator definitions
01a,07may07,m_h Created
*/
#ifndef __INCvxAtomicArchLibh
#define __INCvxAtomicArchLibh
#include <arch/arm/vxAtomicArchLibCommon.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __INCvxAtomicArchLibh */
vxworks-6.9/target/h/arch/arm/vxAtomicArchLibCommon.h
+155
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/* vxAtomicArchLibCommon.h - ARM specific atomic library header */
/*
* Copyright (c) 2009-2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01g,18may12,j_b add support for ARMARCH7M
01f,04mar11,j_b replace hardcoded DMB, DSB opcodes after compiler fix
01e,12jan11,jdw Fix inline assembly opcodes for T2 (WIND00249791)
01d,21oct10,j_b add memory barrier support for ARMv7
01c,07jun09,kk add VX_INSTR_BARRIER() back
01b,05jun09,kk move inlines from vxAtomicArchLib.h to here
01a,17may09,gls written.
*/
#ifndef __INCvxAtomicArchLibCommonh
#define __INCvxAtomicArchLibCommonh
#ifdef __cplusplus
extern "C" {
#endif
/* Remove this line when all arch implement memory barrier API */
#define _WRS_ARCH_SUPPORTS_MEM_BARRIER
/*
* ARM architecture 6 and later defines two kinds of memory barriers:
* - Data Synchronization Barrier (DSB)
* - Data Memory Barrier (DMB)
*
* DMB is enough for read/write memory barrier.
*/
#if (CPU == ARMARCH6) || (CPU == ARMARCH7) || \
(CPU == ARMARCH7_T2) || (CPU == ARMARCH7M)
# if (CPU == ARMARCH6)
/* ARMARCH6 provides memory barrier operations via system control processor */
# if defined (__DCC__)
__asm volatile void __dmb ()
{
! "r0"
mov r0, #0
mcr p15, 0, r0, c7, c10, 5
}
__asm volatile void __dsb ()
{
! "r0"
mov r0, #0
mcr p15, 0, r0, c7, c10, 4
}
# elif defined (__GNUC__)
static __inline__ void __dmb (void)
{
int sbz = 0;
__asm__ volatile (
"mcr p15, 0, %0, c7, c10, 5"
: /* no output */
: "r" (sbz)
: "memory");
}
static __inline__ void __dsb (void)
{
int sbz = 0;
__asm__ volatile (
"mcr p15, 0, %0, c7, c10, 4"
: /* no output */
: "r" (sbz)
: "memory");
}
# else /* !__DCC_ && !__GNUC__ */
#error "error!!! unsupported compiler!!!"
# endif /* __DCC__ */
# elif (CPU == ARMARCH7) || (CPU == ARMARCH7_T2) || \
(CPU == ARMARCH7M)
/* ARMARCH7 provides memory barrier instructions */
# if defined (__DCC__)
__asm volatile void __dmb ()
{
DMB
}
__asm volatile void __dsb ()
{
DSB
}
# elif defined (__GNUC__)
static __inline__ void __dmb (void)
{
__asm__ volatile (
"dmb"
: /* no output */
: /* no input */
: "memory");
}
static __inline__ void __dsb (void)
{
__asm__ volatile (
"dsb"
: /* no output */
: /* no input */
: "memory");
}
# else /* !__DCC_ && !__GNUC__ */
#error "error!!! unsupported compiler!!!"
# endif /* __DCC__ */
# endif /* (CPU == ARMARCH6) */
#define VX_MEM_BARRIER_R() __dmb()
#define VX_MEM_BARRIER_W() __dmb()
#define VX_MEM_BARRIER_RW() __dmb()
#define VX_INSTR_BARRIER() __dmb()
#define VX_SYNC_BARRIER() __dsb()
#else /* (CPU == ARMARCH6) || (CPU == ARMARCH7) || (CPU == ARMARCH7_T2) */
#define VX_MEM_BARRIER_R() _WRS_ASM("NOP")
#define VX_MEM_BARRIER_W() _WRS_ASM("NOP")
#define VX_MEM_BARRIER_RW() _WRS_ASM("NOP")
#define VX_INSTR_BARRIER() _WRS_ASM("NOP")
#define VX_SYNC_BARRIER() _WRS_ASM("NOP")
#endif /* (CPU == ARMARCH6) || (CPU == ARMARCH7) || (CPU == ARMARCH7_T2) */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxAtomicArchLibCommonh */
vxworks-6.9/target/h/arch/arm/vxInlineArch.h
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/* vxInlineArch.h - ARM inline macro configuration */
/*
* Copyright (c) 2007, 2009-2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01c,21may10,m_h Thumb-2 Support
01b,18may09,j_b add _inline_intCpuMicroLock/Unlock support
01a,19jun07,zl created
*/
#ifndef __INCvxInlineArchh
#define __INCvxInlineArchh
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file is included from <vxInline.h>. It may define _WRS_INLINE_xxx
* build configuration macros in order to enable architecture specific
* inlined implementation of a macro definition.
*/
#if !(ARM_THUMB) && !(ARM_THUMB2)
#define _WRS_INLINE_intCpuLock
#define _WRS_INLINE_intCpuUnlock
#define _WRS_INLINE_intCpuMicroLock
#define _WRS_INLINE_intCpuMicroUnlock
#endif /* !ARM_THUMB && !ARM_THUMB2 */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxInlineArchh */