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neelimap
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/* aimCacheLib.h - AIM header for Cache Functions */
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/*
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* Copyright (c) 2003, 2005, 2008, 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01k,27may10,pad Added 'extern C' statement.
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01j,27aug08,jpb Renamed VSB header file
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01i,18jun08,jpb Added include path for kernel configurations options set in
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vsb.
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01h,08may08,jpb Modifications for source build. Renamed INCLUDE_MEM_ALLOT to
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_WRS_CONFIG_MEM_ALLOT.
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01g,24aug05,h_k converted INCLUDE_CACHE_xxx to arch feature.
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01f,19jul05,mil Scaled out features for minimal kernel.
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01e,19nov03,scm flush out cache AIM lock/unlock...
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01d,22oct03,jb Incorporating changes from inspection
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01d,24sep03,jb Continuing Development
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01c,09jun03,jb Continue development
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01b,01may03,jb Continue development
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01a,04apr03,jb written
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*/
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#ifndef __INCaimCacheLibh
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#define __INCaimCacheLibh
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/* Includes Section */
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#include <vsbConfig.h>
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#include <cacheLib.h>
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#include <vwModNum.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Defines Section */
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/*
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* AIM cache errors
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*/
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/* temporary until vwModNum.h is updated */
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#define M_aimcacheLib (190 << 16)
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enum aimCacheErrors {
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S_aimCacheLib_UNKNOWN_CACHE_TYPE = (M_aimcacheLib + 1 ),
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S_aimCacheLib_UNSUPPORTED_CACHE_FUNC,
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S_aimCacheLib_UNKNOWN_CACHE_OP
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};
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/* definitions of function argument types */
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#define C_FLG_MASK 0xFFFFFF00 /* Extract function types */
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#define C_FLG_OP_MASK 0x000000FF /* Extract cache operation */
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#define C_FLG_NOOP 0x00000100 /* Operation not supported */
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#define C_FLG_MGMT 0x00000200 /* Management function, enable/disable */
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#define C_FLG_VIRT 0x00000400 /* Function takes a Virtual Address */
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#ifdef _WRS_SUPPORT_CACHE_ISPHYSICAL
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#define C_FLG_PHYS 0x00000800 /* Function takes a Physical Address */
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#endif /* _WRS_SUPPORT_CACHE_ISPHYSICAL */
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#ifdef _WRS_SUPPORT_CACHE_ISINDEXED
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#define C_FLG_IDX_ONED 0x00001000 /* Function operates on a Indexed, */
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/* one dimensional array */
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#define C_FLG_IDX_TWOD 0x00002000 /* Function operates on a Indexed, */
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/* two dimensional array */
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#endif /* _WRS_SUPPORT_CACHE_ISINDEXED */
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#define C_FLG_ALL 0x00004000 /* Operates on the entire cache*/
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#define C_FLG_DISP 0x00008000 /* Flush uses displacement */
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#ifdef _WRS_SUPPORT_CACHE_LOCK
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#define C_FLG_LOCKPRTKT 0x00010000 /* Protect locked areas */
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#endif /* _WRS_SUPPORT_CACHE_LOCK */
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#define C_FLG_ORDER_RV 0x00020000 /* Reverse calling order from */
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/* Primary, Secondary, Tertiary */
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/* when sub caches are */
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/* supportable by AIM */
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#define C_FLG_FORCE 0x10000000 /* Top level API must call */
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/* this directly, this forces a*/
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/* passthrough to the architecture */
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/* defined routine */
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/* Flags used within aimCacheLib.c */
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#define CACHE_IS_VTOP 0x00100000 /* Virt to Phys needed */
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#define CACHE_IS_PTOV 0x00200000 /* Phys to Virt needed */
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#define CACHE_IS_VIRTUAL 0x00400000 /* The cache op is virtual */
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#define CACHE_IS_PHYSICAL 0x00800000 /* The cache op is physical */
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#define CACHE_IS_INDEXED 0x01000000 /* The cache op is indexed */
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#define CACHE_IS_HARVARD 0x02000000
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#define CACHE_IS_UNIFIED 0x04000000
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#define CACHE_IS_MULTISIZE 0x08000000 /* Different line sizes */
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#define CACHE_MODE_MASK ( CACHE_IS_VIRTUAL | CACHE_IS_PHYSICAL | CACHE_IS_INDEXED)
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/* Typedefs Section */
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/*
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* enumeration of cache types
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* Note: The initial enumeration is to assure compatibility
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* with vxWorks 5.X
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*/
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typedef enum
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{
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CACHE_TYPE_I = _INSTRUCTION_CACHE, /* Instruction Cache */
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CACHE_TYPE_D = _DATA_CACHE, /* Data Cache */
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#ifdef _WRS_SUPPORT_CACHE_EXTRA
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CACHE_TYPE_B = _BRANCH_CACHE, /* Branch Cache */
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CACHE_TYPE_S, /* Secondary Cache */
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CACHE_TYPE_T, /* Tertiary Cache */
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CACHE_TYPE_IL, /* Instruction TLB Cache */
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CACHE_TYPE_DL, /* Data TLB Cache */
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CACHE_TYPE_A, /* Alternate Primary Cache */
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/* Xscale has a "mini-cache" */
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#endif /* _WRS_SUPPORT_CACHE_EXTRA */
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CACHE_TYPE_MAX_SUPPORTED
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}CACHETYPES;
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/* enumeration of Primitive functions */
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typedef enum
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{
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CACHE_OP_NOOP, /* NO OP */
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CACHE_OP_ENABLE, /* CACHENABLE() */
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CACHE_OP_DISABLE, /* CACHEDISABLE() */
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#ifdef _WRS_SUPPORT_CACHE_LOCK
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CACHE_OP_LOCK, /* CACHELOCK() */
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CACHE_OP_UNLOCK, /* CACHEUNLOCK() */
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#endif /* _WRS_SUPPORT_CACHE_LOCK */
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CACHE_OP_FLUSH, /* CACHEFLUSH() */
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CACHE_OP_INVALIDATE, /* CACHEINVALIDATE() */
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CACHE_OP_CLEAR, /* CACHECLEAR() */
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CACHE_OP_TEXTUPDATE, /* CACHETEXTUPDATE() */
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CACHE_OP_PIPEFLUSH, /* CACHEPIPEFLUSH() */
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#ifdef _WRS_SUPPORT_CACHE_XLATE
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CACHE_OP_DMAVIRTOPHYS, /* VIRTUAL-TO-PHYSICAL TRANSLATION */
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CACHE_OP_DMAPHYSTOVIRT, /* PHYSICAL-TO-VIRTUAL TRANSLATION */
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#endif /* _WRS_SUPPORT_CACHE_XLATE */
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#ifdef _WRS_SUPPORT_CACHE_EXTRA
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CACHE_OP_FENCE, /* Memory synchronization */
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CACHE_OP_PREFETCH, /* Prefetch a range of memory */
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#endif /* _WRS_SUPPORT_CACHE_EXTRA */
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#ifndef _WRS_CONFIG_MEM_ALLOT
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CACHE_OP_DMAMALLOC, /* Allocate a dma safe buffer */
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CACHE_OP_DMAFREE, /* Free buffer allocated via DMAMALLOC */
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#endif /* !_WRS_CONFIG_MEM_ALLOT */
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CACHE_OP_ISON, /* Is Cache On */
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#ifdef _WRS_SUPPORT_CACHE_EXTRA
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CACHE_OP_EXP_0, /* Architecture specific expansion */
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CACHE_OP_EXP_1,
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CACHE_OP_EXP_2,
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CACHE_OP_LAST = (CACHE_OP_EXP_2 + 3) /* This keeps _ALL functions */
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/* from overflowing the array */
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#else /* _WRS_SUPPORT_CACHE_EXTRA */
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CACHE_OP_LAST = (CACHE_OP_ISON + 3)
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#endif /* _WRS_SUPPORT_CACHE_EXTRA */
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} CACHE_OPS;
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/* cache Attributes structure */
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typedef struct cacheAttributes
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{
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CACHETYPES cacheType; /* One of CACHETYPES */
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UINT32 cacheModeDefault; /* copyback, writethrough, etc. */
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UINT32 cacheModeSupported;/* copyback, writethrough, etc. */
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UINT32 cacheSize; /* 0 for "not present" */
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UINT32 lineSize; /* in bytes */
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UINT32 lineStep; /* increment between cache lines */
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UINT32 numWays; /* number of way in the cache */
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UINT32 wayStep; /* increment between cache ways */
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UINT32 numSegs; /* number of segments in a segmented cache */
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UINT32 segStep; /* increment between segments */
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void * cacheBase; /* Index or displacement cache ops */
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} CACHEATTRIBUTES;
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/* Description of cache primitive */
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typedef struct cacheOp
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{
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UINT32 opType; /* From C_FLG defines */
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FUNCPTR opPtr; /* Pointer to the Primitive */
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} CACHEOP;
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/* Description of a cache or portion of a cache */
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typedef struct cachePrimitive
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{
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CACHEATTRIBUTES cacheAttr; /* This could be a pointer */
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CACHEOP cacheOps[CACHE_OP_LAST];
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}CACHEPRIMITIVE;
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/*
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* cacheConfig is the structure that encapsulates a CPU's
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* cache properties.
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*/
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typedef struct cacheConfig
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{
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UINT32 nCaches; /* Number of caches described in this struct */
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CACHEPRIMITIVE cachePrimitives[CACHE_TYPE_MAX_SUPPORTED];
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}CACHECONFIG;
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/* The following data elements are initialized and maintained */
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/* by the cache AIM based on the data passed to it via the */
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/* CACHECONFIG structure */
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/*
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* Cache attributes structure for use in cacheAimInfo.
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*/
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typedef struct cacheGlobalAttr
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{
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UINT32 cacheExists; /* Indicates that this entry in the array is valid */
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UINT32 cacheType; /* Type of cache, I,D */
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UINT32 cacheSize; /* Size in bytes of this cache */
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UINT32 cacheLineSize; /* Line size for this cache */
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UINT32 cacheModes; /* Modes supported by this cache */
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UINT32 cacheModeCurrent; /* Current mode of this cache */
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}CACHEGLOBALATTR;
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/*
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* Lock database structure.
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* Keeps track of locked areas, facilitating the protection of locked areas
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* from invalidates. The Lock database uses virtual addresses, a flat memory
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* model allows this.
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*
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* Dynamically allocated by the AIM for lock management.
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*/
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typedef struct cacheLockNode *lockNodePtr;
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typedef struct cacheLockNode
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{
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lockNodePtr pNext;
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lockNodePtr pPrev;
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UINT32 cacheLockStart;
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UINT32 cacheLockEnd;
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}CACHELOCKNODE;
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/* Globally visible array of attributes */
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extern CACHEGLOBALATTR cacheAimInfo[CACHE_TYPE_MAX_SUPPORTED];
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extern UINT32 cacheLineSize; /* Cache line size. Used for alignment */
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extern UINT32 cacheAddrAlign; /* Increment for address alignment */
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extern UINT32 cacheLineMask; /* Mask to align to a cache line */
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/* Forward Declarations */
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STATUS aimCacheInit ( CACHECONFIG * cacheConfig );
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCaimCacheLibh */
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