original files of m241

This commit is contained in:
neelimap
2026-07-30 11:19:44 +05:30
parent 170c2b3f3a
commit afc7070c1f
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/* am335xCan.h - definitions for AM335X based CAN controller */
/*
* Copyright (c) 2012, 2014 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01aug14,hcl add Altera Soc Gen 5 support
01a,30nov12,wqi written.
*/
/*
DESCRIPTION
This file contains definitions used only in am335xCan.c
and am335xCan_cfg.c
*/
#ifndef __INCam335xCanh
#define __INCam335xCanh
/* includes */
#include <dllLib.h>
#include <CAN/TiDCan.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* external WindNet CAN required functions */
/*
* Since all AM335X devices are internal to the processor, only one
* board can exist.
*/
#define MAX_NUM_AM335X_CAN_BOARDS (1)
#define BRD_NDX (0) /* only one board possible */
#ifdef ALT_DEV_BOARD_CYCLONE_V
# define INUM_MSG0 164 /* can0_mo_IRQ */
# define INUM_SYS0 163 /* can0_sts_IRQ */
# define INUM_ERR0 166 /* can0_ecc_uncorrected_IRQ */
# define INUM_MSG1 168 /* can1_mo_IRQ */
# define INUM_SYS1 167 /* can1_sts_IRQ */
# define INUM_ERR1 170 /* can1_ecc_uncorrected_IRQ */
#else
# define INUM_MSG0 52 /* DCAN0 interrupt0 */
# define INUM_SYS0 53 /* DCAN0 interrupt1 */
# define INUM_ERR0 54 /* DCAN0 Parity */
# define INUM_MSG1 55 /* DCAN1 interrupt0 */
# define INUM_SYS1 56 /* DCAN1 interrupt1 */
# define INUM_ERR1 57 /* DCAN1 Parity */
#endif /* ALT_DEV_BOARD_CYCLONE_V */
#define CFG_IMMR 0x80000000
#define MAX_FIFO_SIZE 32
/* the 1Mbps bitrate is the max bitrate */
#define AM335X_CAN_BTR_MAX 1000000
/* the time segment before the sample point */
#define AM335X_CAN_BTR_TSEG1 9
/* the time segment after the sample point */
#define AM335X_CAN_BTR_TSEG2 2
/* the synchronization jump width */
#define AM335X_CAN_BTR_SJW 1
/* the defalut bitrates */
#define AM335X_CAN_BTR_BRP_10K 200
#define AM335X_CAN_BTR_BRP_20K 100
#define AM335X_CAN_BTR_BRP_25K 80
#define AM335X_CAN_BTR_BRP_50K 40
#define AM335X_CAN_BTR_BRP_100K 20
#define AM335X_CAN_BTR_BRP_125K 16
#define AM335X_CAN_BTR_BRP_250K 8
#define AM335X_CAN_BTR_BRP_500K 4
#define AM335X_CAN_BTR_BRP_1M 2
/* typedefs */
/* we need an identifier for each individual AM335X controllers */
typedef enum
{
DCAN1_CTRL,
DCAN2_CTRL
}
DCAN_CTRL_ID;
typedef struct _dcan_fifo_
{
DL_NODE pNode;
UCHAR channelNum[MAX_FIFO_SIZE];
UCHAR bufferSize;
} DCAN_FIFO;
/*
* Define a type to record AM335X device instance.
* Used to pass BSP configuration data to WNCAN.
*/
typedef struct
{
DCAN_CTRL_ID DCANcontrollerId; /* AM335X controller Identifier. */
void * pDevBaseAddr; /* base address of AM335X device */
int intNummsg; /* interrupt number */
int intNumsys; /* interrupt number */
int intNumerr; /* interrupt number */
UINT32 freq; /* frequency */
UINT32 cfgOptions; /* config options */
UCHAR taChl; /* the number of all channels */
UCHAR rxChl; /* the number of receive channels */
UCHAR txChl; /* the number of transmission channels */
/* default bit timing setting */
UCHAR brp;
UCHAR sjw;
UCHAR tseg1;
UCHAR tseg2;
}
am335x_mscan_instance;
IMPORT STATUS am335xCan_init (am335x_mscan_instance * pDCANboardCfg);
IMPORT STATUS am335xCan_establishLinks (struct WNCAN_Device *);
IMPORT struct WNCAN_Device * am335xCan_open (UINT32, UINT32);
IMPORT STATUS am335xCan_close (struct WNCAN_Device *);
IMPORT STATUS CAN_FreeFifoRxChannel (struct WNCAN_Device *pDev,
UCHAR channelNum);
IMPORT STATUS CAN_SetupFifoRxChannel (struct WNCAN_Device *pDev,
UCHAR * channelNum, UCHAR size,
ULONG canID, BOOL ext,
WNCAN_IntType intSetting, long mask);
IMPORT BOOL am335x_cfgGet_inUse (UINT32 brdNdx);
IMPORT void am335x_cfgSet_inUse (UINT32 brdNdx, BOOL val);
IMPORT BOOL am335x_cfgGet_allocated (UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT void am335x_cfgSet_allocated (UINT32 brdNdx, UINT32 ctrlNdx,
BOOL val);
IMPORT struct WNCAN_Board * am335x_cfgGet_canBoardPtr (UINT32 brdNdx);
IMPORT struct WNCAN_Device * am335x_cfgGet_canDevicePtr
(UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT struct WNCAN_Controller * am335x_cfgGet_canControllerPtr
(UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT DCAN_DEV * am335x_cfgGet_mscanDevPtr
(UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT WNCAN_ChannelMode * am335x_cfgGet_chModePtr
(UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT WNCAN_ChannelMode * am335x_cfgGet_chTypePtr
(UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT UINT32 am335x_cfgGet_NumControllers (void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCam335xCanh */
@@ -0,0 +1,70 @@
/* can_tolapai.h - definitions for tolapai CAN controller */
/*
* Copyright (c) 2007 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01a,04Dec07,d_z written
*/
/*
DESCRIPTION
This file contains definitions used for tolapai CAN controller
*/
#ifndef _TOLAPAI_CAN_H_
#define _TOLAPAI_CAN_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* external WindNet CAN required functions */
/*
* Since all MSCAN devices are internal to the processor, only one
* board can exist.
*/
#define MAX_NUM_TOLAPAI_CAN_BOARDS (1)
#define MAX_NUM_TOLAPAI_CAN_CONTROLLERS (2)
#define BRD_NDX (0) /* Only one board possible */
#define PCI_CFG_POWER 0xe0
#define PCI_CFG_POWER_CTL 0x3
#define PCI_CFG_SMIA 0xe8
#define PCI_CFG_SMIA_SYS_INT (1<<0)
#define PCI_CFG_SMIA_PARITY_INT (1<<1)
struct tolapaiCan_DeviceEntry
{
BOOL inUse;
/* data types for the board */
struct WNCAN_Board canBoard;
/* data types for each controller on the board */
BOOL allocated [MAX_NUM_TOLAPAI_CAN_CONTROLLERS];
struct WNCAN_Device canDevice [MAX_NUM_TOLAPAI_CAN_CONTROLLERS];
struct WNCAN_Controller canController [MAX_NUM_TOLAPAI_CAN_CONTROLLERS];
can_os_t can_os [MAX_NUM_TOLAPAI_CAN_CONTROLLERS];
};
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _TOLAPAI_CAN_H_ */
@@ -0,0 +1,53 @@
/* esd_can_pc104_200.h - definitions for ESD CAN PC104/200 board */
/* Copyright 2001 Wind River Systems, Inc. */
/*
modification history
--------------------
20dec01, dnb written
*/
/*
DESCRIPTION
This file contains definitions used only in esd_can_pc104_200.c
and esd_can_pc104_200_cfg.c
*/
#ifndef ESD_CAN_PC104_200_H
#define ESD_CAN_PC104_200_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define ESD_CAN_PC104_200_MAX_CONTROLLERS (2)
struct ESD_CAN_PC104_200_DeviceEntry
{
ULONG ioAddress;
UINT irq;
BOOL inUse;
struct WNCAN_Device canDevice[ESD_CAN_PC104_200_MAX_CONTROLLERS];
struct WNCAN_Controller canControllerArray[ESD_CAN_PC104_200_MAX_CONTROLLERS];
struct WNCAN_Board canBoardArray[ESD_CAN_PC104_200_MAX_CONTROLLERS];
BOOL allocated[ESD_CAN_PC104_200_MAX_CONTROLLERS];
WNCAN_ChannelMode i82527chnMode[I82527_MAX_MSG_OBJ];
struct i82527ChipSpecific can82527;
WNCAN_ChannelMode sja1000chnMode[SJA1000_MAX_MSG_OBJ];
struct TxMsg txMsg;
};
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* ESD_CAN_PC104_200_H */
@@ -0,0 +1,54 @@
/* esd_pci_200.h - definitions for ESD PCI/200 board */
/* Copyright 2001 Wind River Systems, Inc. */
/*
modification history
--------------------
20dec01, dnb written
*/
/*
DESCRIPTION
This file contains definitions used only in esd_pci_200.
and esd_pci_200_cfg.c
*/
#ifndef ESD_PCI_200_H
#define ESD_PCI_200_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define ESD_PCI_200_MAX_CONTROLLERS (2)
struct ESD_PCI_200_ChannelData
{
WNCAN_ChannelMode sja1000chnMode[SJA1000_MAX_MSG_OBJ];
};
struct ESD_PCI_200_DeviceEntry
{
struct WNCAN_Device canDevice[ESD_PCI_200_MAX_CONTROLLERS];
struct ESD_PCI_200_ChannelData chData[ESD_PCI_200_MAX_CONTROLLERS];
struct WNCAN_Controller canControllerArray[ESD_PCI_200_MAX_CONTROLLERS];
struct WNCAN_Board canBoard;
struct TxMsg txMsg[ESD_PCI_200_MAX_CONTROLLERS];
int bus;
int dev;
int func;
BOOL inUse;
BOOL allocated[ESD_PCI_200_MAX_CONTROLLERS];
BOOL intConnect;
};
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* ESD_PCI_200_H */
@@ -0,0 +1,48 @@
/* m5282CAN.h - definitions for MCF5282 baords */
/* Copyright 2001 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,08apr04,lsg Modified for supporting WindNet CAN 1.3
01a,24sep03,eli support for MCF5282 (ColdFire) FlexCAN module
*/
/*
DESCRIPTION
This file contains the declarations and definitions that are used for
MCF5282 boards
*/
#ifndef _m5282CAN_H_
#define _m5282CAN_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/*Define the number of controllers on-board (or on-chip)*/
#define MAX_M5282_CAN_DEVICES 1
struct m5282CAN_DeviceEntry
{
BOOL inUse;
struct WNCAN_Device canDevice;
struct WNCAN_Controller canController;
struct WNCAN_Board canBoard;
struct canAccess canRegAccess;
BOOL allocated;
WNCAN_ChannelMode FlexCANchnMode[FLEXCAN_MAX_MSG_OBJ];
};
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _m5282CAN_H_ */
@@ -0,0 +1,97 @@
/* mpc5121eCan.h - definitions for MPC5121E based CAN controller */
/*
* Copyright (c) 2008 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01a,01dec08,x_f written
*/
/*
DESCRIPTION
This file contains definitions used only in mpc5121eCan.c
and mpc5121eCan_cfg.c
*/
#ifndef _MPC5121E_CAN_H_
#define _MPC5121E_CAN_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "CAN/motMsCan.h"
/* external WindNet CAN required functions */
/*
* Since all MSCAN devices are internal to the processor, only one
* board can exist.
*/
#define MAX_NUM_MPC5121E_CAN_BOARDS (1)
#define BRD_NDX (0) /* Only one board possible */
#define INUM_CAN1 12
#define INUM_CAN2 13
#define IV_CAN1 INUM_TO_IVEC (INUM_CAN1)
#define IV_CAN2 INUM_TO_IVEC (INUM_CAN2)
#define CFG_IMMR 0x80000000
/* We need an identifier for each individual MSCAN controllers */
typedef enum
{
MSCAN1_CTRL,
MSCAN2_CTRL
}
MSCAN_CTRL_ID;
/*
* Define a type to record MSCAN device instance.
* Used to pass BSP configuration data to WNCAN
*/
typedef struct
{
MSCAN_CTRL_ID MSCANcontrollerId; /* MSCAN controller Identifier. */
void * pDevBaseAddr; /* Base address of MSCAN device */
VOIDFUNCPTR * pIntVec; /* Interrupt vector */
int intNum; /* Interrupt number */
UINT32 clockSource; /* 0=Oscillator Clock, 1=IP Bus Clock */
UINT32 freq; /* frequency */
}
mpc5121e_mscan_instance;
/* Defined in mpc5121eCan.c */
IMPORT STATUS mpc5121eCan_init (mpc5121e_mscan_instance * pMSCANboardCfg);
IMPORT STATUS mpc5121eCan_establishLinks (struct WNCAN_Device *);
IMPORT struct WNCAN_Device * mpc5121eCan_open (UINT, UINT);
IMPORT STATUS mpc5121eCan_close (struct WNCAN_Device *);
/* Defined in mpc5121e_cfg.c */
IMPORT BOOL mpc5121e_cfgGet_inUse (UINT brdNdx);
IMPORT void mpc5121e_cfgSet_inUse (UINT brdNdx, BOOL val);
IMPORT BOOL mpc5121e_cfgGet_allocated (UINT brdNdx, UINT ctrlNdx);
IMPORT void mpc5121e_cfgSet_allocated (UINT brdNdx, UINT ctrlNdx, BOOL val);
IMPORT struct WNCAN_Board * mpc5121e_cfgGet_canBoardPtr (UINT brdNdx);
IMPORT struct WNCAN_Device * mpc5121e_cfgGet_canDevicePtr (UINT brdNdx, UINT ctrlNdx);
IMPORT struct WNCAN_Controller * mpc5121e_cfgGet_canControllerPtr (UINT brdNdx, UINT ctrlNdx);
IMPORT MSCAN_DEV * mpc5121e_cfgGet_mscanDevPtr (UINT brdNdx, UINT ctrlNdx);
IMPORT WNCAN_ChannelMode * mpc5121e_cfgGet_chModePtr (UINT brdNdx, UINT ctrlNdx);
IMPORT UINT32 mpc5121e_cfgGet_NumControllers (void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _MPC5121E_CAN_H_ */
@@ -0,0 +1,86 @@
/* mpc5200Can.h - definitions for MPC5200 based CAN controller */
/* Copyright 1984-2004 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
modification history
--------------------
01b,25jun04,bjn Adding extern "C" for CPP.
01a,23oct03,bjn written
*/
/*
DESCRIPTION
This file contains definitions used only in mpc5200Can.c
and mpc5200Can_cfg.c
*/
#ifndef _MPC5200_CAN_H_
#define _MPC5200_CAN_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "CAN/motMsCan.h"
/* external WindNet CAN required functions */
/*
* Since all MSCAN devices are internal to the processor, only one
* board can exist.
*/
#define MAX_NUM_MPC5200CAN_BOARDS (1)
#define BRD_NDX (0) /* Only one board possible */
/* We need an identifier for each individual MSCAN controllers */
typedef enum
{
MSCAN1_CTRL,
MSCAN2_CTRL
}
MSCAN_CTRL_ID;
/*
* Define a type to record MSCAN device instance.
* Used to pass BSP configuration data to WNCAN
*/
typedef struct
{
MSCAN_CTRL_ID MSCANcontrollerId; /* MSCAN controller Identifier. */
void * pDevBaseAddr; /* Base address of MSCAN device */
VOIDFUNCPTR * pIntVec; /* Interrupt vector */
int intNum; /* Interrupt number */
UINT32 clockSource; /* 0=Oscillator Clock, 1=IP Bus Clock */
UINT32 freq; /* frequency */
}
mpc5200_mscan_instance;
/* Defined in mpc5200Can.c */
IMPORT STATUS mpc5200Can_init (mpc5200_mscan_instance * pMSCANboardCfg);
IMPORT STATUS mpc5200Can_establishLinks (struct WNCAN_Device *);
IMPORT struct WNCAN_Device * mpc5200Can_open (UINT, UINT);
IMPORT STATUS mpc5200Can_close (struct WNCAN_Device *);
/* Defined in mpc5200_cfg.c */
IMPORT BOOL mpc5200_cfgGet_inUse (UINT brdNdx);
IMPORT void mpc5200_cfgSet_inUse (UINT brdNdx, BOOL val);
IMPORT BOOL mpc5200_cfgGet_allocated (UINT brdNdx, UINT ctrlNdx);
IMPORT void mpc5200_cfgSet_allocated (UINT brdNdx, UINT ctrlNdx, BOOL val);
IMPORT struct WNCAN_Board * mpc5200_cfgGet_canBoardPtr (UINT brdNdx);
IMPORT struct WNCAN_Device * mpc5200_cfgGet_canDevicePtr (UINT brdNdx, UINT ctrlNdx);
IMPORT struct WNCAN_Controller * mpc5200_cfgGet_canControllerPtr (UINT brdNdx, UINT ctrlNdx);
IMPORT MSCAN_DEV * mpc5200_cfgGet_mscanDevPtr (UINT brdNdx, UINT ctrlNdx);
IMPORT WNCAN_ChannelMode * mpc5200_cfgGet_chModePtr (UINT brdNdx, UINT ctrlNdx);
IMPORT UINT32 mpc5200_cfgGet_NumControllers (void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _MPC5200_CAN_H_ */
+47
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@@ -0,0 +1,47 @@
/* msmcan.h - definitions for MSMCAN PC104 board */
/* Copyright 2001 Wind River Systems, Inc. */
/*
modification history
--------------------
20dec01, dnb written
*/
/*
DESCRIPTION
This file contains definitions used only in msmcan_pc104.c
and msmcan_pc104_cfg.c
*/
#ifndef MSMCAN_H
#define MSMCAN_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define MSMCAN_PC104_MAX_CONTROLLERS (1)
struct MSMCAN_PC104_DeviceEntry
{
ULONG ioAddress;
UINT irq;
BOOL inUse;
struct WNCAN_Device canDevice;
struct WNCAN_Controller canController;
struct WNCAN_Board canBoard;
BOOL allocated;
WNCAN_ChannelMode i82527chnMode[I82527_MAX_MSG_OBJ];
struct i82527ChipSpecific can82527;
};
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* MSMCAN_H */
@@ -0,0 +1,46 @@
/* ppc5xxCAN.h - definitions for PPC5xx baords */
/* Copyright 2001 Wind River Systems, Inc. */
/*
modification history
--------------------
27dec01, lsg
*/
/*
DESCRIPTION
This file contains the declarations and definitions that are used for
PPC5xx boards
*/
#ifndef _ppc5xxCAN_H_
#define _ppc5xxCAN_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/*Define the number of controllers on-board (or on-chip)*/
#define PPC5XXCAN_MAX_CONTROLLERS (1)
struct ppc5xxCAN_DeviceEntry
{
BOOL inUse;
struct WNCAN_Device canDevice;
struct WNCAN_Controller canController;
struct WNCAN_Board canBoard;
struct canAccess canRegAccess;
BOOL allocated;
WNCAN_ChannelMode TouCANchnMode[TOUCAN_MAX_MSG_OBJ];
};
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif