original files of m241
This commit is contained in:
neelimap
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/* TiDCan.h - definitions for the Ti DCAN */
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/*
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* Copyright (c) 2012, 2014 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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25aug14,hcl fix Altera Soc Gen 5 channel number. (VXW6-83280)
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01a,30nov12,wqi written.
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*/
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/*
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DESCRIPTION
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This file contains the functions declarations, specific to the
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new CAN controller, that implement the interface defined
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in the wnCAN.h header file.
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*/
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#ifndef __INCtiDcanh
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#define __INCtiDcanh
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#include <vxWorks.h>
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#include <spinLockLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* max number of message objects for TI AM335X */
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#undef ALT_DEV_BOARD_CYCLONE_V
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#ifdef ALT_DEV_BOARD_CYCLONE_V
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# define TIDCAN_MAX_MSG_OBJ (128)
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#else
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# define TIDCAN_MAX_MSG_OBJ (64)
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#endif
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#define TI_CHN_VALID 0x01
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#define TI_CHN_INVALID 0x02
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/* CAN control register */
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#define TI_DCAN_CTL 0x00
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#define TI_DCAN_CTL_Init (1<<0)
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#define TI_DCAN_CTL_IE0 (1<<1)
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#define TI_DCAN_CTL_SIE (1<<2)
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#define TI_DCAN_CTL_EIE (1<<3)
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#define TI_DCAN_CTL_DAR (1<<5)
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#define TI_DCAN_CTL_CCE (1<<6)
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#define TI_DCAN_CTL_Test (1<<7)
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#define TI_DCAN_CTL_IDS (1<<8)
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#define TI_DCAN_CTL_ABO (1<<9)
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#define TI_DCAN_CTL_SWR (1<<15)
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#define TI_DCAN_CTL_InitDbg (1<<16)
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#define TI_DCAN_CTL_IE1 (1<<17)
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#define TI_DCAN_CTL_DE1 (1<<18)
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#define TI_DCAN_CTL_DE2 (1<<19)
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#define TI_DCAN_CTL_DE3 (1<<20)
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#define TI_DCAN_CTL_PDR (1<<24)
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#define TI_DCAN_CTL_WUBA (1<<25)
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#define TI_DCAN_CTL_PMD_E (0x5<<10)
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#define TI_DCAN_CTL_PMD_MASK (0xf<<10)
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/* error and status register */
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#define TI_DCAN_ES 0x04
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#define TI_DCAN_ES_PDA (1<<10)
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#define TI_DCAN_ES_WKUP (1<<9)
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#define TI_DCAN_ES_PER (1<<8)
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#define TI_DCAN_ES_BOFF (1<<7)
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#define TI_DCAN_ES_EWARN (1<<6)
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#define TI_DCAN_ES_EPASS (1<<5)
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#define TI_DCAN_ES_RXOK (1<<4)
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#define TI_DCAN_ES_TXOK (1<<3)
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/* last error code. */
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#define TI_DCAN_ES_LEC_MASK (7)
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#define TI_DCAN_ES_LEC_STUFF (1)
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#define TI_DCAN_ES_LEC_FORM (2)
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#define TI_DCAN_ES_LEC_ACK (3)
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#define TI_DCAN_ES_LEC_BIT1 (4)
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#define TI_DCAN_ES_LEC_BIT0 (5)
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#define TI_DCAN_ES_LEC_CRC (6)
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#define TI_DCAN_ES_LEC_OK (7)
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#define TI_DCAN_ERR_BOFF (1<<0) /* Bus-Off state */
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#define TI_DCAN_ERR_EPASS (1<<1) /* error passive state */
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#define TI_DCAN_ERR_PER (1<<2) /* parity error detected */
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#define TI_DCAN_ERR_EWARN (1<<3) /* warning state */
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#define TI_DCAN_ERR_PDA (1<<4) /* local power-down mode acknowledge */
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#define TI_DCAN_ERR_STUFF (1<<5) /* stuff error */
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#define TI_DCAN_ERR_FORM (1<<6) /* form error */
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#define TI_DCAN_ERR_ACK (1<<7) /* ack error */
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#define TI_DCAN_ERR_BIT1 (1<<8) /* bit1 error */
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#define TI_DCAN_ERR_BIT0 (1<<9) /* bit0 error */
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#define TI_DCAN_ERR_CRC (1<<10) /* CRC error */
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#define TI_DCAN_ERR_RXOK (1<<11) /* message Received */
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#define TI_DCAN_ERR_TXOK (1<<12) /* message Transmitted */
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#define TI_DCAN_ERR_WKUP (1<<13) /* wake up pending */
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/* bit timing register */
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#define TI_DCAN_BTR 0x0C
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#define TI_DCAN_BTR_BRP_SHIFT 0
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#define TI_DCAN_BTR_SJW_SHIFT 6
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#define TI_DCAN_BTR_TSeg1_SHIFT 8
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#define TI_DCAN_BTR_TSeg2_SHIFT 12
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#define DCAN_BTR_BRPE_SHIFT 16
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#define DCAN_BTR_BRP_MASK 0x3F
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#define DCAN_BTR_BRP_MASK_SHIFT 6
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#define DCAN_BTR_BRP_MAXVAL 0x3FF
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#define DCAN_BTR_BRP_SHIFT 0
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#define DCAN_BTR_SJW_MAXVAL 0x3
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#define DCAN_BTR_SJW_SHIFT 6
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#define DCAN_BTR_TSEG2_MAXVAL 0x7
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#define DCAN_BTR_TSEG2_SHIFT 12
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#define DCAN_BTR_TSEG1_MAXVAL 0xF
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#define DCAN_BTR_TSEG1_SHIFT 8
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/* the values stored in CANBTC should be adjusted */
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#define DCAN_BTR_ADJUST 1
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/* IFx Register */
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#define TI_DCAN_IF1CMD 0x100 /* IF1 Command Registers */
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#define TI_DCAN_IF2CMD 0x120 /* IF2 Command Registers */
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#define TI_DCAN_IFxCMD_WR (1<<23)
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#define TI_DCAN_IFxCMD_MASK (1<<22)
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#define TI_DCAN_IFxCMD_ARB (1<<21)
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#define TI_DCAN_IFxCMD_CTRL (1<<20)
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#define TI_DCAN_IFxCMD_CTRLINTPND (1<<19)
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#define TI_DCAN_IFxCMD_TXRNDT (1<<18)
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#define TI_DCAN_IFxCMD_DATAA (1<<17)
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#define TI_DCAN_IFxCMD_DATAB (1<<16)
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#define TI_DCAN_IFxCMD_BUSY (1<<15)
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#define TI_DCAN_IFxCMD_DMAACT (1<<14)
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#define TI_DCAN_IFxCMD_MSGNO_SHIFT 0
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#define TI_DCAN_IF1MSK 0x104
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#define TI_DCAN_IF2MSK 0x124
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#define TI_DCAN_IFxMSK_MXTD_SHIFT 31
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#define TI_DCAN_IFxMSK_MDIR_SHIFT 30
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#define TI_DCAN_IFxMSK_MASK_SHIFT 0
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#define TI_DCAN_IFxMSK_MXTD_MASK (((UINT32)1)<<31)
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#define TI_DCAN_IFxMSK_MDIR_MASK (1<<30)
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#define TI_DCAN_IFxMSK_MASK_MASK (0x1FFFFFFF)
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#define TI_DCAN_IFxMSK_NOEXT_MASK (0x1FFC0000)
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#define TI_DCAN_IF1ARB 0x108
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#define TI_DCAN_IF2ARB 0x128
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#define TI_DCAN_IFxARB_MSGVAL_SHIFT 31
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#define TI_DCAN_IFxARB_XTD_SHIFT 30
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#define TI_DCAN_IFxARB_DIR_SHIFT 29
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#define TI_DCAN_IFxARB_MSK_SHIFT_EXT 18
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#define TI_DCAN_IFxARB_MSK_SHIFT_STD 0
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#define TI_DCAN_IFxARB_MSGVAL_MASK (((UINT32)1)<<31)
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#define TI_DCAN_IFxARB_XTD_MASK (1<<30)
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#define TI_DCAN_IFxARB_DIR_MASK (1<<29)
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#define TI_DCAN_IFxARB_MSK_MASK_EXT (0x1FFFFFFF)
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#define TI_DCAN_IFxARB_MSK_MASK_STD (0x1FFC0000)
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#define TI_DCAN_IF1MCTL 0x10C
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#define TI_DCAN_IF2MCTL 0x12C
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#define TI_DCAN_IFxMCTL_NEWDAT_SHIFT 15
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#define TI_DCAN_IFxMCTL_MSGLST_SHIFT 14
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#define TI_DCAN_IFxMCTL_INTPND_SHIFT 13
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#define TI_DCAN_IFxMCTL_UMASK_SHIFT 12
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#define TI_DCAN_IFxMCTL_TXIE_SHIFT 11
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#define TI_DCAN_IFxMCTL_RXIE_SHIFT 10
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#define TI_DCAN_IFxMCTL_RMTEN_SHIFT 9
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#define TI_DCAN_IFxMCTL_TXRQST_SHIFT 8
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#define TI_DCAN_IFxMCTL_EOB_SHIFT 7
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#define TI_DCAN_IFxMCTL_DLC_SHIFT 0
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#define TI_DCAN_IFxMCTL_NEWDAT_MASK (1 << 15)
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#define TI_DCAN_IFxMCTL_MSGLST_MASK (1 << 14)
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#define TI_DCAN_IFxMCTL_INTPND_MASK (1 << 13)
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#define TI_DCAN_IFxMCTL_UMASK_MASK (1 << 12)
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#define TI_DCAN_IFxMCTL_TXIE_MASK (1 << 11)
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#define TI_DCAN_IFxMCTL_RXIE_MASK (1 << 10)
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#define TI_DCAN_IFxMCTL_RMTEN_MASK (1 << 9)
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#define TI_DCAN_IFxMCTL_TXRQST_MASK (1 << 8)
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#define TI_DCAN_IFxMCTL_EOB_MASK (1 << 7)
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#define TI_DCAN_IFxMCTL_DLC_MASK 0x0000000F
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#define TI_DCAN_IF1DATA 0x110 /* IF1 Data A Register */
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#define TI_DCAN_IF1DATB 0x114 /* IF1 Data B Register */
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#define TI_DCAN_IF2DATA 0x130 /* IF2 Data A Register */
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#define TI_DCAN_IF2DATB 0x134 /* IF2 Data B Register */
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#define TI_DCAN_INT 0x10 /* interrupt register */
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#define TI_DCAN_INT1_MASK (0x00FF0000)
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#define TI_DCAN_INT0_MASK (0x0000FFFF)
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#define TI_DCAN_ERRC 0x08 /* error counter register */
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#define TI_DCAN_TEST 0x14 /* test register */
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#define TI_DCAN_TEST_LBACK_SHIFT (1 << 4)
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#define TI_DCAN_TEST_EXLBACK_SHIFT (1 << 8)
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#define TI_DCAN_PERR 0x1C /* parity error code register */
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#define TI_DCAN_ABOTR 0x80 /* Auto-Bus-On time register */
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#define TI_DCAN_TXRQ_X 0x84 /* transmission request x register */
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#define TI_DCAN_TXRQ12 0x88 /* transmission request registers */
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#define TI_DCAN_TXRQ34 0x8C
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#define TI_DCAN_TXRQ56 0x90
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#define TI_DCAN_TXRQ78 0x94
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#define TI_DCAN_NWDAT_X 0x98 /* new data X register */
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#define TI_DCAN_NWDAT12 0x9C /* new data registers */
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#define TI_DCAN_NWDAT34 0xA0
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#define TI_DCAN_NWDAT56 0xA4
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#define TI_DCAN_NWDAT78 0xA8
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#define TI_DCAN_INTPND_X 0xAC /* interrupt pending x register */
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#define TI_DCAN_INTPND12 0xB0 /* interrupt pending registers */
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#define TI_DCAN_INTPND34 0xB4
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#define TI_DCAN_INTPND56 0xB8
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#define TI_DCAN_INTPND78 0xBC
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#define TI_DCAN_MSGVAL_X 0xC0 /* message valid X register */
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#define TI_DCAN_MSGVAL12 0xC4 /* message valid registers */
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#define TI_DCAN_MSGVAL34 0xC8
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#define TI_DCAN_MSGVAL56 0xCC
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#define TI_DCAN_MSGVAL78 0xD0
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#define TI_DCAN_INTMUX12 0xD8 /* interrupt multiplexer registers */
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#define TI_DCAN_INTMUX34 0xDC
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#define TI_DCAN_INTMUX56 0xE0
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#define TI_DCAN_INTMUX78 0xE4
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#define TI_DCAN_IF3OBS 0x140 /* IF3 observation register */
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#define TI_DCAN_IF3MSK 0x144 /* IF3 mask register */
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#define TI_DCAN_IF3ARB 0x148 /* IF3 arbitration register */
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#define TI_DCAN_IF3MCTL 0x14C /* IF3 message control register */
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#define TI_DCAN_IF3DATA 0x150 /* IF3 data A register */
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#define TI_DCAN_IF3DATB 0x154 /* IF3 data B register */
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#define TI_DCAN_IF3UPD12 0x160 /* IF3 update enable registers */
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#define TI_DCAN_IF3UPD34 0x164
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#define TI_DCAN_IF3UPD56 0x168
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#define TI_DCAN_IF3UPD78 0x16C
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#define TI_DCAN_TIOC 0x1E0 /* CAN TX IO control register */
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#define TI_DCAN_RT_TX_SHIFT (1<<3)
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#define TI_DCAN_RIOC 0x1E4 /* CAN RX IO control register */
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/* config options */
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#define TI_CFG_LOOPBACK 0x00000001 /* loopback mode enabled */
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#define TI_CFG_PARITY_ON 0x00000002 /* parity function enabled */
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#define TI_CFG_AUTO_BUS_ON 0x00000004 /* Auto-Bus-On enable */
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/* automatic retransmission of not successful messages enabled */
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#define TI_CFG_AUTO_RETRAN_ON 0x00000008
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#define TI_MSG_MAX_LEN 8
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#define TI_DCAN_SET 1
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#define TI_DCAN_CLR 0
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#define TI_DCAN_IFX_WRITE 0
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#define TI_DCAN_IFX_READ 1
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/* data structures for the controller */
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typedef struct dcanDev
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{
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/* register base for the AM335X DCAN */
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void * pDCANregs;
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/* global data for the AM335X device driver */
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UINT32 busErr;
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UINT32 busState;
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UINT32 intMask;
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UCHAR chanInt[TIDCAN_MAX_MSG_OBJ];
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/* Configuration options, set before TIDCAN_Init() is called */
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UINT32 cfgOptions;
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UINT32 intMsg;
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UINT32 intSys;
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UINT32 intErr;
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UINT32 freq;
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UCHAR rxChl;
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UCHAR txChl;
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UCHAR taChl;
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UCHAR ctrlID ;
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/* interrupt lock */
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spinlockIsr_t lock;
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}
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DCAN_DEV;
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/* used by channel allocate */
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struct _dcan_channeldata_
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{
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WNCAN_ChannelMode chnMode[TIDCAN_MAX_MSG_OBJ];
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WNCAN_ChannelType chnType[TIDCAN_MAX_MSG_OBJ];
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}
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DCAN_CHANNELDATA;
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typedef struct _am335x_dcanmsg_
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{
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/* IFX mask registers */
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UINT32 mxtd; /* mask extended mdentifier */
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UINT32 mdir; /* mask message direction */
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UINT32 msk; /* identifier mask */
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/* IFX arbitration registers */
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UINT32 msgVal; /* message valid */
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UINT32 xtd; /* extended identifier */
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UINT32 dir; /* message direction */
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/*
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* message identifier
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* [28:0] 29-bit identifier (extended frame)
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* [28:18] 11-bit identifier (standard frame).
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*
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*/
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UINT32 id;
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/* IFX message control registers */
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UINT32 newDat; /* new data */
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UINT32 msgLst; /* message lost */
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UINT32 intPnd; /* interrupt pending */
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UINT32 uMask; /* use acceptance mask */
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UINT32 txIE; /* transmit interrupt enable */
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UINT32 rxIE; /* receive interrupt enable */
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UINT32 rmtEn; /* remote enable */
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UINT32 txRqst; /* transmit request */
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UINT32 eob; /* end of the fifo buffer */
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UINT32 dlc; /* data length code */
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}
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AM335X_DCANMSG;
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/* cAN message object data structure */
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typedef struct _dcan_msg_obj_
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{
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UINT32 mask; /* IFX mask registers */
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UINT32 arbitration; /* IFX arbitration registers */
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UINT32 msgCtrl; /* IFX message control registers */
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/* IFx Data A and Data B Registers */
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UINT32 dataA; /* message dataA */
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UINT32 dataB; /* message dataB */
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AM335X_DCANMSG dcanmsg;
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} DCAN_MSG_OBJ;
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/* external globals for the controller */
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/* external functions for the controller */
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void DCAN_ISR (ULONG context);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __INCtiDcanh */
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@@ -0,0 +1,90 @@
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/* TiDCanOffsets.h - register offset definitions for the TI AM335X */
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||||
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||||
/*
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||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
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||||
modification history
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||||
--------------------
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||||
01a,30nov12,wqi written.
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||||
*/
|
||||
|
||||
/*
|
||||
* DESCRIPTION
|
||||
* This file contains the functions TI Scalable CAN register offsets.
|
||||
*/
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||||
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||||
#ifndef __INCtiDcanOffsetsh
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||||
#define __INCtiDcanOffsetsh
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||||
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||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define AM335X_OFF_DCAN_CTL TI_DCAN_CTL
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||||
#define AM335X_OFF_DCAN_ES_EOI TI_DCAN_ES
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||||
#define AM335X_OFF_DCAN_ERRC TI_DCAN_ERRC
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||||
#define AM335X_OFF_DCAN_BTR TI_DCAN_BTR
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#define AM335X_OFF_DCAN_INT TI_DCAN_INT
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#define AM335X_OFF_DCAN_TEST TI_DCAN_TEST
|
||||
#define AM335X_OFF_DCAN_PERR TI_DCAN_PERR
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||||
#define AM335X_OFF_DCAN_ABOTR TI_DCAN_ABOTR
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||||
#define AM335X_OFF_DCAN_TXRQ_X TI_DCAN_TXRQ_X
|
||||
#define AM335X_OFF_DCAN_TXRQ12 TI_DCAN_TXRQ12
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||||
#define AM335X_OFF_DCAN_TXRQ34 TI_DCAN_TXRQ34
|
||||
#define AM335X_OFF_DCAN_TXRQ56 TI_DCAN_TXRQ56
|
||||
#define AM335X_OFF_DCAN_TXRQ78 TI_DCAN_TXRQ78
|
||||
#define AM335X_OFF_DCAN_NWDAT_X TI_DCAN_NWDAT_X
|
||||
#define AM335X_OFF_DCAN_NWDAT12 TI_DCAN_NWDAT12
|
||||
#define AM335X_OFF_DCAN_NWDAT34 TI_DCAN_NWDAT34
|
||||
#define AM335X_OFF_DCAN_NWDAT56 TI_DCAN_NWDAT56
|
||||
#define AM335X_OFF_DCAN_NWDAT78 TI_DCAN_NWDAT78
|
||||
#define AM335X_OFF_DCAN_INTPND_X TI_DCAN_INTPND_X
|
||||
#define AM335X_OFF_DCAN_INTPND12 TI_DCAN_INTPND12
|
||||
#define AM335X_OFF_DCAN_INTPND34 TI_DCAN_INTPND34
|
||||
#define AM335X_OFF_DCAN_INTPND56 TI_DCAN_INTPND56
|
||||
#define AM335X_OFF_DCAN_INTPND78 TI_DCAN_INTPND78
|
||||
#define AM335X_OFF_DCAN_MSGVAL_X TI_DCAN_MSGVAL_X
|
||||
#define AM335X_OFF_DCAN_MSGVAL12 TI_DCAN_MSGVAL12
|
||||
#define AM335X_OFF_DCAN_MSGVAL34 TI_DCAN_MSGVAL34
|
||||
#define AM335X_OFF_DCAN_MSGVAL56 TI_DCAN_MSGVAL56
|
||||
#define AM335X_OFF_DCAN_MSGVAL78 TI_DCAN_MSGVAL78
|
||||
#define AM335X_OFF_DCAN_INTMUX12 TI_DCAN_INTMUX12
|
||||
#define AM335X_OFF_DCAN_INTMUX34 TI_DCAN_INTMUX34
|
||||
#define AM335X_OFF_DCAN_INTMUX56 TI_DCAN_INTMUX56
|
||||
#define AM335X_OFF_DCAN_INTMUX78 TI_DCAN_INTMUX78
|
||||
#define AM335X_OFF_DCAN_IF1CMD TI_DCAN_IF1CMD
|
||||
#define AM335X_OFF_DCAN_IF2CMD TI_DCAN_IF2CMD
|
||||
#define AM335X_OFF_DCAN_IF1MSK TI_DCAN_IF1MSK
|
||||
#define AM335X_OFF_DCAN_IF2MSK TI_DCAN_IF2MSK
|
||||
#define AM335X_OFF_DCAN_IF1ARB TI_DCAN_IF1ARB
|
||||
#define AM335X_OFF_DCAN_IF2ARB TI_DCAN_IF2ARB
|
||||
#define AM335X_OFF_DCAN_IF1MCTL TI_DCAN_IF1MCTL
|
||||
#define AM335X_OFF_DCAN_IF2MCTL TI_DCAN_IF2MCTL
|
||||
#define AM335X_OFF_DCAN_IF1DATA TI_DCAN_IF1DATA
|
||||
#define AM335X_OFF_DCAN_IF1DATB TI_DCAN_IF1DATB
|
||||
#define AM335X_OFF_DCAN_IF2DATA TI_DCAN_IF2DATA
|
||||
#define AM335X_OFF_DCAN_IF2DATB TI_DCAN_IF2DATB
|
||||
#define AM335X_OFF_DCAN_IF3OBS TI_DCAN_IF3OBS
|
||||
#define AM335X_OFF_DCAN_IF3MSK TI_DCAN_IF3MSK
|
||||
#define AM335X_OFF_DCAN_IF3ARB TI_DCAN_IF3ARB
|
||||
#define AM335X_OFF_DCAN_IF3MCTL TI_DCAN_IF3MCTL
|
||||
#define AM335X_OFF_DCAN_IF3DATA TI_DCAN_IF3DATA
|
||||
#define AM335X_OFF_DCAN_IF3DATB TI_DCAN_IF3DATB
|
||||
#define AM335X_OFF_DCAN_IF3UPD12 TI_DCAN_IF3UPD12
|
||||
#define AM335X_OFF_DCAN_IF3UPD34 TI_DCAN_IF3UPD34
|
||||
#define AM335X_OFF_DCAN_IF3UPD56 TI_DCAN_IF3UPD56
|
||||
#define AM335X_OFF_DCAN_IF3UPD78 TI_DCAN_IF3UPD78
|
||||
#define AM335X_OFF_DCAN_TIOC TI_DCAN_TIOC
|
||||
#define AM335X_OFF_DCAN_RIOC TI_DCAN_RIOC
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __INCtiDcanOffsetsh */
|
||||
@@ -0,0 +1,117 @@
|
||||
/* canBoard.h - CAN board definitions for Wind River CAN Common Interface */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2004, 2005, 2007, 2008, 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,30nov12,wqi Added am335x DCAN support
|
||||
01c,30dec08,x_f Added fsl_ads5121e CAN support
|
||||
01b,04dec07,d_z Added tolapai can support
|
||||
01a,28dec05,jb3 Add WNCAN_MCF5485 for spring release
|
||||
08apr04,lsg added support for ColdFire 5282 FlexCAN
|
||||
26feb04,bjn Added MPC5200 support
|
||||
09nov01,dnb modified for integration into Tornado
|
||||
12jul01,jac written
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains CAN board definitions for the
|
||||
CAN Common Interface.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef CAN_BOARD_H_
|
||||
#define CAN_BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* forward reference these datatypes */
|
||||
|
||||
typedef UINT WNCAN_BoardType;
|
||||
struct WNCAN_Device;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
_16MHZ = 16000000,
|
||||
_20MHZ = 20000000,
|
||||
_25MHZ = 25000000,
|
||||
_33MHZ = 33000000,
|
||||
_39MHZ = 39000000,
|
||||
_40MHZ = 40000000,
|
||||
_56MHZ = 56000000
|
||||
} XtalFreq;
|
||||
|
||||
|
||||
/* Datatypes used for board's linked list */
|
||||
typedef STATUS (*pfn_Board_EstabLnks_Type)(struct WNCAN_Device*);
|
||||
typedef STATUS (*pfn_Board_Close_Type)(struct WNCAN_Device*);
|
||||
typedef struct WNCAN_Device* (*pfn_Board_Open_Type)(UINT, UINT);
|
||||
typedef void (*pfn_Board_Show_Type)(void);
|
||||
|
||||
|
||||
/* The CAN_BoardType lists the available CAN boards or modules */
|
||||
#define WNCAN_NO_BOARD_ASSIGNED 0
|
||||
#define WNCAN_ESD_PC104_200 1
|
||||
#define WNCAN_ESD_PCI_200 2
|
||||
#define WNCAN_MSMCAN 3
|
||||
#define WNCAN_PPC5XX 4
|
||||
#define WNCAN_ADLINK_7841 5
|
||||
#define WNCAN_DAYTONA 6
|
||||
#define WNCAN_SHTAHOEAMANDA 7
|
||||
#define WNCAN_SHBISCAYNE 8
|
||||
#define WNCAN_MPC5200 9
|
||||
#define WNCAN_MCF5282 10
|
||||
#define WNCAN_MCF5485 11
|
||||
#define WNCAN_BRD_TOLAPAI 12
|
||||
#define WNCAN_MPC5121E 13
|
||||
#define WNCAN_AM335X 14
|
||||
|
||||
struct WNCAN_Board
|
||||
{
|
||||
void (*onEnterISR)(struct WNCAN_Device *);
|
||||
void (*onLeaveISR)(struct WNCAN_Device *);
|
||||
UCHAR (*canInByte)(struct WNCAN_Device *, unsigned int);
|
||||
void (*canOutByte)(struct WNCAN_Device *, unsigned int, UCHAR);
|
||||
void (*enableIrq)(struct WNCAN_Device *);
|
||||
void (*disableIrq)(struct WNCAN_Device *);
|
||||
|
||||
WNCAN_BoardType brdType;
|
||||
UINT irq;
|
||||
ULONG ioAddress;
|
||||
UINT32 bar0;
|
||||
UINT32 bar1;
|
||||
UINT32 bar2;
|
||||
XtalFreq xtalFreq;
|
||||
};
|
||||
|
||||
/* function prototypes */
|
||||
STATUS WNCAN_Board_establishLinks(struct WNCAN_Device *, WNCAN_BoardType);
|
||||
struct WNCAN_Device *WNCAN_Board_Open(UINT,UINT,UINT);
|
||||
void WNCAN_Board_Close(struct WNCAN_Device *);
|
||||
ULONG stringToUlong(const char *pStr);
|
||||
|
||||
|
||||
/* define access macros for use with the board's linked list */
|
||||
#define BOARDLL_INIT() FLL_Create(&g_BoardLLRoot)
|
||||
#define BOARDLL_ADD(n) FLL_Add(&g_BoardLLRoot, n)
|
||||
#define BOARDLL_GET(key) ((BoardLLNode*)FLL_Find(&g_BoardLLRoot, key))
|
||||
#define BOARDLL_FIRST() ((BoardLLNode*)FLL_FirstNode(&g_BoardLLRoot))
|
||||
#define BOARDLL_NEXT(n) ((BoardLLNode*)FLL_NextNode(n))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* CAN_BOARD_H_ */
|
||||
@@ -0,0 +1,90 @@
|
||||
/* canController.h - CAN controller definitions for Wind River CAN Common Interface */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2004, 2007, 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,30nov12,wqi Added am335x DCAN support
|
||||
01a,04dec07,d_z Added tolapai can support
|
||||
08apr04,lsg added FlexCAN related macros
|
||||
26feb04,bjn Added MPC5200 support
|
||||
26dec01,lsg added TOUCAN (PPC5xx) related macros
|
||||
09nov01,dnb modified for integration into Tornado
|
||||
12jul01,jac written
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains CAN controller definitions for the
|
||||
CAN Common Interface.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef CAN_CONTROLLER_H_
|
||||
#define CAN_CONTROLLER_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
struct WNCAN_Device;
|
||||
typedef UINT WNCAN_ControllerType;
|
||||
|
||||
/* Datatypes used for controller's linked list */
|
||||
typedef void (*pfn_Ctrlr_EstabLnks_Type)(struct WNCAN_Device *pDev);
|
||||
|
||||
|
||||
/* The CAN_ControllerType lists the available controllers */
|
||||
#define WNCAN_I82527 1
|
||||
#define WNCAN_SJA1000 2
|
||||
#define WNCAN_TOUCAN 3
|
||||
#define WNCAN_MCP2510 4
|
||||
#define WNCAN_HCAN2 5
|
||||
#define WNCAN_MOTMSCAN 6
|
||||
#define WNCAN_FLEXCAN 7
|
||||
#define WNCAN_CTL_TOLAPAI 8
|
||||
#define WNCAN_TIDCAN 9
|
||||
|
||||
struct WNCAN_Controller
|
||||
{
|
||||
WNCAN_ControllerType ctrlType; /* type of controller */
|
||||
UCHAR ctrlID; /* handle identifier of this controller */
|
||||
UCHAR brp;
|
||||
UCHAR sjw;
|
||||
UCHAR tseg1;
|
||||
UCHAR tseg2;
|
||||
UCHAR samples;
|
||||
struct WNCAN_Device *pDev; /* pointer to parent CAN_Device structure */
|
||||
const UINT *chnType; /* number of ways a message buffer can be configured */
|
||||
UINT *chnMode; /* current way a message buffer is configured */
|
||||
UCHAR numChn; /* number of available channels */
|
||||
void *csData; /* pointer to chip-specific data */
|
||||
};
|
||||
|
||||
|
||||
/* function prototypes */
|
||||
STATUS WNCAN_Controller_establishLinks(struct WNCAN_Device *pDev,
|
||||
WNCAN_ControllerType ctrlType);
|
||||
|
||||
|
||||
/* define access macros for use with the controller's linked list */
|
||||
#define CONTROLLERLL_INIT() FLL_Create(&g_ControllerLLRoot)
|
||||
#define CONTROLLERLL_ADD(n) FLL_Add(&g_ControllerLLRoot, n)
|
||||
#define CONTROLLERLL_GET(key) ((ControllerLLNode*)FLL_Find(&g_ControllerLLRoot, key))
|
||||
#define CONTROLLERLL_FIRST() ((ControllerLLNode*)FLL_FirstNode(&g_ControllerLLRoot))
|
||||
#define CONTROLLERLL_NEXT(n) ((ControllerLLNode*)FLL_NextNode(n))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* CAN_CONTROLLER_H_ */
|
||||
@@ -0,0 +1,104 @@
|
||||
/* canFixedLL.h - WN-CAN fixed-node linked lists */
|
||||
|
||||
/* Copyright 2002 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
07nov02,rgp written
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
The file defines the fixed-node linked lists. A fixed-object linked list is
|
||||
a normal linked list, except that each node in the linked is statically allocated.
|
||||
Therefore, this list does not use any dynamic memory.
|
||||
|
||||
As a result, there may only be limited use of the linked lists.
|
||||
|
||||
In addition, since we want to use common code with what essentially
|
||||
amounts to sub-classes of the nodes (i.e. specific data for each
|
||||
separate linked list), define all data within this header file.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef CAN_FIXEDLL_H_
|
||||
#define CAN_FIXEDLL_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#include "CAN/wnCAN.h"
|
||||
#include "CAN/canBoard.h"
|
||||
#include "CAN/canController.h"
|
||||
|
||||
/* Define Common Fixed-Node Data Structure */
|
||||
typedef struct _fll_node
|
||||
{
|
||||
struct _fll_node *pNext; /* next node ptr */
|
||||
int key; /* identifying key value for each node */
|
||||
|
||||
/* define union for all uses of our linked list. This is effectively
|
||||
** our sub-classing of the data structure
|
||||
**/
|
||||
union
|
||||
{
|
||||
/* board's linked list data */
|
||||
struct
|
||||
{
|
||||
pfn_Board_EstabLnks_Type establinks_fn; /* establishlinks function */
|
||||
pfn_Board_Open_Type open_fn; /* open function */
|
||||
pfn_Board_Close_Type close_fn; /* close function */
|
||||
pfn_Board_Show_Type show_fn; /* show function */
|
||||
} boarddata;
|
||||
|
||||
/* controller's linked list data */
|
||||
struct {
|
||||
pfn_Ctrlr_EstabLnks_Type establinks_fn; /* establishlinks function */
|
||||
} controllerdata;
|
||||
|
||||
} nodedata;
|
||||
|
||||
} FLL_NodeType;
|
||||
|
||||
|
||||
/* define types for each of the supported lists */
|
||||
typedef FLL_NodeType BoardLLNode;
|
||||
typedef FLL_NodeType ControllerLLNode;
|
||||
|
||||
|
||||
/* define struct for an instance of the linked-list */
|
||||
typedef struct _fll_instance
|
||||
{
|
||||
FLL_NodeType *pFirst;
|
||||
} FLL_RootType;
|
||||
|
||||
|
||||
|
||||
/* Linked List APIs */
|
||||
void FLL_Create(FLL_RootType*);
|
||||
void FLL_Add(FLL_RootType*, FLL_NodeType*);
|
||||
FLL_NodeType *FLL_Find(FLL_RootType*, int key);
|
||||
|
||||
#define FLL_FirstNode(rootptr) ( (rootptr) ? (rootptr)->pFirst : NULL )
|
||||
#define FLL_NextNode(nodeptr) ( (nodeptr) ? (nodeptr)->pNext : NULL )
|
||||
|
||||
/***************************************************************************/
|
||||
/***************************************************************************/
|
||||
/***************************************************************************/
|
||||
/* due do the recursive includes of canboard,cancontroller and this file,
|
||||
** need to declare the extern'd global variables here becase the root type
|
||||
** is now fully resolved.
|
||||
*/
|
||||
extern FLL_RootType g_BoardLLRoot;
|
||||
extern FLL_RootType g_ControllerLLRoot;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* CAN_FIXEDLL_H_ */
|
||||
@@ -0,0 +1,102 @@
|
||||
/*****************************************************************************
|
||||
* %LICENSE_DUAL%
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2007 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.GPL.
|
||||
*
|
||||
* Contact Information:
|
||||
* Intel Corporation
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2007 Intel Corporation. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __CAN_FIFO_H__
|
||||
#define __CAN_FIFO_H__
|
||||
|
||||
/******************************************************************************
|
||||
* Check if FIFO is empty.
|
||||
*****************************************************************************/
|
||||
int can_fifo_empty(
|
||||
icp_can_handle_t handle);
|
||||
|
||||
/******************************************************************************
|
||||
* Check if FIFO is full.
|
||||
*****************************************************************************/
|
||||
int can_fifo_full(
|
||||
icp_can_handle_t handle);
|
||||
|
||||
/******************************************************************************
|
||||
* Create a CAN messsage FIFO of size specifified.
|
||||
*****************************************************************************/
|
||||
icp_can_handle_t can_fifo_create(
|
||||
unsigned int num_nodes);
|
||||
|
||||
/******************************************************************************
|
||||
* Delete the FIFO.
|
||||
*****************************************************************************/
|
||||
void can_fifo_destroy(
|
||||
icp_can_handle_t handle);
|
||||
|
||||
/******************************************************************************
|
||||
* Get the first element of the FIFO.
|
||||
*****************************************************************************/
|
||||
int can_fifo_get(
|
||||
icp_can_handle_t handle,
|
||||
icp_can_msg_t *msg);
|
||||
|
||||
/******************************************************************************
|
||||
* Put a message into the FIFO.
|
||||
*****************************************************************************/
|
||||
int can_fifo_put(
|
||||
icp_can_handle_t handle,
|
||||
icp_can_msg_t *msg);
|
||||
|
||||
#endif /* __CAN_FIFO_H__ */
|
||||
@@ -0,0 +1,218 @@
|
||||
/* flexcan.h - definitions for Flexcan on-chip controller for Windnet CAN Interface */
|
||||
|
||||
/* Copyright 2001 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,20may05,lsg Added workaround for chip bug for incorrect 32 bit accesses
|
||||
of FlexCAN registers. This affects Filter register setting
|
||||
01b,08apr04,lsg modified to support WindNet CAN 1.3
|
||||
01a,24sep03,eli support for MCF5282 (ColdFire) FlexCAN module
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains the declarations and definitions that comprise the
|
||||
register definitions and other macros for use with Windnet CAN Interface.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _FLEXCAN_H_
|
||||
#define _FLEXCAN_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
/* Internal Memory Map Assignments
|
||||
*
|
||||
* This is the internal message sructure as used by the
|
||||
* CAN device driver source code. The user never uses this structure
|
||||
*/
|
||||
|
||||
typedef struct _flexcanChannel_ {
|
||||
volatile unsigned short Control;
|
||||
volatile unsigned short Id;
|
||||
volatile unsigned short Id2_OR_TimeStamp;
|
||||
volatile unsigned char Data[8];
|
||||
volatile unsigned short No_use;
|
||||
|
||||
} FlexCAN_StandardMsgType;
|
||||
|
||||
#define FLEXCAN_INACTIVE_BUFFER 0x0000
|
||||
#define FLEXCAN_BUFFER_READY_TO_RX 0x0040
|
||||
#define FLEXCAN_BUFFER_FULL 0x0020
|
||||
#define FLEXCAN_BUFFER_OVERRUN 0x0060
|
||||
#define FLEXCAN_BUFFER_BUSY 0x0010
|
||||
|
||||
#define FLEXCAN_TX_NOT_READY 0x0080
|
||||
#define FLEXCAN_TX 0x00c0
|
||||
#define FLEXCAN_RESPONSE_TO_REMOTE 0x00a0
|
||||
|
||||
#define FLEXCAN_REGS_BASE 0x001c0000
|
||||
#define FLEXCAN_BUFFERS_BASE 0x001c0080
|
||||
#define FLEXCAN_LBUF_LOWEST_ID_FIRST 0
|
||||
#define FLEXCAN_TSYNC_ENABLE 1
|
||||
#define FLEXCAN_MAX_MSG_OBJ 16
|
||||
#define FLEXCAN_REG_MAX_OFFSET 0x080
|
||||
#define FLEXCAN_BUF_MAX_OFFSET 0x180
|
||||
|
||||
#define FLEXCAN_NUM_INT_SRCS 19
|
||||
#define FLEXCAN_INT_SRC_MIN_NUM 8
|
||||
#define FLEXCAN_INT_SRC_MAX_NUM 26
|
||||
/*****************************************************************************
|
||||
* Register offsets
|
||||
*/
|
||||
|
||||
typedef struct _flexcan_
|
||||
{
|
||||
volatile unsigned short can_MCR; /* Module Configuration Register */
|
||||
volatile unsigned short can_res1;
|
||||
volatile unsigned short can_res2;
|
||||
volatile unsigned char can_CR0;
|
||||
volatile unsigned char can_CR1;
|
||||
volatile unsigned char can_PRESDIV;
|
||||
volatile unsigned char can_CR2;
|
||||
volatile unsigned short can_TIMER;
|
||||
volatile unsigned short can_res3[2];
|
||||
volatile unsigned short can_RxGlobalMask_hi;
|
||||
volatile unsigned short can_RxGlobalMask_lo;
|
||||
volatile unsigned short can_RxBuff14Mask_hi;
|
||||
volatile unsigned short can_RxBuff14Mask_lo;
|
||||
volatile unsigned short can_RxBuff15Mask_hi;
|
||||
volatile unsigned short can_RxBuff15Mask_lo;
|
||||
volatile unsigned short can_res4[2];
|
||||
volatile unsigned short can_ESTAT;
|
||||
volatile unsigned short can_IMASK;
|
||||
volatile unsigned short can_IFLAG;
|
||||
volatile unsigned char can_RxECTR;
|
||||
volatile unsigned char can_TxECTR;
|
||||
} _FlexCAN; /* 384 bytes total */
|
||||
|
||||
/* Module Configuration Register */
|
||||
|
||||
#define FLEXCAN_STOP 0x8000 /* Disable FlexCAN clocks */
|
||||
#define FLEXCAN_FRZ 0x4000 /* FlexCAN enabled to enter debug mode */
|
||||
#define FLEXCAN_HALT 0x1000 /* FlexCAN enters debug mode */
|
||||
#define FLEXCAN_NOTRDY 0x0800 /* FlexCAN is in low-power stop or debug mode */
|
||||
#define FLEXCAN_WAKEMSK 0x0400 /* wakeup interrupt is enabled */
|
||||
#define FLEXCAN_SOFTRST 0x0200 /* soft reset cycle initiated/completed */
|
||||
#define FLEXCAN_FRZACK 0x0100 /* FlexCAN has entered/exited debug mode */
|
||||
#define FLEXCAN_SUPV 0x0080 /* supervisor/user mode */
|
||||
#define FLEXCAN_SELFWAKE 0x0040 /* self wake enabled */
|
||||
#define FLEXCAN_APS 0x0020 /* auto-power save */
|
||||
#define FLEXCAN_STOPACK 0x0010 /* FlexCAN entered low-power stop mode */
|
||||
|
||||
/* Control Register 0 */
|
||||
|
||||
#define FLEXCAN_BOFFMSK 0x80 /* bus off interrupt enable */
|
||||
#define FLEXCAN_ERRMSK 0x40 /* error interrupt enable */
|
||||
#define FLEXCAN_RXMODE 0x04 /* CANRX pin polarity */
|
||||
#define FLEXCAN_TXMODE_POS 0x00 /* CANTX pin positive polarity */
|
||||
#define FLEXCAN_TXMODE_NEG 0x01 /* CANTX pin negative polarity */
|
||||
#define FLEXCAN_TXMODE_OPD 0x02 /* CANTX pin open drain */
|
||||
|
||||
/* Control Register 1 */
|
||||
|
||||
#define FLEXCAN_SAMP 0x80 /* sampling mode */
|
||||
#define FLEXCAN_TSYNC 0x20 /* timer synchronize mode */
|
||||
#define FLEXCAN_LBUF 0x10 /* lowest buffer transmitted first */
|
||||
#define FLEXCAN_LOM 0x08 /* listen only mode */
|
||||
#define FLEXCAN_PROPSEG 0x07 /* propagation segment time mask */
|
||||
|
||||
/* Error and Status Register (ESTAT) */
|
||||
|
||||
#define FLEXCAN_BITERR 0xc000 /* transmit bit error */
|
||||
#define FLEXCAN_ACKERR 0x2000 /* acknowlege error */
|
||||
#define FLEXCAN_CRCERR 0x1000 /* crc error */
|
||||
#define FLEXCAN_FORMERR 0x0800 /* message format error */
|
||||
#define FLEXCAN_STUFFERR 0x0400 /* bit stuff error */
|
||||
#define FLEXCAN_TXWARN 0x0200 /* transmit error status */
|
||||
#define FLEXCAN_RXWARN 0x0100 /* receive error status */
|
||||
#define FLEXCAN_FCS 0x0030 /* fault confinment state */
|
||||
#define FLEXCAN_ERR_ACTIVE 0x0000 /* confinment state ERROR ACTIVE */
|
||||
#define FLEXCAN_ERR_PASSIVE 0x0010 /* confinment state ERROR PASSIVE */
|
||||
#define FLEXCAN_BOFFINT 0x0004 /* bus off interrupt */
|
||||
#define FLEXCAN_ERRINT 0x0002 /* error interrupt */
|
||||
#define FLEXCAN_WAKEINT 0x0001 /* wake interrupt */
|
||||
|
||||
typedef struct _flexcanBuffers_
|
||||
{
|
||||
volatile FlexCAN_StandardMsgType can_MSG[FLEXCAN_MAX_MSG_OBJ];
|
||||
}_FlexCANbuffers;
|
||||
|
||||
typedef volatile _FlexCAN *FlexCAN;
|
||||
typedef volatile _FlexCANbuffers *FlexCANBuf;
|
||||
|
||||
struct canAccess
|
||||
{
|
||||
FlexCAN pFlexCanRegs;
|
||||
FlexCANBuf pFlexCanBufs;
|
||||
UCHAR FlexcanPropseg;
|
||||
USHORT FlexCANAutoPowersSave;
|
||||
USHORT FlexCANSupv;
|
||||
UCHAR FlexCANTimerSync;
|
||||
UCHAR FlexCANLBuf;
|
||||
UCHAR FlexCANSrcIcrVal[FLEXCAN_NUM_INT_SRCS];
|
||||
};
|
||||
|
||||
/* table of regbases for each can channel */
|
||||
extern FlexCAN pFlexCanRegsBaseAdr[];
|
||||
extern FlexCANBuf pFlexCanBufsBaseAdr[];
|
||||
|
||||
/*
|
||||
* Formatting identifier bits
|
||||
*/
|
||||
#define FLEXCAN_ID_BITS_28TO18 0xFFE0
|
||||
#define FLEXCAN_ID_BITS_17TO15 0x7
|
||||
#define FLEXCAN_IDE_EXT 0x0008
|
||||
|
||||
#define FLEXCAN_M28TO18 0xffe00000
|
||||
#define FLEXCAN_M17TO0 0x001ffff8
|
||||
|
||||
extern const UINT g_FLEXCANchnType[FLEXCAN_MAX_MSG_OBJ];
|
||||
|
||||
#define FLEXCAN_RXBUF14_MASK 14
|
||||
#define FLEXCAN_RXBUF15_MASK 15
|
||||
|
||||
/*----------------------------------------------
|
||||
* duplicate macros, added in ppcFlexcan.h after
|
||||
* CAN api update
|
||||
*
|
||||
* FLEXCAN Control Register (FLEXCAN_CR2)
|
||||
*(MSB)0 1 2 3 4 5 6 7
|
||||
* --------------------------------------------
|
||||
*| RJW | PSEG | PSEG2 |
|
||||
*| | | |
|
||||
* --------------------------------------------
|
||||
*/
|
||||
|
||||
#ifndef FLEXCAN_RJW
|
||||
#define FLEXCAN_RJW 0xC0
|
||||
#endif
|
||||
|
||||
#ifndef FLEXCAN_PSEG
|
||||
#define FLEXCAN_PSEG 0x38
|
||||
#endif
|
||||
|
||||
#ifndef FLEXCAN_PSEG2
|
||||
#define FLEXCAN_PSEG2 0x07
|
||||
#endif
|
||||
|
||||
#ifndef FLEXCAN_GetM17TO0
|
||||
#define FLEXCAN_GetM17TO0 0x0007fffe
|
||||
#endif
|
||||
|
||||
/*------------------------------------------------*/
|
||||
|
||||
void FlexCAN_registration(void);
|
||||
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FLEXCAN_H_ */
|
||||
@@ -0,0 +1,81 @@
|
||||
/* flexcanOffsets.h - definitions for Flexcan for WNCAN Interface */
|
||||
|
||||
/* Copyright 2001 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,08jun04,lsg created
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains the FlexCAN register offsets
|
||||
|
||||
|
||||
*/
|
||||
#ifndef FLEXCAN_OFFSETS_H_
|
||||
#define FLEXCAN_OFFSETS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Register offsets
|
||||
*/
|
||||
|
||||
#define FLEXCAN_MCR_OFFSET 0x0
|
||||
#define FLEXCAN_CR0_OFFSET 0x6
|
||||
#define FLEXCAN_CR1_OFFSET 0x7
|
||||
#define FLEXCAN_PRESDIV_OFFSET 0x8
|
||||
#define FLEXCAN_CR2_OFFSET 0x9
|
||||
#define FLEXCAN_TIMER_OFFSET 0xA
|
||||
#define FLEXCAN_RXGLOBALMASK_OFFSET 0x10
|
||||
#define FLEXCAN_RXBUFF14MASK_OFFSET 0x14
|
||||
#define FLEXCAN_RXBUFF15MASK_OFFSET 0x18
|
||||
#define FLEXCAN_ESTAT_OFFSET 0x20
|
||||
#define FLEXCAN_IMASK_OFFSET 0x22
|
||||
#define FLEXCAN_IFLAG_OFFSET 0x24
|
||||
#define FLEXCAN_RXECTR_OFFSET 0x26
|
||||
#define FLEXCAN_TXECTR_OFFSET 0x27
|
||||
#define FLEXCAN_REG_MAX_OFFSET 0x28
|
||||
|
||||
#define FLEXCAN_BUFF0_OFFSET 0x80
|
||||
#define FLEXCAN_BUFF1_OFFSET 0x90
|
||||
#define FLEXCAN_BUFF2_OFFSET 0xA0
|
||||
#define FLEXCAN_BUFF3_OFFSET 0xB0
|
||||
#define FLEXCAN_BUFF4_OFFSET 0xC0
|
||||
#define FLEXCAN_BUFF5_OFFSET 0xD0
|
||||
#define FLEXCAN_BUFF6_OFFSET 0xE0
|
||||
#define FLEXCAN_BUFF7_OFFSET 0xF0
|
||||
#define FLEXCAN_BUFF8_OFFSET 0x100
|
||||
#define FLEXCAN_BUFF9_OFFSET 0x110
|
||||
#define FLEXCAN_BUFF10_OFFSET 0x120
|
||||
#define FLEXCAN_BUFF11_OFFSET 0x130
|
||||
#define FLEXCAN_BUFF12_OFFSET 0x140
|
||||
#define FLEXCAN_BUFF13_OFFSET 0x150
|
||||
#define FLEXCAN_BUFF14_OFFSET 0x160
|
||||
#define FLEXCAN_BUFF15_OFFSET 0x170
|
||||
#define FLEXCAN_BUF_MAX_OFFSET 0x280
|
||||
|
||||
#define TOUCAN_BUFF_CTRLSTAT_OFFSET 0
|
||||
#define TOUCAN_BUFF_IDHI_OFFSET 2
|
||||
#define TOUCAN_BUFF_IDLO_OFFSET 4
|
||||
#define TOUCAN_BUFF_DATA0_OFFSET 6
|
||||
#define TOUCAN_BUFF_DATA1_OFFSET 7
|
||||
#define TOUCAN_BUFF_DATA2_OFFSET 8
|
||||
#define TOUCAN_BUFF_DATA3_OFFSET 9
|
||||
#define TOUCAN_BUFF_DATA4_OFFSET 0xa
|
||||
#define TOUCAN_BUFF_DATA5_OFFSET 0xb
|
||||
#define TOUCAN_BUFF_DATA6_OFFSET 0xc
|
||||
#define TOUCAN_BUFF_DATA7_OFFSET 0xd
|
||||
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FLEXCAN_OFFSETS_H_ */
|
||||
@@ -0,0 +1,84 @@
|
||||
/* hcan_2.h - Hitachi CAN v2 header file */
|
||||
|
||||
/* Copyright 2002 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,29mar05,lsg Fix capitalization in include
|
||||
12Nov02, rgp written
|
||||
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _HCAN2_H_
|
||||
#define _HCAN2_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#include <CAN/wnCAN.h>
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/** constants regarding the HCAN controller **/
|
||||
/***********************************************************************/
|
||||
|
||||
#define HCAN2_MAX_MSG_OBJ 32
|
||||
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/** data structures for the HCAN controller **/
|
||||
/***********************************************************************/
|
||||
struct HCan2_ChannelData
|
||||
{
|
||||
WNCAN_ChannelMode chnMode[HCAN2_MAX_MSG_OBJ];
|
||||
};
|
||||
|
||||
|
||||
/* data placed into the csData of the channel datastructure */
|
||||
typedef struct _ta_ctrlrdata
|
||||
{
|
||||
void *regbase; /* register base address */
|
||||
|
||||
/* since this controller can exist either on-chip or part
|
||||
** of the Tahoe-Amanda, those boards will have different
|
||||
** ways to sleep and wake the clock associated with the
|
||||
** controller. Thus, provide for functions that are board
|
||||
** specific, to wake and sleep, enable,disable
|
||||
**/
|
||||
int wake_sleep_value; /* value to pass to wake/sleep fn */
|
||||
|
||||
/* board's wake and sleep functions */
|
||||
STATUS (*wakefn)(int);
|
||||
STATUS (*sleepfn)(int);
|
||||
|
||||
/* board's IRQ enable/disable functions */
|
||||
void (*enableirqfn)(struct WNCAN_Device *);
|
||||
void (*disableirqfn)(struct WNCAN_Device *);
|
||||
|
||||
|
||||
} HCan2_PvtCtrlrData;
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/** external globals for the controller **/
|
||||
/***********************************************************************/
|
||||
extern const WNCAN_ChannelType g_hcan2chnType[HCAN2_MAX_MSG_OBJ];
|
||||
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/** external functions for the controller **/
|
||||
/***********************************************************************/
|
||||
void HCan2_registration(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
|
||||
#endif /* _HCAN2_H_ */
|
||||
@@ -0,0 +1,126 @@
|
||||
/* hcan2Offsets.h */
|
||||
|
||||
/* Copyright 2002 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
Description: Supply offsets and macros for use with te register
|
||||
access APIs.
|
||||
|
||||
|
||||
modification history
|
||||
--------------------
|
||||
12nov02,rgp written
|
||||
*/
|
||||
|
||||
|
||||
#ifndef HCAN2_OFFSETS_H_
|
||||
#define HCAN2_OFFSETS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/********************************/
|
||||
/* controller registers offsets */
|
||||
/********************************/
|
||||
#define HCAN2_MCR_OFFSET 0x00
|
||||
#define HCAN2_GSR_OFFSET 0x02
|
||||
#define HCAN2_BCR1_OFFSET 0x04
|
||||
#define HCAN2_BCR0_OFFSET 0x06
|
||||
#define HCAN2_IRR_OFFSET 0x08
|
||||
#define HCAN2_IMM_OFFSET 0x0A
|
||||
#define HCAN2_ERRCTNRS_OFFSET 0x0C
|
||||
#define HCAN2_TXPR1_OFFSET 0x20
|
||||
#define HCAN2_TXPR0_OFFSET 0x22
|
||||
#define HCAN2_TXCR1_OFFSET 0x28
|
||||
#define HCAN2_TXCR0_OFFSET 0x2A
|
||||
#define HCAN2_TXACK1_OFFSET 0x30
|
||||
#define HCAN2_TXACK0_OFFSET 0x32
|
||||
#define HCAN2_ABACK1_OFFSET 0x38
|
||||
#define HCAN2_ABACK0_OFFSET 0x3A
|
||||
#define HCAN2_RXPR1_OFFSET 0x40
|
||||
#define HCAN2_RXPR0_OFFSET 0x42
|
||||
#define HCAN2_RFPR1_OFFSET 0x48
|
||||
#define HCAN2_RFPR0_OFFSET 0x4A
|
||||
#define HCAN2_MBIMR1_OFFSET 0x50
|
||||
#define HCAN2_MBIMR0_OFFSET 0x52
|
||||
#define HCAN2_UMSR1_OFFSET 0x58
|
||||
#define HCAN2_UMSR0_OFFSET 0x5A
|
||||
#define HCAN2_TCNTR_OFFSET 0x80
|
||||
#define HCAN2_TCR_OFFSET 0x82
|
||||
#define HCAN2_TSR_OFFSET 0x84
|
||||
#define HCAN2_TDCR_OFFSET 0x86
|
||||
#define HCAN2_LOSR_OFFSET 0x88
|
||||
#define HCAN2_ICR0CC_OFFSET 0x8A
|
||||
#define HCAN2_ICR0TM_OFFSET 0x8C
|
||||
#define HCAN2_ICR1_OFFSET 0x8E
|
||||
#define HCAN2_TCMR0_OFFSET 0x90
|
||||
#define HCAN2_TCMR1_OFFSET 0x92
|
||||
#define HCAN2_TCMR2_OFFSET 0x94
|
||||
#define HCAN2_CCR_OFFSET 0x96
|
||||
#define HCAN2_CMAX_OFFSET 0x98
|
||||
#define HCAN2_TMR_OFFSET 0x9A
|
||||
|
||||
#define HCAN2_ENDOFREGISTERS 0x9C
|
||||
|
||||
|
||||
/************************/
|
||||
/* mailbox offsets */
|
||||
/************************/
|
||||
#define HCAN2_MB0_OFFSET 0x100
|
||||
#define HCAN2_MB1_OFFSET 0x120
|
||||
#define HCAN2_MB2_OFFSET 0x140
|
||||
#define HCAN2_MB3_OFFSET 0x160
|
||||
#define HCAN2_MB4_OFFSET 0x180
|
||||
#define HCAN2_MB5_OFFSET 0x1A0
|
||||
#define HCAN2_MB6_OFFSET 0x1C0
|
||||
#define HCAN2_MB7_OFFSET 0x1E0
|
||||
#define HCAN2_MB8_OFFSET 0x200
|
||||
#define HCAN2_MB9_OFFSET 0x220
|
||||
#define HCAN2_MB10_OFFSET 0x240
|
||||
#define HCAN2_MB11_OFFSET 0x260
|
||||
#define HCAN2_MB12_OFFSET 0x280
|
||||
#define HCAN2_MB13_OFFSET 0x2A0
|
||||
#define HCAN2_MB14_OFFSET 0x2C0
|
||||
#define HCAN2_MB15_OFFSET 0x2E0
|
||||
#define HCAN2_MB16_OFFSET 0x300
|
||||
#define HCAN2_MB17_OFFSET 0x320
|
||||
#define HCAN2_MB18_OFFSET 0x340
|
||||
#define HCAN2_MB19_OFFSET 0x360
|
||||
#define HCAN2_MB20_OFFSET 0x380
|
||||
#define HCAN2_MB21_OFFSET 0x3A0
|
||||
#define HCAN2_MB22_OFFSET 0x3C0
|
||||
#define HCAN2_MB23_OFFSET 0x3E0
|
||||
#define HCAN2_MB24_OFFSET 0x400
|
||||
#define HCAN2_MB25_OFFSET 0x420
|
||||
#define HCAN2_MB26_OFFSET 0x440
|
||||
#define HCAN2_MB27_OFFSET 0x460
|
||||
#define HCAN2_MB28_OFFSET 0x480
|
||||
#define HCAN2_MB29_OFFSET 0x4A0
|
||||
#define HCAN2_MB30_OFFSET 0x4C0
|
||||
#define HCAN2_MB31_OFFSET 0x4E0
|
||||
|
||||
#define HCAN2_ENDOFMAILBOXES 0x500
|
||||
|
||||
/*************************/
|
||||
/* mailbox field offsets */
|
||||
/*************************/
|
||||
#define HCAN2_MBCTRL0_OFFSET 0x00
|
||||
#define HCAN2_MBCTRL1_OFFSET 0x02
|
||||
#define HCAN2_MBCTRL2_OFFSET 0x04
|
||||
#define HCAN2_MBTIMESTAMP_OFFSET 0x06
|
||||
#define HCAN2_MBDATA01_OFFSET 0x08
|
||||
#define HCAN2_MBDATA23_OFFSET 0x0A
|
||||
#define HCAN2_MBDATA45_OFFSET 0x0C
|
||||
#define HCAN2_MBDATA67_OFFSET 0x0E
|
||||
#define HCAN2_MBFILTER0_OFFSET 0x10
|
||||
#define HCAN2_MBFILTER1_OFFSET 0x12
|
||||
|
||||
#define HCAN2_ENDOFMAILBOXFIELDS 0x14
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,77 @@
|
||||
/* i82527.h - definitions for Intel 82527 CAN Controller */
|
||||
|
||||
/* Copyright 2001 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
09nov01,dnb modified for integration into Tornado
|
||||
12jul01,jac written
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains the functions declarations, specific to the
|
||||
Intel 82527 CAN controller, that implement the interface defined
|
||||
in the wnCAN.h header file.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _I82527_H_
|
||||
#define _I82527_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
/* max number of message objects for i82527 */
|
||||
#define I82527_MAX_MSG_OBJ 15
|
||||
|
||||
/* bit constants */
|
||||
#define I82527_B_INIT 0x01 /* is 1 after reset or busoff, must be set to 0 1st time */
|
||||
#define I82527_B_IE 0x02 /* interrupt enable, must be 1 for using msg obj int's */
|
||||
#define I82527_B_SIE 0x04 /* status interrupt enable, can be 0 */
|
||||
#define I82527_B_EIE 0x08 /* Error interrupt enable, can be 0 */
|
||||
#define I82527_B_CCE 0x40 /* config change enable, must be 0 for accessing cfg reg's*/
|
||||
|
||||
/* status register */
|
||||
#define I82527_B_LEC0 0x01
|
||||
#define I82527_B_LEC1 0x02
|
||||
#define I82527_B_LEC2 0x04
|
||||
#define I82527_B_TXOK 0x08
|
||||
#define I82527_B_RXOK 0x10
|
||||
#define I82527_B_WAKE 0x20
|
||||
#define I82527_B_WARN 0x40 /* read-only, must be 0 for bus transfer */
|
||||
#define I82527_B_BOFF 0x80 /* read-only, must be 0 for bus transfer */
|
||||
|
||||
/* CPU interface register */
|
||||
#define I82527_B_CEN 0x01
|
||||
#define I82527_B_MUX 0x04
|
||||
#define I82527_B_SLEEP 0x08
|
||||
#define I82527_B_PWD 0x10
|
||||
#define I82527_B_DMC 0x20
|
||||
#define I82527_B_DSC 0x40
|
||||
#define I82527_B_RSTST 0x80
|
||||
|
||||
struct i82527ChipSpecific
|
||||
{
|
||||
BOOL busOffInt;
|
||||
BOOL wakeUpInt;
|
||||
BOOL errorInt;
|
||||
};
|
||||
|
||||
|
||||
extern const UINT g_i82527chnType[I82527_MAX_MSG_OBJ];
|
||||
|
||||
void i82527_registration(void);
|
||||
void i82527ISR(ULONG context);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _I82527_H_ */
|
||||
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
i82527Offsets.h - register offset definitions for
|
||||
Intel 82527 CAN Controller
|
||||
|
||||
Copyright 2001 Wind River Systems, Inc.
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
29may02,lsg modified for CAN driver update
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains the functions i82527 register offsets
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _I82527_OFFSETS_H_
|
||||
#define _I82527_OFFSETS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#define I82527_R_CTRL 0
|
||||
#define I82527_R_SR 1
|
||||
#define I82527_R_INFR 2
|
||||
#define I82527_R_HSR 4
|
||||
#define I82527_R_GMS 6
|
||||
#define I82527_R_GME 8
|
||||
#define I82527_R_M15M 0x0C
|
||||
#define I82527_R_CLKO 0x1F
|
||||
#define I82527_R_BCR 0x2F
|
||||
#define I82527_R_BTR0 0x3F
|
||||
#define I82527_R_BTR1 0x4F
|
||||
#define I82527_R_INT 0x5F
|
||||
#define I82527_R_P1C 0x9F
|
||||
#define I82527_R_P2C 0xAF
|
||||
#define I82527_R_P1I 0xBF
|
||||
#define I82527_R_P2I 0xCF
|
||||
#define I82527_R_P1O 0xDF
|
||||
#define I82527_R_P2O 0xEF
|
||||
#define I82527_R_SRA 0xFF
|
||||
|
||||
#define I82527_MAX_OFFSET 0x100
|
||||
|
||||
#define I82527_R_RCV 0xF0
|
||||
#define I82527_R_XMT 0x10
|
||||
|
||||
/* Register Offsets */
|
||||
#define I82527_OFFS_MSG 0x10 /* message address offset */
|
||||
#define I82527_OFFS_DATA 0x07 /* message offset for data bytes */
|
||||
#define I82527_OFFS_CTRL0 0x00 /* first message control register */
|
||||
#define I82527_OFFS_CTRL1 0x01 /* second message control register */
|
||||
#define I82527_OFFS_ARBIT 0x02 /* message arbitration register for setting the id*/
|
||||
#define I82527_OFFS_MCR 0x06 /* message configuration register */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /*_I82527_OFFSETS_H_*/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,397 @@
|
||||
/*****************************************************************************
|
||||
* %LICENSE_DUAL%
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2007 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.GPL.
|
||||
*
|
||||
* Contact Information:
|
||||
* Intel Corporation
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2007 Intel Corporation. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/**
|
||||
*****************************************************************************
|
||||
* @file icp_can_regs.h
|
||||
*
|
||||
* @defgroup icp_CanAcc_Regs Registers for CAN I/O Unit.
|
||||
*
|
||||
* @description
|
||||
* This file contains the defition of the CAN device memory
|
||||
* mapped registers.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ICP_CAN_REGS_H__
|
||||
#define __ICP_CAN_REGS_H__
|
||||
|
||||
/*****************************************************************************
|
||||
* Device characteristics
|
||||
*****************************************************************************/
|
||||
#define MM_REG_SIZE 0x29c /**< All CAN regs */
|
||||
#define NUM_RX_BUFFS 16 /**< Num CAN Rx buffers */
|
||||
#define NUM_TX_BUFFS 8 /**< Num CAN Tx buffers */
|
||||
|
||||
/*****************************************************************************
|
||||
* Memory map offset definitions
|
||||
*****************************************************************************/
|
||||
#define MM_INTSTAT 0x000 /**< Interrupt status */
|
||||
#define MM_INTENBL 0x004 /**< Interrupt enables */
|
||||
#define MM_BUFFSTAT 0x008 /**< Buffer status */
|
||||
#define MM_ERRSTAT 0x00c /**< Error status */
|
||||
#define MM_CMD 0x010 /**< Command reg */
|
||||
#define MM_CFG 0x014 /**< Config reg */
|
||||
|
||||
#define MM_TX0 0x020 /**< Tx reg 0 */
|
||||
#define MM_TX1 0x030 /**< Tx reg 1 */
|
||||
#define MM_TX2 0x040 /**< Tx reg 2 */
|
||||
#define MM_TX3 0x050 /**< Tx reg 3 */
|
||||
#define MM_TX4 0x060 /**< Tx reg 4 */
|
||||
#define MM_TX5 0x070 /**< Tx reg 5 */
|
||||
#define MM_TX6 0x080 /**< Tx reg 6 */
|
||||
#define MM_TX7 0x090 /**< Tx reg 7 */
|
||||
|
||||
#define MM_RX0 0x0a0 /**< Rx reg 0 */
|
||||
#define MM_RX1 0x0c0 /**< Tx reg 1 */
|
||||
#define MM_RX2 0x0e0 /**< Tx reg 2 */
|
||||
#define MM_RX3 0x100 /**< Tx reg 3 */
|
||||
#define MM_RX4 0x120 /**< Tx reg 4 */
|
||||
#define MM_RX5 0x140 /**< Tx reg 5 */
|
||||
#define MM_RX6 0x160 /**< Tx reg 6 */
|
||||
#define MM_RX7 0x180 /**< Tx reg 7 */
|
||||
#define MM_RX8 0x1a0 /**< Tx reg 8 */
|
||||
#define MM_RX9 0x1c0 /**< Tx reg 9 */
|
||||
#define MM_RX10 0x1e0 /**< Tx reg 10 */
|
||||
#define MM_RX11 0x200 /**< Tx reg 11 */
|
||||
#define MM_RX12 0x220 /**< Tx reg 12 */
|
||||
#define MM_RX13 0x240 /**< Tx reg 13 */
|
||||
#define MM_RX14 0x260 /**< Tx reg 14 */
|
||||
#define MM_RX15 0x280 /**< Tx reg 15 */
|
||||
|
||||
/*
|
||||
* Tx message register offsets. These offsets corresponds
|
||||
* to offsets within each of the MM_TXx registers
|
||||
*/
|
||||
#define MM_TXCTL 0x00 /**< Tx control */
|
||||
#define MM_TXCMD 0x00 /**< Tx command */
|
||||
#define MM_TXID 0x04 /**< Tx ID */
|
||||
#define MM_TXDATAH 0x08 /**< Tx data high */
|
||||
#define MM_TXDATAL 0x0c /**< Tx data low */
|
||||
|
||||
/*
|
||||
* Rx message register offsets.These offsets corresponds
|
||||
* to offsets withing each of the MM_RXx registers
|
||||
*/
|
||||
#define MM_RXCTL 0x00 /**< Rx conrol */
|
||||
#define MM_RXCMD 0x00 /**< Rx command */
|
||||
#define MM_RXID 0x04 /**< Rx ID */
|
||||
#define MM_RXDATAH 0x08 /**< Rx data high */
|
||||
#define MM_RXDATAL 0x0c /**< Rx data low */
|
||||
#define MM_RXAMR 0x10 /**< Rx acceptance mask */
|
||||
#define MM_RXACR 0x14 /**< Rx acceptance control */
|
||||
#define MM_RXAMRDATA 0x18 /**< Rx AMR data */
|
||||
#define MM_RXACRDATA 0x1c /**< Rx ACR data */
|
||||
|
||||
/*****************************************************************************
|
||||
* Register mask and bit definitions
|
||||
*****************************************************************************/
|
||||
/* Interrupt Status Bits */
|
||||
#define MSK_IS_ARLOSS (1<<BIT_IS_ARLOSS) /**< Arbitration loss*/
|
||||
#define MSK_IS_OVRLOAD (1<<BIT_IS_OVRLOAD) /**< Overload */
|
||||
#define MSK_IS_BITERR (1<<BIT_IS_BITERR) /**< Bit error */
|
||||
#define MSK_IS_STUFFERR (1<<BIT_IS_STUFFERR) /**< Stuff error */
|
||||
#define MSK_IS_ACKERR (1<<BIT_IS_ACKERR) /**< ACK error */
|
||||
#define MSK_IS_FORMERR (1<<BIT_IS_FORMERR) /**< Form error */
|
||||
#define MSK_IS_CRCERR (1<<BIT_IS_CRCERR) /**< CRC error */
|
||||
#define MSK_IS_BUSOFF (1<<BIT_IS_BUSOFF) /**< Bus off */
|
||||
#define MSK_IS_RXMSGLOSS (1<<BIT_IS_RXMSGLOSS) /**< Rx msg loss */
|
||||
#define MSK_IS_TXMSG (1<<BIT_IS_TXMSG) /**< Tx msg */
|
||||
#define MSK_IS_RXMSG (1<<BIT_IS_RXMSG) /**< Rx msg */
|
||||
|
||||
#define BIT_IS_ARLOSS 2
|
||||
#define BIT_IS_OVRLOAD 3
|
||||
#define BIT_IS_BITERR 4
|
||||
#define BIT_IS_STUFFERR 5
|
||||
#define BIT_IS_ACKERR 6
|
||||
#define BIT_IS_FORMERR 7
|
||||
#define BIT_IS_CRCERR 8
|
||||
#define BIT_IS_BUSOFF 9
|
||||
#define BIT_IS_RXMSGLOSS 10
|
||||
#define BIT_IS_TXMSG 11
|
||||
#define BIT_IS_RXMSG 12
|
||||
|
||||
/* Interrupt enable register */
|
||||
#define MSK_IE_INTENBL (1<<BIT_IE_INTENBL) /**< Ints Enabled */
|
||||
#define MSK_IE_ARLOSS (1<<BIT_IE_ARLOSS) /**< Arbitration loss*/
|
||||
#define MSK_IE_OVRLOAD (1<<BIT_IE_OVRLOAD) /**< Overload */
|
||||
#define MSK_IE_BITERR (1<<BIT_IE_BITERR) /**< Bit error */
|
||||
#define MSK_IE_STUFFERR (1<<BIT_IE_STUFFERR) /**< Stuff error */
|
||||
#define MSK_IE_ACKERR (1<<BIT_IE_ACKERR) /**< ACK error */
|
||||
#define MSK_IE_FORMERR (1<<BIT_IE_FORMERR) /**< Form error */
|
||||
#define MSK_IE_CRCERR (1<<BIT_IE_CRCERR) /**< CRC error */
|
||||
#define MSK_IE_BUSOFF (1<<BIT_IE_BUSOFF) /**< Bus off */
|
||||
#define MSK_IE_RXMSGLOSS (1<<BIT_IE_RXMSGLOSS) /**< Rx msg loss */
|
||||
#define MSK_IE_TXMSG (1<<BIT_IE_TXMSG) /**< Tx msg */
|
||||
#define MSK_IE_RXMSG (1<<BIT_IE_RXMSG) /**< Rx msg */
|
||||
|
||||
#define MSK_IE_ALL 0x1ffd /**< Enable all ints */
|
||||
#define MSK_IE_ERR 0x07fc /**< Enable all errs */
|
||||
|
||||
#define BIT_IE_INTENBL 0
|
||||
#define BIT_IE_ARLOSS 2
|
||||
#define BIT_IE_OVRLOAD 3
|
||||
#define BIT_IE_BITERR 4
|
||||
#define BIT_IE_STUFFERR 5
|
||||
#define BIT_IE_ACKERR 6
|
||||
#define BIT_IE_FORMERR 7
|
||||
#define BIT_IE_CRCERR 8
|
||||
#define BIT_IE_BUSOFF 9
|
||||
#define BIT_IE_RXMSGLOSS 10
|
||||
#define BIT_IE_TXMSG 11
|
||||
#define BIT_IE_RXMSG 12
|
||||
|
||||
/* Buffer status indicators */
|
||||
#define MSK_BS_RXMSG0 (1<<BIT_BS_RXMSG0) /**< Rx msg 0 */
|
||||
#define MSK_BS_RXMSG1 (1<<BIT_BS_RXMSG1) /**< Rx msg 1 */
|
||||
#define MSK_BS_RXMSG2 (1<<BIT_BS_RXMSG2) /**< Rx msg 2 */
|
||||
#define MSK_BS_RXMSG3 (1<<BIT_BS_RXMSG3) /**< Rx msg 3 */
|
||||
#define MSK_BS_RXMSG4 (1<<BIT_BS_RXMSG4) /**< Rx msg 4 */
|
||||
#define MSK_BS_RXMSG5 (1<<BIT_BS_RXMSG5) /**< Rx msg 5 */
|
||||
#define MSK_BS_RXMSG6 (1<<BIT_BS_RXMSG6) /**< Rx msg 6 */
|
||||
#define MSK_BS_RXMSG7 (1<<BIT_BS_RXMSG7) /**< Rx msg 7 */
|
||||
#define MSK_BS_RXMSG8 (1<<BIT_BS_RXMSG8) /**< Rx msg 8 */
|
||||
#define MSK_BS_RXMSG9 (1<<BIT_BS_RXMSG9) /**< Rx msg 9 */
|
||||
#define MSK_BS_RXMSG10 (1<<BIT_BS_RXMSG10) /**< Rx msg 10 */
|
||||
#define MSK_BS_RXMSG11 (1<<BIT_BS_RXMSG11) /**< Rx msg 11 */
|
||||
#define MSK_BS_RXMSG12 (1<<BIT_BS_RXMSG12) /**< Rx msg 12 */
|
||||
#define MSK_BS_RXMSG13 (1<<BIT_BS_RXMSG13) /**< Rx msg 13 */
|
||||
#define MSK_BS_RXMSG14 (1<<BIT_BS_RXMSG14) /**< Rx msg 14 */
|
||||
#define MSK_BS_RXMSG15 (1<<BIT_BS_RXMSG15) /**< Rx msg 15 */
|
||||
|
||||
#define MSK_BS_RXALL 0x0000FFFF /**< All Rx msg bufs */
|
||||
|
||||
/* Transmit msg buffers statuses */
|
||||
#define MSK_BS_TXMSG0 (1<<BIT_BS_TXMSG0) /**< Tx msg 0 */
|
||||
#define MSK_BS_TXMSG1 (1<<BIT_BS_TXMSG1) /**< Tx msg 1 */
|
||||
#define MSK_BS_TXMSG2 (1<<BIT_BS_TXMSG2) /**< Tx msg 2 */
|
||||
#define MSK_BS_TXMSG3 (1<<BIT_BS_TXMSG3) /**< Tx msg 3 */
|
||||
#define MSK_BS_TXMSG4 (1<<BIT_BS_TXMSG4) /**< Tx msg 4 */
|
||||
#define MSK_BS_TXMSG5 (1<<BIT_BS_TXMSG5) /**< Tx msg 5 */
|
||||
#define MSK_BS_TXMSG6 (1<<BIT_BS_TXMSG6) /**< Tx msg 6 */
|
||||
#define MSK_BS_TXMSG7 (1<<BIT_BS_TXMSG7) /**< Tx msg 7 */
|
||||
|
||||
#define MSK_BS_TXALL 0x00FF0000 /**< All Tx msg bufs */
|
||||
|
||||
#define BIT_BS_RXMSG0 0
|
||||
#define BIT_BS_RXMSG1 1
|
||||
#define BIT_BS_RXMSG2 2
|
||||
#define BIT_BS_RXMSG3 3
|
||||
#define BIT_BS_RXMSG4 4
|
||||
#define BIT_BS_RXMSG5 5
|
||||
#define BIT_BS_RXMSG6 6
|
||||
#define BIT_BS_RXMSG7 7
|
||||
#define BIT_BS_RXMSG8 8
|
||||
#define BIT_BS_RXMSG9 9
|
||||
#define BIT_BS_RXMSG10 10
|
||||
#define BIT_BS_RXMSG11 11
|
||||
#define BIT_BS_RXMSG12 12
|
||||
#define BIT_BS_RXMSG13 13
|
||||
#define BIT_BS_RXMSG14 14
|
||||
#define BIT_BS_RXMSG15 15
|
||||
#define BIT_BS_TXMSG0 16
|
||||
#define BIT_BS_TXMSG1 17
|
||||
#define BIT_BS_TXMSG2 18
|
||||
#define BIT_BS_TXMSG3 19
|
||||
#define BIT_BS_TXMSG4 20
|
||||
#define BIT_BS_TXMSG5 21
|
||||
#define BIT_BS_TXMSG6 22
|
||||
#define BIT_BS_TXMSG7 23
|
||||
|
||||
/* Error status */
|
||||
#define MSK_ES_TXERRCNT (0xff<<BIT_ES_TXERRCNT) /**< Tx err count */
|
||||
#define MSK_ES_RXERRCNT (0xff<<BIT_ES_RXERRCNT) /**< Rx err count */
|
||||
#define MSK_ES_ERRSTAT (0x3<<BIT_ES_ERRSTAT) /**< Error state */
|
||||
#define MSK_ES_TXGTE96 (1<<BIT_ES_TXGTE96) /**< Tx >= 96 */
|
||||
#define MSK_ES_RXGTE96 (1<<BIT_ES_RXGTE96) /**< Rx >= 96 */
|
||||
|
||||
#define BIT_ES_TXERRCNT 0
|
||||
#define BIT_ES_RXERRCNT 8
|
||||
#define BIT_ES_ERRSTAT 16
|
||||
#define BIT_ES_TXGTE96 18
|
||||
#define BIT_ES_RXGTE96 19
|
||||
|
||||
/* Command */
|
||||
#define MSK_CMD_RUN (1<<BIT_CMD_RUN) /**< Run mode */
|
||||
#define MSK_CMD_LISTEN (1<<BIT_CMD_LISTEN) /**< Listen mode */
|
||||
|
||||
#define BIT_CMD_RUN 0
|
||||
#define BIT_CMD_LISTEN 1
|
||||
|
||||
/* Configuration */
|
||||
#define MSK_CFG_EDGE (1<<BIT_CFG_EDGE) /**< Edge trig */
|
||||
#define MSK_CFG_SMPL (1<<BIT_CFG_SMPL) /**< Sample mode */
|
||||
#define MSK_CFG_SJW (0x3<<BIT_CFG_SJW) /**< Synch jump width*/
|
||||
#define MSK_CFG_RSTRT (1<<BIT_CFG_RSTRT) /**< Auto restart */
|
||||
#define MSK_CFG_TSEG2 (0x7<<BIT_CFG_TSEG2) /**< Time segment 2 */
|
||||
#define MSK_CFG_TSEG1 (0xf<<BIT_CFG_TSEG1) /**< Time segment 1 */
|
||||
#define MSK_CFG_ARB (1<<BIT_CFG_ARB) /**< Arb: RR/Fixed */
|
||||
#define MSK_CFG_BITRATE (0x3fff<<BIT_CFG_BITRATE)/**< Prescaler */
|
||||
|
||||
#define BIT_CFG_EDGE 0
|
||||
#define BIT_CFG_SMPL 1
|
||||
#define BIT_CFG_SJW 2
|
||||
#define BIT_CFG_RSTRT 4
|
||||
#define BIT_CFG_TSEG2 5
|
||||
#define BIT_CFG_TSEG1 8
|
||||
#define BIT_CFG_ARB 12
|
||||
#define BIT_CFG_BITRATE 16
|
||||
|
||||
/* TxMessage control */
|
||||
#define MSK_TXCTL_INTENBL (1<<BIT_TXCTL_INTENBL) /**< Tx int enable */
|
||||
#define MSK_TXCTL_WPN0 (1<<BIT_TXCTL_WPN0) /**< WPN b[2] */
|
||||
#define MSK_TXCTL_DLC (0xf<<BIT_TXCTL_DLC) /**< Data length */
|
||||
#define MSK_TXCTL_IDE (1<<BIT_TXCTL_IDE) /**< Ext ID? */
|
||||
#define MSK_TXCTL_RTR (1<<BIT_TXCTL_RTR) /**< RTR? */
|
||||
#define MSK_TXCTL_WPN1 (1<<BIT_TXCTL_WPN1) /**< WPN b[21:16] */
|
||||
|
||||
#define BIT_TXCTL_INTENBL 2
|
||||
#define BIT_TXCTL_WPN0 3
|
||||
#define BIT_TXCTL_DLC 16
|
||||
#define BIT_TXCTL_IDE 20
|
||||
#define BIT_TXCTL_RTR 21
|
||||
#define BIT_TXCTL_WPN1 23
|
||||
|
||||
/* TxMessage command */
|
||||
#define MSK_TXCMD_REQ (1<<BIT_TXCMD_REQ) /**< Req tx */
|
||||
#define MSK_TXCMD_ABORT (1<<BIT_TXCMD_ABORT) /**< Req abort */
|
||||
#define MSK_TXCMD_WPN0 (1<<BIT_TXCMD_WPN0) /**< WPN 0 */
|
||||
#define MSK_TXCMD_WPN1 (1<<BIT_TXCMD_WPN1) /**< WPN 1 */
|
||||
|
||||
#define BIT_TXCMD_REQ 0
|
||||
#define BIT_TXCMD_ABORT 1
|
||||
#define BIT_TXCMD_WPN0 3
|
||||
#define BIT_TXCMD_WPN1 23
|
||||
|
||||
/* TxMessage ID */
|
||||
#define MSK_TXMSGIDS 0xfffffff8
|
||||
#define BIT_TXID 3
|
||||
#define BIT_TXID_UPPER 21
|
||||
|
||||
/* RxMessage control */
|
||||
#define MSK_RXCTL_BUFENBL (1<<BIT_RXCTL_BUFENBL) /**< Buf enabled */
|
||||
#define MSK_RXCTL_RTRRPLY (1<<BIT_RXCTL_RTRRPLY) /**< RTR msg */
|
||||
#define MSK_RXCTL_INTENBL (1<<BIT_RXCTL_INTENBL) /**< Int enabled */
|
||||
#define MSK_RXCTL_LNKFLG (1<<BIT_RXCTL_LNKFLG) /**< Linked buffer */
|
||||
#define MSK_RXCTL_WPNL (1<<BIT_RXCTL_WPNL) /**< WPN b[6:3] */
|
||||
#define MSK_RXCTL_DLC (0xf<<BIT_RXCTL_DLC) /**< Data len code */
|
||||
#define MSK_RXCTL_IDE (1<<BIT_RXCTL_IDE) /**< Ext ID? */
|
||||
#define MSK_RXCTL_RTR (1<<BIT_RXCTL_RTR) /**< RTR? */
|
||||
#define MSK_RXCTL_WPNH (1<<BIT_RXCTL_WPNH) /**< WPN b[21:16] */
|
||||
|
||||
#define BIT_RXCTL_BUFENBL 3
|
||||
#define BIT_RXCTL_RTRRPLY 4
|
||||
#define BIT_RXCTL_INTENBL 5
|
||||
#define BIT_RXCTL_LNKFLG 6
|
||||
#define BIT_RXCTL_WPNL 7
|
||||
#define BIT_RXCTL_DLC 16
|
||||
#define BIT_RXCTL_IDE 20
|
||||
#define BIT_RXCTL_RTR 21
|
||||
#define BIT_RXCTL_WPNH 23
|
||||
|
||||
/* RxMessage command */
|
||||
#define MSK_RXCMD_MSGAV (1<<BIT_RXCMD_MSGAV) /**< Msg avail */
|
||||
#define MSK_RXCMD_RTRRPLYPEND (1<<BIT_RXCMD_RTRRPLYPEND)/**< RTR reply pend*/
|
||||
#define MSK_RXCMD_RTRABORT (1<<BIT_RXCMD_RTRABORT) /**< RTR abort */
|
||||
#define MSK_RXCMD_WPNL (1<<BIT_RXCMD_WPNL) /**< WPNL */
|
||||
#define MSK_RXCMD_WPNH (1<<BIT_RXCMD_WPNH) /**< WPNH */
|
||||
|
||||
#define BIT_RXCMD_MSGAV 0
|
||||
#define BIT_RXCMD_RTRRPLYPEND 1
|
||||
#define BIT_RXCMD_RTRABORT 2
|
||||
#define BIT_RXCMD_WPNL 7
|
||||
#define BIT_RXCMD_WPNH 23
|
||||
|
||||
/* RxMessage ID */
|
||||
#define MSK_RXID (0x1fffffff<<BIT_RXMSGIDS)/**< Rx msg ID */
|
||||
#define BIT_RXID 3
|
||||
#define BIT_RXID_UPPER 21
|
||||
|
||||
/* RxMessage acceptance mask register */
|
||||
#define MSK_RXAMR_RTR (1<<BIT_RXAMR_RTR) /**< Rx AMR RTR */
|
||||
#define MSK_RXAMR_IDE (1<<BIT_RXAMR_IDE) /**< Rx AMR IDE? */
|
||||
#define MSK_RXAMR_ID (0x1fffffff<<BIT_RXAMR_ID) /**< Rx AMR ID */
|
||||
#define MSK_RXAMR_ID_UPPER (0x7ff<<BIT_RXAMR_ID_UPPER) /**< Rx AMR ID UPPER*/
|
||||
|
||||
#define BIT_RXAMR_RTR 1
|
||||
#define BIT_RXAMR_IDE 2
|
||||
#define BIT_RXAMR_ID 3
|
||||
#define BIT_RXAMR_ID_UPPER 21
|
||||
|
||||
/* RxMessage acceptance code register */
|
||||
#define MSK_RXACR_RTR (1<<BIT_RXACR_RTR) /**< Rx ACR RTR */
|
||||
#define MSK_RXACR_IDE (1<<BIT_RXACR_IDE) /**< Rx ACR IDE? */
|
||||
#define MSK_RXACR_ID (0x1fffffff<<BIT_RXACR_ID)/**< Rx ACR ID */
|
||||
#define MSK_RXACR_ID_UPPER (0x7ff<<BIT_RXACR_ID_UPPER) /**< Rx ACR ID UPPER*/
|
||||
|
||||
#define BIT_RXACR_RTR 1
|
||||
#define BIT_RXACR_IDE 2
|
||||
#define BIT_RXACR_ID 3
|
||||
#define BIT_RXACR_ID_UPPER 21
|
||||
|
||||
/* RxMessage acceptance mask register - data */
|
||||
#define MSK_RXAMRDATA 0x0000ffff /**< Rx AMR data */
|
||||
#define BIT_RXAMRDATA 0
|
||||
|
||||
/* RxMessage acceptance code register - data */
|
||||
#define MSK_RXACRDATA 0x0000ffff /**< Rx ACR data */
|
||||
#define BIT_RXACRDATA 0
|
||||
|
||||
#endif /* __ICP_CAN_REGS_H__ */
|
||||
@@ -0,0 +1,284 @@
|
||||
/*****************************************************************************
|
||||
* %LICENSE_DUAL%
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2007 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.GPL.
|
||||
*
|
||||
* Contact Information:
|
||||
* Intel Corporation
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2007 Intel Corporation. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/**
|
||||
*****************************************************************************
|
||||
* @file icp_can_types.h
|
||||
*
|
||||
* @defgroup icp_CanAcc_Types Public types for CAN I/O Unit.
|
||||
*
|
||||
* @description
|
||||
* These functions specify the hardware access function used to
|
||||
* maipulate the CAN device.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ICP_CAN_TYPES_H__
|
||||
#define __ICP_CAN_TYPES_H__
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* Message data length.
|
||||
* @description
|
||||
* Used to define the CAN message data length.
|
||||
*/
|
||||
#define ICP_CAN_MSG_DATA_LEN 8 /**< CAN Msg data length */
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* Debug output.
|
||||
* @description
|
||||
* Used to enable/disable deboug output.
|
||||
*/
|
||||
/*#define ICP_CAN_DEBUG 1*/ /**< CAN debug enable/disable */
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
/*
|
||||
******************************************************************************
|
||||
* Structures
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP handle
|
||||
* @description
|
||||
* This type uniquely identifies an ICP CAN object.
|
||||
*/
|
||||
typedef int icp_can_handle_t; /**< Generic handle type */
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Message
|
||||
* @description
|
||||
* This type defines a CAN messages.
|
||||
*/
|
||||
typedef struct icp_can_msg {
|
||||
unsigned short ide; /**< Standard/extended msg */
|
||||
unsigned int id; /**< 11 or 29 bit msg id */
|
||||
unsigned short dlc; /**< Size of data */
|
||||
unsigned char data[ICP_CAN_MSG_DATA_LEN];/**< Message pay load */
|
||||
unsigned short rtr; /**< RTR message */
|
||||
} icp_can_msg_t;
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Timing
|
||||
* @description
|
||||
* This type defines the parameters that define the CAN timing.
|
||||
*/
|
||||
typedef struct icp_can_timing {
|
||||
unsigned int bitrate; /**< Bitrate (kbps) */
|
||||
unsigned int cfg_bitrate; /**< Bitrate */
|
||||
unsigned int cfg_tseg1; /**< Tseg1 */
|
||||
unsigned int cfg_tseg2; /**< Tseg2 */
|
||||
unsigned int cfg_sjw; /**< Sync jump width */
|
||||
unsigned int smpl_mode; /**< Sampling mode */
|
||||
unsigned int edge_mode; /**< Edge R / D */
|
||||
} icp_can_timing_t;
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Error
|
||||
* @description
|
||||
* This type defines a CAN error stats.
|
||||
*/
|
||||
typedef struct icp_can_error {
|
||||
unsigned int rxgte96; /**< Rx err cnt >=96 */
|
||||
unsigned int txgte96; /**< Tx err cnt >=96 */
|
||||
unsigned int error_stat; /**< Error state of CAN node */
|
||||
/**< 00=error active (normal)*/
|
||||
/**< 01=error passive */
|
||||
/**< 1x=bus off */
|
||||
unsigned int rx_err_cnt; /**< Rx counter */
|
||||
unsigned int tx_err_cnt; /**< Tx counter */
|
||||
} icp_can_error_t;
|
||||
|
||||
/*
|
||||
******************************************************************************
|
||||
* Enumerated Types
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Filter
|
||||
* @description
|
||||
* This structure contains the filter information for ACR and AMR filter.
|
||||
*/
|
||||
typedef struct icp_can_acc_filter {
|
||||
unsigned int id; /**< ID */
|
||||
unsigned int id_ext; /**< Standard/extended ID? */
|
||||
unsigned int rtr; /**< RTR message */
|
||||
unsigned short data; /**< High byte pair */
|
||||
} icp_can_acc_filter_t;
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Rx Filter
|
||||
* @description
|
||||
* This structures describes the ACR and AMR filter for an Rx buffer.
|
||||
*/
|
||||
typedef struct icp_can_rx_filter {
|
||||
unsigned int num; /**< Filter number */
|
||||
icp_can_acc_filter_t amr; /**< Acceptance Mask Reg */
|
||||
icp_can_acc_filter_t acr; /**< Acceptance Control Reg */
|
||||
} icp_can_rx_filter_t;
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Active/Listen Mode
|
||||
* @description
|
||||
* Idententies the valid values for the Active/Listen mode.
|
||||
*/
|
||||
typedef enum {
|
||||
ICP_CAN_ACTIVE = 0, /**< R/w to/from the CAN */
|
||||
ICP_CAN_LISTEN /**< Only read from the CAN */
|
||||
} icp_can_listen_mode_t;
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Run/Stop Mode
|
||||
* @description
|
||||
* Identifies the valid values for the Run/Stop mode.
|
||||
*/
|
||||
typedef enum {
|
||||
ICP_CAN_STOP = 0, /**< CAN stopped */
|
||||
ICP_CAN_RUN /**< CAN running */
|
||||
} icp_can_run_mode_t;
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Arbitration Mode
|
||||
* @description
|
||||
* Identifies the valid values for the arbitration mode.
|
||||
*/
|
||||
typedef enum {
|
||||
ICP_CAN_ROUND_ROBIN = 0, /**< Equal priority */
|
||||
ICP_CAN_FIXED_PRIORITY /**< Buffer num priority */
|
||||
} icp_can_arbiter_t;
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Sampling Mode
|
||||
* @description
|
||||
* Identifies the valid values for the sampling mode.
|
||||
*/
|
||||
typedef enum {
|
||||
ICP_CAN_ONE_POINT = 0, /**< One sampling point */
|
||||
ICP_CAN_THREE_POINTS /**< Three sampling points */
|
||||
} icp_can_sampling_mode_t;
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Sync Mode
|
||||
* @description
|
||||
* Identifies the valid values for the sync mode.
|
||||
*/
|
||||
typedef enum {
|
||||
ICP_CAN_EDGE_R_TO_D = 0, /**< Recessive to dominant */
|
||||
ICP_CAN_BOTH_EDGES /**< Trigger on both edges */
|
||||
} icp_can_sync_t;
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Auto Restart Mode
|
||||
* @description
|
||||
* Identifies the valid values for the auto-restart mode.
|
||||
*/
|
||||
typedef enum {
|
||||
ICP_CAN_MANUAL = 0, /**< Manual restart */
|
||||
ICP_CAN_AUTO /**< Automatic restart */
|
||||
} icp_can_auto_restart_t;
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Common baud rates
|
||||
* @description
|
||||
* Identifies common baudrates.
|
||||
*/
|
||||
typedef enum {
|
||||
ICP_CAN_BAUD_10 = 0, /**< 10 kbps */
|
||||
ICP_CAN_BAUD_20, /**< 20 kbps */
|
||||
ICP_CAN_BAUD_50, /**< 50 kbps */
|
||||
ICP_CAN_BAUD_125, /**< 125 kbps */
|
||||
ICP_CAN_BAUD_250, /**< 250 kbps */
|
||||
ICP_CAN_BAUD_500, /**< 500 kbps */
|
||||
ICP_CAN_BAUD_800, /**< 800 kbps */
|
||||
ICP_CAN_BAUD_1000 /**< 1000 kbps */
|
||||
} icp_can_baud_t;
|
||||
|
||||
/**
|
||||
* @ingroup icp_CanAcc_Types
|
||||
* ICP CAN Interrupt Enables
|
||||
* @description
|
||||
* Identifies interrupt enables/disables.
|
||||
*/
|
||||
typedef enum {
|
||||
ICP_CAN_ENABLE, /**< Enable bit only */
|
||||
ICP_CAN_DISABLE, /**< Disable bit only */
|
||||
ICP_CAN_ALL, /**< All ints */
|
||||
ICP_CAN_NONE /**< No ints */
|
||||
} icp_can_interrupt_t;
|
||||
|
||||
|
||||
#endif /* __ICP_CAN_TYPES_H__ */
|
||||
@@ -0,0 +1,156 @@
|
||||
/* motMsCan.h - definitions for the Motorola MSCAN */
|
||||
|
||||
/* Copyright 1984-2004 Wind River Systems, Inc. */
|
||||
#include "copyright_wrs.h"
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,25jun04,bjn Adding extern "C" for CPP.
|
||||
01b,21apr04,bjn support DevIO interface
|
||||
01a,23oct03,bjn written
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains the functions declarations, specific to the
|
||||
new CAN controller, that implement the interface defined
|
||||
in the wnCAN.h header file.
|
||||
*/
|
||||
|
||||
#ifndef _MOTMSCAN_H_
|
||||
#define _MOTMSCAN_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*
|
||||
* Max number of message objects for Motorola MSCAN
|
||||
* TX = 0,1 and 2. RX = 3.
|
||||
*/
|
||||
|
||||
#define MOTMSCAN_MAX_TX_MSG_OBJ (3)
|
||||
#define MOTMSCAN_MAX_RX_MSG_OBJ (1)
|
||||
|
||||
#define MOTMSCAN_RX_MSG_OBJ_NUM (3)
|
||||
|
||||
#define MOTMSCAN_MAX_MSG_OBJ (MOTMSCAN_MAX_TX_MSG_OBJ + MOTMSCAN_MAX_RX_MSG_OBJ)
|
||||
|
||||
typedef struct _mscan_dev_
|
||||
{
|
||||
/* Configuration options, set before MOTMSCAN_Init() is called */
|
||||
|
||||
void * pMSCANregs;
|
||||
|
||||
UCHAR CANCTL0value;
|
||||
UCHAR CANCTL1value;
|
||||
UCHAR CANIDACvalue;
|
||||
UCHAR CANRIERvalue;
|
||||
int intNum;
|
||||
UINT freq;
|
||||
|
||||
/* Global data for the MSCAN device driver */
|
||||
|
||||
BOOL rtr[MOTMSCAN_MAX_TX_MSG_OBJ];
|
||||
|
||||
UCHAR can_RIERshadow;
|
||||
UCHAR tempDisableRXFIE;
|
||||
|
||||
WNCAN_IntType txChanInt[MOTMSCAN_MAX_TX_MSG_OBJ];
|
||||
}
|
||||
MSCAN_DEV;
|
||||
|
||||
|
||||
/* Data structures for the controller */
|
||||
|
||||
struct MSCAN_ChannelData
|
||||
{
|
||||
WNCAN_ChannelMode chnMode[MOTMSCAN_MAX_MSG_OBJ];
|
||||
};
|
||||
|
||||
|
||||
/* external globals for the controller */
|
||||
|
||||
extern const UINT g_MSCANchnType[MOTMSCAN_MAX_MSG_OBJ];
|
||||
|
||||
|
||||
/* external functions for the controller */
|
||||
|
||||
void MSCAN_registration (void);
|
||||
void MSCAN_ISR (ULONG context);
|
||||
|
||||
/*****************************************************************************
|
||||
* Register: CANCTL0
|
||||
*/
|
||||
|
||||
#define CR0_RXFRM (0x80)
|
||||
#define CR0_RXACT (0x40)
|
||||
#define CR0_CSWAI (0x20)
|
||||
#define CR0_SYNCH (0x10)
|
||||
#define CR0_TIME (0x08)
|
||||
#define CR0_WUPE (0x04)
|
||||
#define CR0_SLPRQ (0x02)
|
||||
#define CR0_INITRQ (0x01)
|
||||
|
||||
/*****************************************************************************
|
||||
* Register: CANCTL1
|
||||
*/
|
||||
|
||||
#define CR1_CANE (0x80)
|
||||
#define CR1_CLKSRC (0x40)
|
||||
#define CR1_LOOPB (0x20)
|
||||
#define CR1_LISTEN (0x10)
|
||||
#define CR1_WUPM (0x04)
|
||||
#define CR1_SLPAK (0x02)
|
||||
#define CR1_INITAK (0x01)
|
||||
|
||||
/*****************************************************************************
|
||||
* Register: CANRFLG/CANRIER
|
||||
*/
|
||||
|
||||
#define RX_WUPIE (0x80)
|
||||
#define RX_CSCIE (0x40)
|
||||
#define RX_RSTATE1 (0x20)
|
||||
#define RX_RSTATE0 (0x10)
|
||||
#define RX_TSTATE1 (0x08)
|
||||
#define RX_TSTATE0 (0x04)
|
||||
#define RX_OVRIE (0x02)
|
||||
#define RX_RXFIE (0x01)
|
||||
|
||||
#define RX_RX_STATUS_CHANGE_0_ENB (0x00<<4)
|
||||
#define RX_RX_STATUS_CHANGE_1_ENB (0x01<<4)
|
||||
#define RX_RX_STATUS_CHANGE_2_ENB (0x02<<4)
|
||||
#define RX_RX_STATUS_CHANGE_3_ENB (0x03<<4)
|
||||
|
||||
#define RX_TX_STATUS_CHANGE_0_ENB (0x00<<2)
|
||||
#define RX_TX_STATUS_CHANGE_1_ENB (0x01<<2)
|
||||
#define RX_TX_STATUS_CHANGE_2_ENB (0x02<<2)
|
||||
#define RX_TX_STATUS_CHANGE_3_ENB (0x03<<2)
|
||||
|
||||
#define RSTATE_BITS (0x30)
|
||||
#define TSTATE_BITS (0x0C)
|
||||
|
||||
/*****************************************************************************
|
||||
* Register: CANBTR0
|
||||
*/
|
||||
|
||||
#define BTR0_BRP_BITS (0x3f)
|
||||
|
||||
#define BTR0_SJW_BS (6)
|
||||
|
||||
/*****************************************************************************
|
||||
* Register: CANBTR1
|
||||
*/
|
||||
|
||||
#define BTR1_TSEG1_BITS (0x0f)
|
||||
#define BTR1_TSEG2_BITS (0x70)
|
||||
|
||||
#define BTR1_TSEG2_BS (4)
|
||||
#define BTR1_SAMP_BS (7)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _MOTMSCAN_H_ */
|
||||
@@ -0,0 +1,164 @@
|
||||
/* motMsCanOffsets.h - register offset definitions for the Motorola MSCAN */
|
||||
|
||||
/* Copyright 1984-2004 Wind River Systems, Inc. */
|
||||
#include "copyright_wrs.h"
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,25jun04,bjn Adding extern "C" for CPP.
|
||||
01b,05may04,bjn Removed MOTMSCAN_GetCanId, not required for external usage.
|
||||
01a,23oct03,bjn written
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains the functions Motorola Scalable CAN register offsets
|
||||
*/
|
||||
|
||||
#ifndef _MOTMSCAN_OFFSETS_H_
|
||||
#define _MOTMSCAN_OFFSETS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* MSCAN Base Register Offsets */
|
||||
|
||||
#define can_CR0 (0x00)
|
||||
#define can_CR1 (0x01)
|
||||
#define can_BTR0 (0x04)
|
||||
#define can_BTR1 (0x05)
|
||||
#define can_RFLG (0x08)
|
||||
#define can_RIER (0x09)
|
||||
#define can_TFLG (0x0C)
|
||||
#define can_TIER (0x0D)
|
||||
#define can_TARQ (0x10)
|
||||
#define can_TAAK (0x11)
|
||||
#define can_TBSEL (0x14)
|
||||
#define can_IDAC (0x15)
|
||||
#define can_RXERR (0x1c)
|
||||
#define can_TXERR (0x1d)
|
||||
|
||||
/* ID Acceptance Registers */
|
||||
#define can_IDAR0 (0x20)
|
||||
#define can_IDAR1 (0x21)
|
||||
#define can_IDAR2 (0x24)
|
||||
#define can_IDAR3 (0x25)
|
||||
#define can_IDAR4 (0x30)
|
||||
#define can_IDAR5 (0x31)
|
||||
#define can_IDAR6 (0x34)
|
||||
#define can_IDAR7 (0x35)
|
||||
|
||||
/* ID Mask Registers */
|
||||
#define can_IDMR0 (0x28)
|
||||
#define can_IDMR1 (0x29)
|
||||
#define can_IDMR2 (0x2C)
|
||||
#define can_IDMR3 (0x2D)
|
||||
#define can_IDMR4 (0x38)
|
||||
#define can_IDMR5 (0x39)
|
||||
#define can_IDMR6 (0x3C)
|
||||
#define can_IDMR7 (0x3D)
|
||||
|
||||
/* RX FG Buffer */
|
||||
#define can_RXIDR0 (0x40)
|
||||
#define can_RXIDR1 (0x41)
|
||||
#define can_RXIDR2 (0x44)
|
||||
#define can_RXIDR3 (0x45)
|
||||
#define can_RXDSR0 (0x48)
|
||||
#define can_RXDSR1 (0x49)
|
||||
#define can_RXDSR2 (0x4c)
|
||||
#define can_RXDSR3 (0x4d)
|
||||
#define can_RXDSR4 (0x50)
|
||||
#define can_RXDSR5 (0x51)
|
||||
#define can_RXDSR6 (0x54)
|
||||
#define can_RXDSR7 (0x55)
|
||||
#define can_RXDLR (0x58)
|
||||
#define can_RXTIMH (0x5c)
|
||||
#define can_RXTIML (0x5d)
|
||||
|
||||
/* TX FG Buffer */
|
||||
#define can_TXIDR0 (0x60)
|
||||
#define can_TXIDR1 (0x61)
|
||||
#define can_TXIDR2 (0x64)
|
||||
#define can_TXIDR3 (0x65)
|
||||
#define can_TXDSR0 (0x68)
|
||||
#define can_TXDSR1 (0x69)
|
||||
#define can_TXDSR2 (0x6c)
|
||||
#define can_TXDSR3 (0x6d)
|
||||
#define can_TXDSR4 (0x70)
|
||||
#define can_TXDSR5 (0x71)
|
||||
#define can_TXDSR6 (0x74)
|
||||
#define can_TXDSR7 (0x75)
|
||||
#define can_TXDLR (0x78)
|
||||
#define can_TXTBPR (0x79)
|
||||
#define can_TXTIMH (0x7c)
|
||||
#define can_TXTIML (0x7d)
|
||||
|
||||
|
||||
/*
|
||||
* Additional MSCAN API functions, provided mainly to configure
|
||||
* MSCAN filters
|
||||
*/
|
||||
|
||||
/*
|
||||
* CAN IDs for MSCAN ID Mask Registers:
|
||||
* '0' bit indicates match the bit.
|
||||
* '1' bit indicates don't match the bit.
|
||||
*/
|
||||
|
||||
#define NO_MATCH_STD_BITS (0x000007ffUL) /* 11 Bits for standard CAN */
|
||||
#define NO_MATCH_EXT_BITS (0x1fffffffUL) /* 29 Bits for extended CAN */
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
UINT32 IDR0_3;
|
||||
}
|
||||
id32;
|
||||
|
||||
struct
|
||||
{
|
||||
UINT16 IDR0_1;
|
||||
UINT16 IDR2_3;
|
||||
}
|
||||
id16;
|
||||
|
||||
struct
|
||||
{
|
||||
UINT8 IDR0;
|
||||
UINT8 IDR1;
|
||||
UINT8 IDR2;
|
||||
UINT8 IDR3;
|
||||
}
|
||||
id8;
|
||||
}
|
||||
MSCAN_ID_REG;
|
||||
|
||||
#define SET_MSCAN_IDE_BIT (0x01)
|
||||
#define SET_MSCAN_RTR_BIT (0x02)
|
||||
#define SET_MSCAN_SRR_BIT (0x04)
|
||||
|
||||
void MOTMSCAN_GetIdMsgBuffer (long canId, BOOL ext, UINT8 options,
|
||||
MSCAN_ID_REG * pMSCAN_IDR);
|
||||
|
||||
/*****************************************************************************
|
||||
* Register: IDAC
|
||||
*/
|
||||
|
||||
#define IDAM_BS (3)
|
||||
|
||||
#define IDAM_2_32BIT_FILTERS (0x00)
|
||||
#define IDAM_4_16BIT_FILTERS (0x10)
|
||||
#define IDAM_8_08BIT_FILTERS (0x20)
|
||||
#define IDAM_FILTER_CLOSED (0x30)
|
||||
|
||||
#define IDAM_BITS (0x30)
|
||||
#define IDHIT_BITS (0x07)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _MOTMSCAN_OFFSETS_H_ */
|
||||
@@ -0,0 +1,176 @@
|
||||
/* am335xCan.h - definitions for AM335X based CAN controller */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012, 2014 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01aug14,hcl add Altera Soc Gen 5 support
|
||||
01a,30nov12,wqi written.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains definitions used only in am335xCan.c
|
||||
and am335xCan_cfg.c
|
||||
*/
|
||||
|
||||
#ifndef __INCam335xCanh
|
||||
#define __INCam335xCanh
|
||||
|
||||
/* includes */
|
||||
|
||||
#include <dllLib.h>
|
||||
#include <CAN/TiDCan.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* external WindNet CAN required functions */
|
||||
|
||||
/*
|
||||
* Since all AM335X devices are internal to the processor, only one
|
||||
* board can exist.
|
||||
*/
|
||||
|
||||
#define MAX_NUM_AM335X_CAN_BOARDS (1)
|
||||
|
||||
#define BRD_NDX (0) /* only one board possible */
|
||||
|
||||
#ifdef ALT_DEV_BOARD_CYCLONE_V
|
||||
# define INUM_MSG0 164 /* can0_mo_IRQ */
|
||||
# define INUM_SYS0 163 /* can0_sts_IRQ */
|
||||
# define INUM_ERR0 166 /* can0_ecc_uncorrected_IRQ */
|
||||
# define INUM_MSG1 168 /* can1_mo_IRQ */
|
||||
# define INUM_SYS1 167 /* can1_sts_IRQ */
|
||||
# define INUM_ERR1 170 /* can1_ecc_uncorrected_IRQ */
|
||||
#else
|
||||
# define INUM_MSG0 52 /* DCAN0 interrupt0 */
|
||||
# define INUM_SYS0 53 /* DCAN0 interrupt1 */
|
||||
# define INUM_ERR0 54 /* DCAN0 Parity */
|
||||
# define INUM_MSG1 55 /* DCAN1 interrupt0 */
|
||||
# define INUM_SYS1 56 /* DCAN1 interrupt1 */
|
||||
# define INUM_ERR1 57 /* DCAN1 Parity */
|
||||
#endif /* ALT_DEV_BOARD_CYCLONE_V */
|
||||
|
||||
#define CFG_IMMR 0x80000000
|
||||
#define MAX_FIFO_SIZE 32
|
||||
|
||||
/* the 1Mbps bitrate is the max bitrate */
|
||||
|
||||
#define AM335X_CAN_BTR_MAX 1000000
|
||||
|
||||
/* the time segment before the sample point */
|
||||
|
||||
#define AM335X_CAN_BTR_TSEG1 9
|
||||
|
||||
/* the time segment after the sample point */
|
||||
|
||||
#define AM335X_CAN_BTR_TSEG2 2
|
||||
|
||||
/* the synchronization jump width */
|
||||
|
||||
#define AM335X_CAN_BTR_SJW 1
|
||||
|
||||
/* the defalut bitrates */
|
||||
|
||||
#define AM335X_CAN_BTR_BRP_10K 200
|
||||
#define AM335X_CAN_BTR_BRP_20K 100
|
||||
#define AM335X_CAN_BTR_BRP_25K 80
|
||||
#define AM335X_CAN_BTR_BRP_50K 40
|
||||
#define AM335X_CAN_BTR_BRP_100K 20
|
||||
#define AM335X_CAN_BTR_BRP_125K 16
|
||||
#define AM335X_CAN_BTR_BRP_250K 8
|
||||
#define AM335X_CAN_BTR_BRP_500K 4
|
||||
#define AM335X_CAN_BTR_BRP_1M 2
|
||||
|
||||
/* typedefs */
|
||||
|
||||
/* we need an identifier for each individual AM335X controllers */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DCAN1_CTRL,
|
||||
DCAN2_CTRL
|
||||
}
|
||||
DCAN_CTRL_ID;
|
||||
|
||||
typedef struct _dcan_fifo_
|
||||
{
|
||||
DL_NODE pNode;
|
||||
UCHAR channelNum[MAX_FIFO_SIZE];
|
||||
UCHAR bufferSize;
|
||||
} DCAN_FIFO;
|
||||
|
||||
/*
|
||||
* Define a type to record AM335X device instance.
|
||||
* Used to pass BSP configuration data to WNCAN.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
DCAN_CTRL_ID DCANcontrollerId; /* AM335X controller Identifier. */
|
||||
void * pDevBaseAddr; /* base address of AM335X device */
|
||||
int intNummsg; /* interrupt number */
|
||||
int intNumsys; /* interrupt number */
|
||||
int intNumerr; /* interrupt number */
|
||||
|
||||
UINT32 freq; /* frequency */
|
||||
UINT32 cfgOptions; /* config options */
|
||||
UCHAR taChl; /* the number of all channels */
|
||||
UCHAR rxChl; /* the number of receive channels */
|
||||
UCHAR txChl; /* the number of transmission channels */
|
||||
|
||||
/* default bit timing setting */
|
||||
|
||||
UCHAR brp;
|
||||
UCHAR sjw;
|
||||
UCHAR tseg1;
|
||||
UCHAR tseg2;
|
||||
|
||||
}
|
||||
am335x_mscan_instance;
|
||||
|
||||
IMPORT STATUS am335xCan_init (am335x_mscan_instance * pDCANboardCfg);
|
||||
IMPORT STATUS am335xCan_establishLinks (struct WNCAN_Device *);
|
||||
IMPORT struct WNCAN_Device * am335xCan_open (UINT32, UINT32);
|
||||
IMPORT STATUS am335xCan_close (struct WNCAN_Device *);
|
||||
|
||||
IMPORT STATUS CAN_FreeFifoRxChannel (struct WNCAN_Device *pDev,
|
||||
UCHAR channelNum);
|
||||
IMPORT STATUS CAN_SetupFifoRxChannel (struct WNCAN_Device *pDev,
|
||||
UCHAR * channelNum, UCHAR size,
|
||||
ULONG canID, BOOL ext,
|
||||
WNCAN_IntType intSetting, long mask);
|
||||
|
||||
IMPORT BOOL am335x_cfgGet_inUse (UINT32 brdNdx);
|
||||
IMPORT void am335x_cfgSet_inUse (UINT32 brdNdx, BOOL val);
|
||||
IMPORT BOOL am335x_cfgGet_allocated (UINT32 brdNdx, UINT32 ctrlNdx);
|
||||
IMPORT void am335x_cfgSet_allocated (UINT32 brdNdx, UINT32 ctrlNdx,
|
||||
BOOL val);
|
||||
|
||||
IMPORT struct WNCAN_Board * am335x_cfgGet_canBoardPtr (UINT32 brdNdx);
|
||||
IMPORT struct WNCAN_Device * am335x_cfgGet_canDevicePtr
|
||||
(UINT32 brdNdx, UINT32 ctrlNdx);
|
||||
IMPORT struct WNCAN_Controller * am335x_cfgGet_canControllerPtr
|
||||
(UINT32 brdNdx, UINT32 ctrlNdx);
|
||||
IMPORT DCAN_DEV * am335x_cfgGet_mscanDevPtr
|
||||
(UINT32 brdNdx, UINT32 ctrlNdx);
|
||||
IMPORT WNCAN_ChannelMode * am335x_cfgGet_chModePtr
|
||||
(UINT32 brdNdx, UINT32 ctrlNdx);
|
||||
IMPORT WNCAN_ChannelMode * am335x_cfgGet_chTypePtr
|
||||
(UINT32 brdNdx, UINT32 ctrlNdx);
|
||||
IMPORT UINT32 am335x_cfgGet_NumControllers (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __INCam335xCanh */
|
||||
@@ -0,0 +1,70 @@
|
||||
/* can_tolapai.h - definitions for tolapai CAN controller */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,04Dec07,d_z written
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains definitions used for tolapai CAN controller
|
||||
*/
|
||||
|
||||
#ifndef _TOLAPAI_CAN_H_
|
||||
#define _TOLAPAI_CAN_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* external WindNet CAN required functions */
|
||||
|
||||
/*
|
||||
* Since all MSCAN devices are internal to the processor, only one
|
||||
* board can exist.
|
||||
*/
|
||||
|
||||
#define MAX_NUM_TOLAPAI_CAN_BOARDS (1)
|
||||
#define MAX_NUM_TOLAPAI_CAN_CONTROLLERS (2)
|
||||
|
||||
#define BRD_NDX (0) /* Only one board possible */
|
||||
|
||||
#define PCI_CFG_POWER 0xe0
|
||||
#define PCI_CFG_POWER_CTL 0x3
|
||||
|
||||
#define PCI_CFG_SMIA 0xe8
|
||||
#define PCI_CFG_SMIA_SYS_INT (1<<0)
|
||||
#define PCI_CFG_SMIA_PARITY_INT (1<<1)
|
||||
|
||||
|
||||
struct tolapaiCan_DeviceEntry
|
||||
{
|
||||
BOOL inUse;
|
||||
|
||||
/* data types for the board */
|
||||
|
||||
struct WNCAN_Board canBoard;
|
||||
|
||||
/* data types for each controller on the board */
|
||||
|
||||
BOOL allocated [MAX_NUM_TOLAPAI_CAN_CONTROLLERS];
|
||||
struct WNCAN_Device canDevice [MAX_NUM_TOLAPAI_CAN_CONTROLLERS];
|
||||
struct WNCAN_Controller canController [MAX_NUM_TOLAPAI_CAN_CONTROLLERS];
|
||||
|
||||
can_os_t can_os [MAX_NUM_TOLAPAI_CAN_CONTROLLERS];
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _TOLAPAI_CAN_H_ */
|
||||
@@ -0,0 +1,53 @@
|
||||
/* esd_can_pc104_200.h - definitions for ESD CAN PC104/200 board */
|
||||
|
||||
/* Copyright 2001 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
20dec01, dnb written
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains definitions used only in esd_can_pc104_200.c
|
||||
and esd_can_pc104_200_cfg.c
|
||||
|
||||
*/
|
||||
|
||||
#ifndef ESD_CAN_PC104_200_H
|
||||
#define ESD_CAN_PC104_200_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define ESD_CAN_PC104_200_MAX_CONTROLLERS (2)
|
||||
|
||||
struct ESD_CAN_PC104_200_DeviceEntry
|
||||
{
|
||||
ULONG ioAddress;
|
||||
UINT irq;
|
||||
BOOL inUse;
|
||||
|
||||
struct WNCAN_Device canDevice[ESD_CAN_PC104_200_MAX_CONTROLLERS];
|
||||
struct WNCAN_Controller canControllerArray[ESD_CAN_PC104_200_MAX_CONTROLLERS];
|
||||
struct WNCAN_Board canBoardArray[ESD_CAN_PC104_200_MAX_CONTROLLERS];
|
||||
BOOL allocated[ESD_CAN_PC104_200_MAX_CONTROLLERS];
|
||||
|
||||
WNCAN_ChannelMode i82527chnMode[I82527_MAX_MSG_OBJ];
|
||||
struct i82527ChipSpecific can82527;
|
||||
|
||||
WNCAN_ChannelMode sja1000chnMode[SJA1000_MAX_MSG_OBJ];
|
||||
struct TxMsg txMsg;
|
||||
|
||||
};
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ESD_CAN_PC104_200_H */
|
||||
@@ -0,0 +1,54 @@
|
||||
/* esd_pci_200.h - definitions for ESD PCI/200 board */
|
||||
|
||||
/* Copyright 2001 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
20dec01, dnb written
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains definitions used only in esd_pci_200.
|
||||
and esd_pci_200_cfg.c
|
||||
|
||||
*/
|
||||
#ifndef ESD_PCI_200_H
|
||||
#define ESD_PCI_200_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define ESD_PCI_200_MAX_CONTROLLERS (2)
|
||||
|
||||
|
||||
struct ESD_PCI_200_ChannelData
|
||||
{
|
||||
WNCAN_ChannelMode sja1000chnMode[SJA1000_MAX_MSG_OBJ];
|
||||
};
|
||||
|
||||
|
||||
struct ESD_PCI_200_DeviceEntry
|
||||
{
|
||||
struct WNCAN_Device canDevice[ESD_PCI_200_MAX_CONTROLLERS];
|
||||
struct ESD_PCI_200_ChannelData chData[ESD_PCI_200_MAX_CONTROLLERS];
|
||||
struct WNCAN_Controller canControllerArray[ESD_PCI_200_MAX_CONTROLLERS];
|
||||
struct WNCAN_Board canBoard;
|
||||
struct TxMsg txMsg[ESD_PCI_200_MAX_CONTROLLERS];
|
||||
int bus;
|
||||
int dev;
|
||||
int func;
|
||||
BOOL inUse;
|
||||
BOOL allocated[ESD_PCI_200_MAX_CONTROLLERS];
|
||||
BOOL intConnect;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ESD_PCI_200_H */
|
||||
@@ -0,0 +1,48 @@
|
||||
/* m5282CAN.h - definitions for MCF5282 baords */
|
||||
|
||||
/* Copyright 2001 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,08apr04,lsg Modified for supporting WindNet CAN 1.3
|
||||
01a,24sep03,eli support for MCF5282 (ColdFire) FlexCAN module
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains the declarations and definitions that are used for
|
||||
MCF5282 boards
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _m5282CAN_H_
|
||||
#define _m5282CAN_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*Define the number of controllers on-board (or on-chip)*/
|
||||
#define MAX_M5282_CAN_DEVICES 1
|
||||
|
||||
struct m5282CAN_DeviceEntry
|
||||
{
|
||||
BOOL inUse;
|
||||
struct WNCAN_Device canDevice;
|
||||
struct WNCAN_Controller canController;
|
||||
struct WNCAN_Board canBoard;
|
||||
struct canAccess canRegAccess;
|
||||
BOOL allocated;
|
||||
WNCAN_ChannelMode FlexCANchnMode[FLEXCAN_MAX_MSG_OBJ];
|
||||
};
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* _m5282CAN_H_ */
|
||||
@@ -0,0 +1,97 @@
|
||||
/* mpc5121eCan.h - definitions for MPC5121E based CAN controller */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,01dec08,x_f written
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains definitions used only in mpc5121eCan.c
|
||||
and mpc5121eCan_cfg.c
|
||||
*/
|
||||
|
||||
#ifndef _MPC5121E_CAN_H_
|
||||
#define _MPC5121E_CAN_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#include "CAN/motMsCan.h"
|
||||
|
||||
/* external WindNet CAN required functions */
|
||||
|
||||
/*
|
||||
* Since all MSCAN devices are internal to the processor, only one
|
||||
* board can exist.
|
||||
*/
|
||||
|
||||
#define MAX_NUM_MPC5121E_CAN_BOARDS (1)
|
||||
|
||||
#define BRD_NDX (0) /* Only one board possible */
|
||||
|
||||
#define INUM_CAN1 12
|
||||
#define INUM_CAN2 13
|
||||
#define IV_CAN1 INUM_TO_IVEC (INUM_CAN1)
|
||||
#define IV_CAN2 INUM_TO_IVEC (INUM_CAN2)
|
||||
|
||||
#define CFG_IMMR 0x80000000
|
||||
|
||||
/* We need an identifier for each individual MSCAN controllers */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MSCAN1_CTRL,
|
||||
MSCAN2_CTRL
|
||||
}
|
||||
MSCAN_CTRL_ID;
|
||||
|
||||
/*
|
||||
* Define a type to record MSCAN device instance.
|
||||
* Used to pass BSP configuration data to WNCAN
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
MSCAN_CTRL_ID MSCANcontrollerId; /* MSCAN controller Identifier. */
|
||||
void * pDevBaseAddr; /* Base address of MSCAN device */
|
||||
VOIDFUNCPTR * pIntVec; /* Interrupt vector */
|
||||
int intNum; /* Interrupt number */
|
||||
UINT32 clockSource; /* 0=Oscillator Clock, 1=IP Bus Clock */
|
||||
UINT32 freq; /* frequency */
|
||||
}
|
||||
mpc5121e_mscan_instance;
|
||||
|
||||
/* Defined in mpc5121eCan.c */
|
||||
IMPORT STATUS mpc5121eCan_init (mpc5121e_mscan_instance * pMSCANboardCfg);
|
||||
IMPORT STATUS mpc5121eCan_establishLinks (struct WNCAN_Device *);
|
||||
IMPORT struct WNCAN_Device * mpc5121eCan_open (UINT, UINT);
|
||||
IMPORT STATUS mpc5121eCan_close (struct WNCAN_Device *);
|
||||
|
||||
/* Defined in mpc5121e_cfg.c */
|
||||
IMPORT BOOL mpc5121e_cfgGet_inUse (UINT brdNdx);
|
||||
IMPORT void mpc5121e_cfgSet_inUse (UINT brdNdx, BOOL val);
|
||||
IMPORT BOOL mpc5121e_cfgGet_allocated (UINT brdNdx, UINT ctrlNdx);
|
||||
IMPORT void mpc5121e_cfgSet_allocated (UINT brdNdx, UINT ctrlNdx, BOOL val);
|
||||
IMPORT struct WNCAN_Board * mpc5121e_cfgGet_canBoardPtr (UINT brdNdx);
|
||||
IMPORT struct WNCAN_Device * mpc5121e_cfgGet_canDevicePtr (UINT brdNdx, UINT ctrlNdx);
|
||||
IMPORT struct WNCAN_Controller * mpc5121e_cfgGet_canControllerPtr (UINT brdNdx, UINT ctrlNdx);
|
||||
IMPORT MSCAN_DEV * mpc5121e_cfgGet_mscanDevPtr (UINT brdNdx, UINT ctrlNdx);
|
||||
IMPORT WNCAN_ChannelMode * mpc5121e_cfgGet_chModePtr (UINT brdNdx, UINT ctrlNdx);
|
||||
IMPORT UINT32 mpc5121e_cfgGet_NumControllers (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _MPC5121E_CAN_H_ */
|
||||
@@ -0,0 +1,86 @@
|
||||
/* mpc5200Can.h - definitions for MPC5200 based CAN controller */
|
||||
|
||||
/* Copyright 1984-2004 Wind River Systems, Inc. */
|
||||
#include "copyright_wrs.h"
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,25jun04,bjn Adding extern "C" for CPP.
|
||||
01a,23oct03,bjn written
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains definitions used only in mpc5200Can.c
|
||||
and mpc5200Can_cfg.c
|
||||
*/
|
||||
|
||||
#ifndef _MPC5200_CAN_H_
|
||||
#define _MPC5200_CAN_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#include "CAN/motMsCan.h"
|
||||
|
||||
/* external WindNet CAN required functions */
|
||||
|
||||
/*
|
||||
* Since all MSCAN devices are internal to the processor, only one
|
||||
* board can exist.
|
||||
*/
|
||||
|
||||
#define MAX_NUM_MPC5200CAN_BOARDS (1)
|
||||
|
||||
#define BRD_NDX (0) /* Only one board possible */
|
||||
|
||||
/* We need an identifier for each individual MSCAN controllers */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MSCAN1_CTRL,
|
||||
MSCAN2_CTRL
|
||||
}
|
||||
MSCAN_CTRL_ID;
|
||||
|
||||
/*
|
||||
* Define a type to record MSCAN device instance.
|
||||
* Used to pass BSP configuration data to WNCAN
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
MSCAN_CTRL_ID MSCANcontrollerId; /* MSCAN controller Identifier. */
|
||||
void * pDevBaseAddr; /* Base address of MSCAN device */
|
||||
VOIDFUNCPTR * pIntVec; /* Interrupt vector */
|
||||
int intNum; /* Interrupt number */
|
||||
UINT32 clockSource; /* 0=Oscillator Clock, 1=IP Bus Clock */
|
||||
UINT32 freq; /* frequency */
|
||||
}
|
||||
mpc5200_mscan_instance;
|
||||
|
||||
/* Defined in mpc5200Can.c */
|
||||
IMPORT STATUS mpc5200Can_init (mpc5200_mscan_instance * pMSCANboardCfg);
|
||||
IMPORT STATUS mpc5200Can_establishLinks (struct WNCAN_Device *);
|
||||
IMPORT struct WNCAN_Device * mpc5200Can_open (UINT, UINT);
|
||||
IMPORT STATUS mpc5200Can_close (struct WNCAN_Device *);
|
||||
|
||||
/* Defined in mpc5200_cfg.c */
|
||||
IMPORT BOOL mpc5200_cfgGet_inUse (UINT brdNdx);
|
||||
IMPORT void mpc5200_cfgSet_inUse (UINT brdNdx, BOOL val);
|
||||
IMPORT BOOL mpc5200_cfgGet_allocated (UINT brdNdx, UINT ctrlNdx);
|
||||
IMPORT void mpc5200_cfgSet_allocated (UINT brdNdx, UINT ctrlNdx, BOOL val);
|
||||
IMPORT struct WNCAN_Board * mpc5200_cfgGet_canBoardPtr (UINT brdNdx);
|
||||
IMPORT struct WNCAN_Device * mpc5200_cfgGet_canDevicePtr (UINT brdNdx, UINT ctrlNdx);
|
||||
IMPORT struct WNCAN_Controller * mpc5200_cfgGet_canControllerPtr (UINT brdNdx, UINT ctrlNdx);
|
||||
IMPORT MSCAN_DEV * mpc5200_cfgGet_mscanDevPtr (UINT brdNdx, UINT ctrlNdx);
|
||||
IMPORT WNCAN_ChannelMode * mpc5200_cfgGet_chModePtr (UINT brdNdx, UINT ctrlNdx);
|
||||
IMPORT UINT32 mpc5200_cfgGet_NumControllers (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _MPC5200_CAN_H_ */
|
||||
@@ -0,0 +1,47 @@
|
||||
/* msmcan.h - definitions for MSMCAN PC104 board */
|
||||
|
||||
/* Copyright 2001 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
20dec01, dnb written
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains definitions used only in msmcan_pc104.c
|
||||
and msmcan_pc104_cfg.c
|
||||
|
||||
*/
|
||||
#ifndef MSMCAN_H
|
||||
#define MSMCAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define MSMCAN_PC104_MAX_CONTROLLERS (1)
|
||||
|
||||
struct MSMCAN_PC104_DeviceEntry
|
||||
{
|
||||
ULONG ioAddress;
|
||||
UINT irq;
|
||||
BOOL inUse;
|
||||
|
||||
struct WNCAN_Device canDevice;
|
||||
struct WNCAN_Controller canController;
|
||||
struct WNCAN_Board canBoard;
|
||||
BOOL allocated;
|
||||
|
||||
WNCAN_ChannelMode i82527chnMode[I82527_MAX_MSG_OBJ];
|
||||
struct i82527ChipSpecific can82527;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* MSMCAN_H */
|
||||
@@ -0,0 +1,46 @@
|
||||
/* ppc5xxCAN.h - definitions for PPC5xx baords */
|
||||
|
||||
/* Copyright 2001 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
27dec01, lsg
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains the declarations and definitions that are used for
|
||||
PPC5xx boards
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _ppc5xxCAN_H_
|
||||
#define _ppc5xxCAN_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*Define the number of controllers on-board (or on-chip)*/
|
||||
#define PPC5XXCAN_MAX_CONTROLLERS (1)
|
||||
|
||||
struct ppc5xxCAN_DeviceEntry
|
||||
{
|
||||
BOOL inUse;
|
||||
struct WNCAN_Device canDevice;
|
||||
struct WNCAN_Controller canController;
|
||||
struct WNCAN_Board canBoard;
|
||||
struct canAccess canRegAccess;
|
||||
BOOL allocated;
|
||||
WNCAN_ChannelMode TouCANchnMode[TOUCAN_MAX_MSG_OBJ];
|
||||
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,110 @@
|
||||
/* SJA1000.h - definitions for Phillips SJA1000 CAN Controller */
|
||||
|
||||
/* Copyright 2001 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,06oct05,lsg Rename macros that are common with
|
||||
target/h/arch/mips/archMips
|
||||
09nov01,dnb modified for integration into Tornado
|
||||
12jul01,jac written
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains the functions declarations, specific to the
|
||||
Phillips SJA1000 CAN controller, that implement the interface defined
|
||||
in the windnet_can.h header file.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef SJA1000_H_
|
||||
#define SJA1000_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* mode register bits */
|
||||
#define MOD_RM 0x01
|
||||
#define MOD_LOM 0x02
|
||||
#define MOD_STM 0x04
|
||||
#define MOD_AFM 0x08
|
||||
#define MOD_SM 0x10
|
||||
|
||||
/* command register bits */
|
||||
#define CMR_TR 0x01
|
||||
#define CMR_AT 0x02
|
||||
#define CMR_RRB 0x04
|
||||
#define CMR_CDO 0x08
|
||||
#define CMR_SRR 0x10
|
||||
|
||||
/* status register bits */
|
||||
#define SJA1000_SR_RBS 0x01
|
||||
#define SJA1000_SR_DOS 0x02
|
||||
#define SJA1000_SR_TBS 0x04
|
||||
#define SJA1000_SR_TCS 0x08
|
||||
#define SJA1000_SR_RS 0x10
|
||||
#define SJA1000_SR_TS 0x20
|
||||
#define SJA1000_SR_ES 0x40
|
||||
#define SJA1000_SR_BS 0x80
|
||||
|
||||
/* interrupt register bits */
|
||||
#define IR_RI 0x01
|
||||
#define IR_TI 0x02
|
||||
#define IR_EI 0x04
|
||||
#define IR_DOI 0x08
|
||||
#define IR_WUI 0x10
|
||||
#define IR_EPI 0x20
|
||||
#define IR_ALI 0x40
|
||||
#define IR_BEI 0x80
|
||||
|
||||
/* interrupt enable register bits */
|
||||
#define IER_RIE 0x01
|
||||
#define IER_TIE 0x02
|
||||
#define IER_EIE 0x04
|
||||
#define IER_DOIE 0x08
|
||||
#define IER_WUIE 0x10
|
||||
#define IER_EPIE 0x20
|
||||
#define IER_ALIE 0x40
|
||||
#define IER_BEIE 0x80
|
||||
|
||||
/* error code capture register */
|
||||
#define ECC_SEG0 0x01
|
||||
#define ECC_SEG1 0x02
|
||||
#define ECC_SEG2 0x04
|
||||
#define ECC_SEG3 0x08
|
||||
#define ECC_SEG4 0x10
|
||||
#define ECC_DIR 0x20
|
||||
#define ECC_ERRC0 0x40
|
||||
#define ECC_ERCC1 0x80
|
||||
|
||||
/* max number of message objects for sja1000 */
|
||||
#define SJA1000_MAX_MSG_OBJ 2
|
||||
|
||||
/* sja1000 channel types */
|
||||
#define TX_CHN_NUM 0
|
||||
#define RX_CHN_NUM 1
|
||||
|
||||
extern const UINT g_sja1000chnType[SJA1000_MAX_MSG_OBJ];
|
||||
|
||||
struct TxMsg
|
||||
{
|
||||
ULONG id;
|
||||
BOOL ext;
|
||||
BOOL rtr;
|
||||
UCHAR len;
|
||||
UCHAR data[8];
|
||||
};
|
||||
|
||||
void sja1000_registration(void);
|
||||
void sja1000ISR(ULONG context);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* SJA1000_H_ */
|
||||
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains the sja1000 pelican register offsets
|
||||
|
||||
*/
|
||||
|
||||
#ifndef SJA1000_OFFSETS_H_
|
||||
#define SJA1000_OFFSETS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define SJA1000_MOD 0
|
||||
#define SJA1000_CMR 1
|
||||
#define SJA1000_SR 2
|
||||
#define SJA1000_IR 3
|
||||
#define SJA1000_IER 4
|
||||
#define SJA1000_BTR0 6
|
||||
#define SJA1000_BTR1 7
|
||||
#define SJA1000_OCR 8
|
||||
#define SJA1000_ALC 11
|
||||
#define SJA1000_ECC 12
|
||||
#define SJA1000_EWLR 13
|
||||
#define SJA1000_RXERR 14
|
||||
#define SJA1000_TXERR 15
|
||||
#define SJA1000_SFF 16
|
||||
#define SJA1000_EFF 16
|
||||
#define SJA1000_ACR0 16
|
||||
#define SJA1000_RXID 17
|
||||
#define SJA1000_TXID 17
|
||||
#define SJA1000_ACR1 17
|
||||
#define SJA1000_ACR2 18
|
||||
#define SJA1000_ACR3 19
|
||||
#define SJA1000_SFDATA 19
|
||||
#define SJA1000_AMR0 20
|
||||
#define SJA1000_AMR1 21
|
||||
#define SJA1000_AMR2 22
|
||||
#define SJA1000_AMR3 23
|
||||
#define SJA1000_RMC 29
|
||||
#define SJA1000_RXBSA 30
|
||||
#define SJA1000_CDR 31
|
||||
|
||||
#define SJA1000_MAX_OFFSET 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,125 @@
|
||||
#ifndef _TOUCAN_H_
|
||||
#define _TOUCAN_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#include <drv/misc/can/ppcTouCAN.h>
|
||||
|
||||
/***********************************************************************/
|
||||
/* MPC5XX Internal Memory Map Assignments (MC5XX) */
|
||||
/***********************************************************************/
|
||||
/* This is the internal message sructure as used by the
|
||||
** CAN device driver source code. The user never uses this structure
|
||||
*/
|
||||
|
||||
typedef struct _toucanChannel_ {
|
||||
volatile unsigned short Control;
|
||||
volatile unsigned short Id;
|
||||
volatile unsigned short Id2_OR_TimeStamp;
|
||||
volatile unsigned char Data[8];
|
||||
volatile unsigned short No_use;
|
||||
|
||||
} TouCAN_StandardMsgType;
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Register offsets
|
||||
*/
|
||||
|
||||
typedef struct _toucan_
|
||||
{
|
||||
volatile unsigned short can_MCR;
|
||||
volatile unsigned short can_TTR;
|
||||
volatile unsigned short can_ICR;
|
||||
volatile unsigned char can_CR0;
|
||||
volatile unsigned char can_CR1;
|
||||
volatile unsigned char can_PRESDIV;
|
||||
volatile unsigned char can_CR2;
|
||||
volatile unsigned short can_TIMER;
|
||||
volatile unsigned short can_res1[2];
|
||||
volatile unsigned long can_RxGlobalMask;
|
||||
volatile unsigned long can_RxBuff14Mask;
|
||||
volatile unsigned long can_RxBuff15Mask;
|
||||
volatile unsigned short can_res2[2];
|
||||
volatile unsigned short can_ESTAT;
|
||||
volatile unsigned short can_IMASK;
|
||||
volatile unsigned short can_IFLAG;
|
||||
volatile unsigned char can_RxECTR;
|
||||
volatile unsigned char can_TxECTR;
|
||||
} _TouCAN; /* 384 bytes total */
|
||||
|
||||
|
||||
typedef struct _toucanBuffers_
|
||||
{
|
||||
volatile TouCAN_StandardMsgType can_MSG[TOUCAN_MAX_MSG_OBJ];
|
||||
}_TouCANbuffers;
|
||||
|
||||
typedef volatile _TouCAN *TouCAN;
|
||||
typedef volatile _TouCANbuffers *TouCANBuf;
|
||||
|
||||
struct canAccess
|
||||
{
|
||||
TouCAN pTouCanRegs;
|
||||
TouCANBuf pTouCanBufs;
|
||||
UCHAR ToucanPropseg;
|
||||
USHORT TouCANAutoPowersSave;
|
||||
USHORT TouCANSupv;
|
||||
UCHAR TouCANTimerSync;
|
||||
UCHAR TouCANLBuf;
|
||||
};
|
||||
|
||||
/* table of regbases for each can channel */
|
||||
extern TouCAN pTouCanRegsBaseAdr[];
|
||||
extern TouCANBuf pTouCanBufsBaseAdr[];
|
||||
|
||||
/*
|
||||
* Formatting identifier bits
|
||||
*/
|
||||
#define TOUCAN_ID_BITS_28TO18 0xFFE0
|
||||
#define TOUCAN_ID_BITS_17TO15 0x7
|
||||
#define TOUCAN_IDE_EXT 0x0008
|
||||
|
||||
extern const UINT g_TOUCANchnType[TOUCAN_MAX_MSG_OBJ];
|
||||
|
||||
#define TOUCAN_RXBUF14_MASK 14
|
||||
#define TOUCAN_RXBUF15_MASK 15
|
||||
|
||||
/*----------------------------------------------
|
||||
* duplicate macros, added in ppcToucan.h after
|
||||
* CAN api update
|
||||
*
|
||||
* TOUCAN Control Register (TOUCAN_CR2)
|
||||
*(MSB)0 1 2 3 4 5 6 7
|
||||
* --------------------------------------------
|
||||
*| RJW | PSEG | PSEG2 |
|
||||
*| | | |
|
||||
* --------------------------------------------
|
||||
*/
|
||||
|
||||
#ifndef TOUCAN_RJW
|
||||
#define TOUCAN_RJW 0xC0
|
||||
#endif
|
||||
|
||||
#ifndef TOUCAN_PSEG
|
||||
#define TOUCAN_PSEG 0x38
|
||||
#endif
|
||||
|
||||
#ifndef TOUCAN_PSEG2
|
||||
#define TOUCAN_PSEG2 0x07
|
||||
#endif
|
||||
|
||||
#ifndef TOUCAN_GetM17TO0
|
||||
#define TOUCAN_GetM17TO0 0x0007fffe
|
||||
#endif
|
||||
|
||||
/*------------------------------------------------*/
|
||||
|
||||
void TouCAN_registration(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _toucan_H_ */
|
||||
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains the TOUCAN register offsets
|
||||
|
||||
*/
|
||||
|
||||
#ifndef TOUCAN_OFFSETS_H_
|
||||
#define TOUCAN_OFFSETS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define TOUCAN_MCR_OFFSET 0x0
|
||||
#define TOUCAN_TTR_OFFSET 0x2
|
||||
#define TOUCAN_ICR_OFFSET 0x4
|
||||
#define TOUCAN_CR0_OFFSET 0x6
|
||||
#define TOUCAN_CR1_OFFSET 0x7
|
||||
#define TOUCAN_PRESDIV_OFFSET 0x8
|
||||
#define TOUCAN_CR2_OFFSET 0x9
|
||||
#define TOUCAN_TIMER_OFFSET 0xA
|
||||
#define TOUCAN_RXGLOBALMASK_OFFSET 0x10
|
||||
#define TOUCAN_RXBUFF14MASK_OFFSET 0x14
|
||||
#define TOUCAN_RXBUFF15MASK_OFFSET 0x18
|
||||
#define TOUCAN_ESTAT_OFFSET 0x20
|
||||
#define TOUCAN_IMASK_OFFSET 0x22
|
||||
#define TOUCAN_IFLAG_OFFSET 0x24
|
||||
#define TOUCAN_RXECTR_OFFSET 0x26
|
||||
#define TOUCAN_TXECTR_OFFSET 0x27
|
||||
#define TOUCAN_REG_MAX_OFFSET 0x28
|
||||
|
||||
#define TOUCAN_BUFF0_OFFSET 0x100
|
||||
#define TOUCAN_BUFF1_OFFSET 0x110
|
||||
#define TOUCAN_BUFF2_OFFSET 0x120
|
||||
#define TOUCAN_BUFF3_OFFSET 0x130
|
||||
#define TOUCAN_BUFF4_OFFSET 0x140
|
||||
#define TOUCAN_BUFF5_OFFSET 0x150
|
||||
#define TOUCAN_BUFF6_OFFSET 0x160
|
||||
#define TOUCAN_BUFF7_OFFSET 0x170
|
||||
#define TOUCAN_BUFF8_OFFSET 0x180
|
||||
#define TOUCAN_BUFF9_OFFSET 0x190
|
||||
#define TOUCAN_BUFF10_OFFSET 0x1a0
|
||||
#define TOUCAN_BUFF11_OFFSET 0x1b0
|
||||
#define TOUCAN_BUFF12_OFFSET 0x1c0
|
||||
#define TOUCAN_BUFF13_OFFSET 0x1d0
|
||||
#define TOUCAN_BUFF14_OFFSET 0x1e0
|
||||
#define TOUCAN_BUFF15_OFFSET 0x1f0
|
||||
#define TOUCAN_BUF_MAX_OFFSET 0x200
|
||||
|
||||
#define TOUCAN_BUFF_CTRLSTAT_OFFSET 0
|
||||
#define TOUCAN_BUFF_IDHI_OFFSET 2
|
||||
#define TOUCAN_BUFF_IDLO_OFFSET 4
|
||||
#define TOUCAN_BUFF_DATA0_OFFSET 6
|
||||
#define TOUCAN_BUFF_DATA1_OFFSET 7
|
||||
#define TOUCAN_BUFF_DATA2_OFFSET 8
|
||||
#define TOUCAN_BUFF_DATA3_OFFSET 9
|
||||
#define TOUCAN_BUFF_DATA4_OFFSET 0xa
|
||||
#define TOUCAN_BUFF_DATA5_OFFSET 0xb
|
||||
#define TOUCAN_BUFF_DATA6_OFFSET 0xc
|
||||
#define TOUCAN_BUFF_DATA7_OFFSET 0xd
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,415 @@
|
||||
/* wnCAN.h - definitions for Windnet CAN Interface */
|
||||
|
||||
/* Copyright 2001 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,06oct05,lsg fix warning
|
||||
09nov01,dnb modified for integration into Tornado
|
||||
12jul01,jac written
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
DESCRIPTION
|
||||
This file contains the declarations and definitions that comprise the
|
||||
Windnet CAN Interface.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef WN_CAN_H
|
||||
#define WN_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#include <CAN/canController.h>
|
||||
#include <CAN/canBoard.h>
|
||||
|
||||
typedef struct tagCANVersionInfo
|
||||
{
|
||||
UCHAR major;
|
||||
UCHAR minor;
|
||||
} WNCAN_VersionInfo;
|
||||
|
||||
#define WNCAN_ILLEGAL_CHN_NUM 0xff
|
||||
|
||||
/* types of channel configurations */
|
||||
#define WNCAN_CHN_INVALID 0x00
|
||||
#define WNCAN_CHN_TRANSMIT 0x01
|
||||
#define WNCAN_CHN_RECEIVE 0x02
|
||||
#define WNCAN_CHN_TRANSMIT_RECEIVE 0x03
|
||||
#define WNCAN_CHN_INACTIVE 0x04
|
||||
#define WNCAN_CHN_RTR_REQUESTER 0x11
|
||||
#define WNCAN_CHN_RTR_RESPONDER 0x12
|
||||
|
||||
typedef UINT WNCAN_ChannelType;
|
||||
typedef UINT WNCAN_ChannelMode;
|
||||
|
||||
#define WNCAN_IS_CHN_RTR 0x10
|
||||
|
||||
/* CAN bus error type */
|
||||
#define WNCAN_ERR_NONE 0
|
||||
#define WNCAN_ERR_BIT 0x1
|
||||
#define WNCAN_ERR_ACK 0x2
|
||||
#define WNCAN_ERR_CRC 0x4
|
||||
#define WNCAN_ERR_FORM 0x8
|
||||
#define WNCAN_ERR_STUFF 0x10
|
||||
#define WNCAN_ERR_UNKNOWN 0x20
|
||||
|
||||
typedef UINT WNCAN_BusError;
|
||||
|
||||
/* status code returned by CAN_GetBusStatus */
|
||||
#define WNCAN_BUS_OK 0
|
||||
#define WNCAN_BUS_WARN 1
|
||||
#define WNCAN_BUS_OFF 2
|
||||
|
||||
typedef UINT WNCAN_BusStatus;
|
||||
|
||||
/* Interrupt status */
|
||||
#define WNCAN_INT_NONE 0
|
||||
#define WNCAN_INT_ERROR 0x1
|
||||
#define WNCAN_INT_BUS_OFF 0x2
|
||||
#define WNCAN_INT_WAKE_UP 0x4
|
||||
#define WNCAN_INT_TX 0x8
|
||||
#define WNCAN_INT_RX 0x10
|
||||
#define WNCAN_INT_RTR_RESPONSE 0x20
|
||||
#define WNCAN_INT_TXCLR 0x40
|
||||
#define WNCAN_INT_SPURIOUS 0xffffeeee
|
||||
#define WNCAN_INT_ALL 0xffffffff
|
||||
|
||||
typedef UINT WNCAN_IntType;
|
||||
|
||||
|
||||
/*Macro definitions to be used with filtering*/
|
||||
#define COMPARE_ALL_STD_IDS 0x7FF
|
||||
#define COMPARE_ALL_EXT_IDS 0x1FFFFFFF
|
||||
#define ACCEPT_ALL_STD_IDS 0
|
||||
#define ACCEPT_ALL_STD_IDS 0
|
||||
|
||||
/* STATUS error codes returned by CAN interface functions */
|
||||
#define WNCAN_NOERROR 0
|
||||
#define WNCAN_BUSY 80
|
||||
#define WNCAN_NOTINITIALIZED 81
|
||||
#define WNCAN_NULL_POINTER 82
|
||||
#define WNCAN_ILLEGAL_CHANNEL_NO 83
|
||||
#define WNCAN_ILLEGAL_CONFIG 84
|
||||
#define WNCAN_ILLEGAL_CTRL_NO 85
|
||||
#define WNCAN_ILLEGAL_BOARD_INDEX 86
|
||||
#define WNCAN_NO_OP 87
|
||||
#define WNCAN_BUFFER_UNDERFLOW 89
|
||||
#define WNCAN_BUFFER_OVERFLOW 90
|
||||
#define WNCAN_ILLEGAL_DATA_LENGTH 91
|
||||
#define WNCAN_NULL_BUFFER 92
|
||||
#define WNCAN_ILLEGAL_MASK_VALUE 93
|
||||
#define WNCAN_BUS_FAULT 94
|
||||
#define WNCAN_HWFEATURE_NOT_AVAILABLE 95
|
||||
#define WNCAN_ILLEGAL_CHANNEL_MODE 96
|
||||
#define WNCAN_RTR_MODE_NOT_SUPPORTED 97
|
||||
#define WNCAN_NO_AVAIL_CHANNELS 98
|
||||
#define WNCAN_ILLEGAL_OFFSET 101
|
||||
#define WNCAN_CANNOT_SET_ERRINT 102
|
||||
#define WNCAN_CANNOT_SET_BOFFINT 104
|
||||
#define WNCAN_CANNOT_SET_WAKEUPINT 108
|
||||
#define WNCAN_INCOMPATIBLE_TYPE 109
|
||||
#define WNCAN_SLEEP_IN_RESET_MODE 110
|
||||
#define WNCAN_USE_AUTO_RESPONSE 111
|
||||
#define WNCAN_USE_RTR_REQ_CHN_MODE 112
|
||||
#define WNCAN_TSEG_ZERO 113
|
||||
#define WNCAN_NUMTQ_LT_NINE 114
|
||||
#define WNCAN_UNKNOWN_ERROR 255
|
||||
|
||||
/* defined error codes */
|
||||
#define M_wnCan (496 << 16)
|
||||
|
||||
#define S_can_invalid_parameter (M_wnCan + 1)
|
||||
#define S_can_unknown_controller (M_wnCan + 2)
|
||||
#define S_can_invalid_timing_combination (M_wnCan + 3)
|
||||
#define S_can_out_of_memory (M_wnCan + 4)
|
||||
#define S_can_unknown_board (M_wnCan + 5)
|
||||
|
||||
#define S_can_busy (M_wnCan + WNCAN_BUSY)
|
||||
#define S_can_illegal_channel_no (M_wnCan + WNCAN_ILLEGAL_CHANNEL_NO)
|
||||
#define S_can_illegal_config (M_wnCan + WNCAN_ILLEGAL_CONFIG)
|
||||
#define S_can_illegal_ctrl_no (M_wnCan + WNCAN_ILLEGAL_CTRL_NO)
|
||||
#define S_can_illegal_board_no (M_wnCan + WNCAN_ILLEGAL_BOARD_INDEX)
|
||||
#define S_can_no_op (M_wnCan + WNCAN_NO_OP)
|
||||
#define S_can_buffer_underflow (M_wnCan + WNCAN_BUFFER_UNDERFLOW)
|
||||
#define S_can_buffer_overflow (M_wnCan + WNCAN_BUFFER_OVERFLOW)
|
||||
#define S_can_illegal_data_length (M_wnCan + WNCAN_ILLEGAL_DATA_LENGTH)
|
||||
#define S_can_null_input_buffer (M_wnCan + WNCAN_NULL_BUFFER)
|
||||
#define S_can_illegal_mask_value (M_wnCan + WNCAN_ILLEGAL_MASK_VALUE)
|
||||
#define S_can_bus_fault (M_wnCan + WNCAN_BUS_FAULT)
|
||||
#define S_can_hwfeature_not_available (M_wnCan + WNCAN_HWFEATURE_NOT_AVAILABLE)
|
||||
#define S_can_illegal_channel_mode (M_wnCan + WNCAN_ILLEGAL_CHANNEL_MODE)
|
||||
#define S_can_illegal_offset (M_wnCan + WNCAN_ILLEGAL_OFFSET)
|
||||
#define S_can_cannot_set_error_int (M_wnCan + WNCAN_CANNOT_SET_ERRINT)
|
||||
#define S_can_cannot_set_boff_int (M_wnCan + WNCAN_CANNOT_SET_BOFFINT)
|
||||
#define S_can_cannot_set_wakeup_int (M_wnCan + WNCAN_CANNOT_SET_WAKEUPINT)
|
||||
#define S_can_rtr_mode_not_supported (M_wnCan + WNCAN_RTR_MODE_NOT_SUPPORTED)
|
||||
#define S_can_no_available_channels (M_wnCan + WNCAN_NO_AVAIL_CHANNELS)
|
||||
#define S_can_incompatible_int_type (M_wnCan + WNCAN_INCOMPATIBLE_TYPE)
|
||||
#define S_can_cannot_sleep_in_reset_mode (M_wnCan + WNCAN_SLEEP_IN_RESET_MODE)
|
||||
#define S_can_use_auto_response_feature (M_wnCan + WNCAN_USE_AUTO_RESPONSE)
|
||||
#define S_can_use_rtr_requester_channel_mode (M_wnCan + WNCAN_USE_RTR_REQ_CHN_MODE)
|
||||
#define S_can_tseg2_cannot_be_zero (M_wnCan + WNCAN_TSEG_ZERO)
|
||||
#define S_can_numTq_less_than_nine (M_wnCan + WNCAN_NUMTQ_LT_NINE)
|
||||
#define S_can_Unknown_Error (M_wnCan + WNCAN_UNKNOWN_ERROR)
|
||||
|
||||
struct WNCAN_Controller;
|
||||
struct WNCAN_Board;
|
||||
|
||||
typedef struct WNCAN_Device
|
||||
{
|
||||
STATUS (*Init)(struct WNCAN_Device *p);
|
||||
|
||||
void (*Start)(struct WNCAN_Device *p);
|
||||
|
||||
void (*Stop)(struct WNCAN_Device *p);
|
||||
|
||||
STATUS (*SetIntMask)(struct WNCAN_Device *pDev, WNCAN_IntType intMask);
|
||||
|
||||
void (*EnableInt)(struct WNCAN_Device *pDev);
|
||||
|
||||
void (*DisableInt)(struct WNCAN_Device *pDev);
|
||||
|
||||
STATUS (*SetBitTiming)(struct WNCAN_Device *pDev,UCHAR tseg1,
|
||||
UCHAR tseg2,UCHAR brp,UCHAR sjw, BOOL numSamples);
|
||||
|
||||
UINT (*GetBaudRate)(struct WNCAN_Device *pDev, UINT* samplePoint);
|
||||
|
||||
WNCAN_BusStatus (*GetBusStatus)(struct WNCAN_Device *pDev);
|
||||
|
||||
WNCAN_BusError (*GetBusError)(struct WNCAN_Device *pDev);
|
||||
|
||||
WNCAN_IntType (*GetIntStatus)(struct WNCAN_Device *pDev,UCHAR *chnNum);
|
||||
|
||||
long (*ReadID)(struct WNCAN_Device *pDev,UCHAR chnNum,
|
||||
BOOL *ext);
|
||||
|
||||
STATUS (*WriteID)(struct WNCAN_Device *pDev,UCHAR chnNum,
|
||||
ULONG canID,BOOL ext);
|
||||
|
||||
STATUS (*ReadData)(struct WNCAN_Device *pDev,UCHAR chnNum,
|
||||
UCHAR *data,UCHAR *len,BOOL *newData);
|
||||
|
||||
int (*GetMessageLength)(struct WNCAN_Device *pDev,
|
||||
UCHAR chnNum);
|
||||
|
||||
STATUS (*WriteData)(struct WNCAN_Device *pDev,UCHAR chnNum,
|
||||
UCHAR* data,UCHAR len);
|
||||
|
||||
STATUS (*Tx)(struct WNCAN_Device *pDev,UCHAR chnNum);
|
||||
|
||||
STATUS (*TxMsg)(struct WNCAN_Device *pDev,UCHAR chnNum,
|
||||
ULONG canId,BOOL ext,UCHAR* data,UCHAR len);
|
||||
|
||||
STATUS (*SetGlobalRxFilter)(struct WNCAN_Device *pDev,
|
||||
long mask,BOOL ext);
|
||||
|
||||
long (*GetGlobalRxFilter)(struct WNCAN_Device *pDev, BOOL ext);
|
||||
|
||||
STATUS (*SetLocalMsgFilter)(struct WNCAN_Device *pDev,
|
||||
UCHAR channel, long mask, BOOL ext);
|
||||
|
||||
long (*GetLocalMsgFilter)(struct WNCAN_Device *pDev, UCHAR channel, BOOL ext);
|
||||
|
||||
int (*IsMessageLost)(struct WNCAN_Device *pDev,
|
||||
UCHAR chnNum);
|
||||
|
||||
STATUS (*ClearMessageLost)(struct WNCAN_Device *pDev,
|
||||
UCHAR chnNum);
|
||||
|
||||
int (*IsRTR)(struct WNCAN_Device *pDev,UCHAR chnNum);
|
||||
|
||||
STATUS (*SetRTR)(struct WNCAN_Device *pDev,UCHAR chnNum, BOOL rtr);
|
||||
|
||||
void (*TxAbort)(struct WNCAN_Device *pDev);
|
||||
|
||||
STATUS (*Sleep)(struct WNCAN_Device *pDev);
|
||||
|
||||
STATUS (*WakeUp)(struct WNCAN_Device *pDev);
|
||||
|
||||
void (*pISRCallback)(struct WNCAN_Device *pDev,
|
||||
WNCAN_IntType intStatus, UCHAR chnNum);
|
||||
|
||||
STATUS (*EnableChannel )(struct WNCAN_Device *pDev,
|
||||
UCHAR chnNum, WNCAN_IntType useInterrupts);
|
||||
|
||||
STATUS (*DisableChannel )(struct WNCAN_Device *pDev,
|
||||
UCHAR chnNum);
|
||||
|
||||
|
||||
STATUS (*WriteReg)(struct WNCAN_Device *pDev, UINT offset,
|
||||
UCHAR *data, UINT length);
|
||||
|
||||
STATUS (*ReadReg)(struct WNCAN_Device *pDev, UINT offset,
|
||||
UCHAR *data, UINT length);
|
||||
|
||||
const char *deviceName;
|
||||
UINT deviceId;
|
||||
|
||||
struct WNCAN_Controller *pCtrl;
|
||||
struct WNCAN_Board *pBrd;
|
||||
void *userData; /* user data context pointer */
|
||||
|
||||
} WNCAN_DEVICE;
|
||||
|
||||
/* function prototypes */
|
||||
STATUS CAN_InstallISRCallback(struct WNCAN_Device *pDev,
|
||||
void (*pFun)(struct WNCAN_Device *pDev2,
|
||||
WNCAN_IntType intStatus,UCHAR chnNum));
|
||||
|
||||
struct WNCAN_Device *WNCAN_Open(UINT,UINT,UINT);
|
||||
|
||||
void WNCAN_Close(struct WNCAN_Device *);
|
||||
|
||||
WNCAN_ChannelMode WNCAN_GetMode(struct WNCAN_Device *pDev, UCHAR chn);
|
||||
|
||||
STATUS WNCAN_SetMode(struct WNCAN_Device *pDev, UCHAR channelNum,
|
||||
WNCAN_ChannelMode mode);
|
||||
|
||||
STATUS WNCAN_GetTxChannel(struct WNCAN_Device *pDev,UCHAR *chnNum);
|
||||
|
||||
STATUS WNCAN_GetRxChannel(struct WNCAN_Device *pDev,UCHAR *chnNum);
|
||||
|
||||
STATUS WNCAN_GetRTRRequesterChannel(struct WNCAN_Device *pDev,UCHAR *chnNum);
|
||||
|
||||
STATUS WNCAN_GetRTRResponderChannel(struct WNCAN_Device *pDev,UCHAR *chnNum);
|
||||
|
||||
STATUS WNCAN_FreeChannel(struct WNCAN_Device *pDev,UCHAR chnNum);
|
||||
|
||||
const WNCAN_VersionInfo* WNCAN_GetVersion(void);
|
||||
|
||||
void wncan_core_init(void);
|
||||
|
||||
/* additional functions */
|
||||
#ifdef INCLUDE_TOUCAN
|
||||
STATUS TouCAN_SetPropseg(struct WNCAN_Device *pDev, UCHAR propseg);
|
||||
#endif
|
||||
|
||||
#ifdef INCLUDE_FLEXCAN
|
||||
STATUS FlexCAN_SetPropseg(struct WNCAN_Device *pDev, UCHAR propseg);
|
||||
STATUS FlexCAN_SetIntLevel(struct WNCAN_Device *pDev, UCHAR srcNum, UCHAR intLevel, UCHAR intPriorityInLevel);
|
||||
STATUS FlexCAN_GetIntLevel(struct WNCAN_Device *pDev, UCHAR srcNum, UCHAR *intLevel, UCHAR *intPriorityInLevel);
|
||||
#endif
|
||||
|
||||
/* The following Macros map the interface function calls to the implementation
|
||||
functions set by the installation routine of the device driver. */
|
||||
|
||||
/* controller independent function prototypes */
|
||||
|
||||
#define CAN_Open(a,b,c) WNCAN_Open(a,b,c)
|
||||
|
||||
#define CAN_Close(a) WNCAN_Close(a)
|
||||
|
||||
#define CAN_GetMode(a,b) WNCAN_GetMode(a,b)
|
||||
|
||||
#define CAN_SetMode(a,b,c) WNCAN_SetMode(a,b,c)
|
||||
|
||||
#define CAN_GetTxChannel(a,b) WNCAN_GetTxChannel(a,b)
|
||||
|
||||
#define CAN_GetRxChannel(a,b) WNCAN_GetRxChannel(a,b)
|
||||
|
||||
#define CAN_GetRTRResponderChannel(a,b) WNCAN_GetRTRResponderChannel(a,b)
|
||||
|
||||
#define CAN_GetRTRRequesterChannel(a,b) WNCAN_GetRTRRequesterChannel(a,b)
|
||||
|
||||
#define CAN_FreeChannel(a,b) WNCAN_FreeChannel(a,b)
|
||||
|
||||
#define CAN_GetVersion() WNCAN_GetVersion()
|
||||
|
||||
/* controller dependent function prototypes */
|
||||
|
||||
#define CAN_GetBusStatus(a) a->GetBusStatus(a)
|
||||
|
||||
#define CAN_GetBusError(a) a->GetBusError(a)
|
||||
|
||||
#define CAN_Init(a) a->Init(a)
|
||||
|
||||
#define CAN_Start(a) a->Start(a)
|
||||
|
||||
#define CAN_Stop(a) a->Stop(a)
|
||||
|
||||
#define CAN_SetBitTiming(a,b,c,d,e,f) a->SetBitTiming(a,b,c,d,e,f)
|
||||
|
||||
#define CAN_GetBaudRate(a,b) a->GetBaudRate(a,b)
|
||||
|
||||
#define CAN_SetIntMask(a,b) a->SetIntMask(a,b)
|
||||
|
||||
#define CAN_EnableInt(a) a->EnableInt(a)
|
||||
|
||||
#define CAN_DisableInt(a) a->DisableInt(a)
|
||||
|
||||
#define CAN_ReadID(a,b,c) a->ReadID(a,b,c)
|
||||
|
||||
#define CAN_WriteID(a,b,c,d) a->WriteID(a,b,c,d)
|
||||
|
||||
#define CAN_ReadData(a,b,c,d,e) a->ReadData(a,b,c,d,e)
|
||||
|
||||
#define CAN_GetMessageLength(a,b) a->GetMessageLength(a,b)
|
||||
|
||||
#define CAN_WriteData(a,b,c,d) a->WriteData(a,b,c,d)
|
||||
|
||||
#define CAN_Tx(a,b) a->Tx(a,b)
|
||||
|
||||
#define CAN_TxMsg(a,b,c,d,e,f) a->TxMsg(a,b,c,d,e,f)
|
||||
|
||||
#define CAN_SetGlobalRxFilter(a,b,c) a->SetGlobalRxFilter(a,b,c)
|
||||
|
||||
#define CAN_GetGlobalRxFilter(a,b) a->GetGlobalRxFilter(a,b)
|
||||
|
||||
#define CAN_SetLocalMsgFilter(a,b,c,d) a->SetLocalMsgFilter(a,b,c,d)
|
||||
|
||||
#define CAN_GetLocalMsgFilter(a, b, c) a->GetLocalMsgFilter(a, b, c)
|
||||
|
||||
#define CAN_GetIntStatus(a,b) a->GetIntStatus(a,b)
|
||||
|
||||
#define CAN_IsMessageLost(a,b) a->IsMessageLost(a,b)
|
||||
|
||||
#define CAN_ClearMessageLost(a,b) a->ClearMessageLost(a,b)
|
||||
|
||||
#define CAN_IsRTR(a,b) a->IsRTR(a,b)
|
||||
|
||||
#define CAN_SetRTR(a,b,c) a->SetRTR(a,b,c)
|
||||
|
||||
#define CAN_TxAbort(a) a->TxAbort(a)
|
||||
|
||||
#define CAN_Sleep(a) a->Sleep(a)
|
||||
|
||||
#define CAN_WakeUp(a) a->WakeUp(a)
|
||||
|
||||
#define CAN_WriteReg(a,b,c,d) a->WriteReg(a,b,c,d)
|
||||
|
||||
#define CAN_ReadReg(a,b,c,d) a->ReadReg(a,b,c,d)
|
||||
|
||||
#define CAN_EnableChannel(a,b,c) a->EnableChannel(a,b,c)
|
||||
#define CAN_DisableChannel(a,b) a->DisableChannel(a,b)
|
||||
|
||||
/* variable access */
|
||||
#define CAN_GetXtalFreq(a) a->pBrd->xtalFreq
|
||||
#define CAN_GetControllerType(a) a->pCtrl->ctrlType
|
||||
#define CAN_GetNumChannels(a) a->pCtrl->numChn
|
||||
#define CAN_SetSjw(a,b) (a->pCtrl->sjw = b)
|
||||
#define CAN_SetBrp(a,b) (a->pCtrl->brp = b)
|
||||
#define CAN_SetTseg1(a,b) (a->pCtrl->tseg1 = b)
|
||||
#define CAN_SetTseg2(a,b) (a->pCtrl->tseg2 = b)
|
||||
#define CAN_SetNumOfSamples(a,b) (a->pCtrl->samples = b)
|
||||
|
||||
/*These macros are provided for backward compatibility */
|
||||
#define I82527_SetMsgObj15RxFilter(a, b) \
|
||||
CAN_SetLocalMsgFilter(a,14,b,1)
|
||||
|
||||
#define TouCAN_SetMsgObj14or15RxFilter(a,b,c,d) \
|
||||
CAN_SetLocalMsgFilter(a,d,b,c)
|
||||
|
||||
#include <CAN/wncan_api.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* WN_CAN_H */
|
||||
@@ -0,0 +1,345 @@
|
||||
/* wncanDevIO.h - WIND NET CAN Device I/O Interface header file. */
|
||||
|
||||
/* Copyright 2002-2003 Wind River Systems, Inc. */
|
||||
#include "copyright_wrs.h"
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,20sep04,lsg Gave enum to setFuncSwitch an identifier
|
||||
01d,17jul04,lsg Modified _wncan_ctlrconfig to access multiple ctrlSetConfig
|
||||
functions for FlexCAN
|
||||
01c,08apr04,lsg Added FlexCAN related info to WNCAN_CTLRCONFIG
|
||||
01b,21apr04,bjn Added WNCAN_REG, WNCAN_REG_SET and WNCAN_REG_GET
|
||||
01a,19Dec02,emcw created
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
|
||||
This file contains the type and function definitions of the Device I/O Interface feature
|
||||
of WIND NET CAN.
|
||||
|
||||
NOTE
|
||||
|
||||
RESTRICTIONS
|
||||
|
||||
INCLUDE FILES
|
||||
|
||||
CAN/wnCAN.h
|
||||
*/
|
||||
|
||||
#ifndef __INCwncanDevIOh
|
||||
#define __INCwncanDevIOh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ==== Include files ==== */
|
||||
|
||||
#include <vxWorks.h>
|
||||
#include <iosLib.h>
|
||||
#include <rngLib.h>
|
||||
#include <semLib.h>
|
||||
#include <selectLib.h>
|
||||
#include <string.h>
|
||||
#include <CAN/wnCAN.h>
|
||||
|
||||
|
||||
/* ==== Constants ==== */
|
||||
|
||||
#define WNCAN_LG_BUF_SIZE 200
|
||||
#define WNCAN_MAX_DATA_LEN 8 /* max #bytes in CAN message data */
|
||||
#define WNCAN_DEFAULT_RINGBUF_SIZE 4 /* default #CAN msgs in internal buffers */
|
||||
|
||||
|
||||
/* ==== WNCAN DevIO interface ioctl() commands ==== */
|
||||
|
||||
/* Base command code */
|
||||
|
||||
#define DEVIO_CANCMD_BASE 100
|
||||
|
||||
/* Device commands */
|
||||
|
||||
#define WNCAN_HALT (DEVIO_CANCMD_BASE + 1)
|
||||
#define WNCAN_SLEEP (DEVIO_CANCMD_BASE + 2)
|
||||
#define WNCAN_WAKE (DEVIO_CANCMD_BASE + 3)
|
||||
#define WNCAN_TX_ABORT (DEVIO_CANCMD_BASE + 4)
|
||||
#define WNCAN_RXCHAN_GET (DEVIO_CANCMD_BASE + 5)
|
||||
#define WNCAN_TXCHAN_GET (DEVIO_CANCMD_BASE + 6)
|
||||
#define WNCAN_RTRREQCHAN_GET (DEVIO_CANCMD_BASE + 7)
|
||||
#define WNCAN_RTRRESPCHAN_GET (DEVIO_CANCMD_BASE + 8)
|
||||
#define WNCAN_BUSINFO_GET (DEVIO_CANCMD_BASE + 9)
|
||||
#define WNCAN_CONFIG_SET (DEVIO_CANCMD_BASE + 10)
|
||||
#define WNCAN_CONFIG_GET (DEVIO_CANCMD_BASE + 11)
|
||||
|
||||
/* Channel commands */
|
||||
|
||||
#define WNCAN_CHNCONFIG_SET (DEVIO_CANCMD_BASE + 12)
|
||||
#define WNCAN_CHNCONFIG_GET (DEVIO_CANCMD_BASE + 13)
|
||||
#define WNCAN_CHN_ENABLE (DEVIO_CANCMD_BASE + 14)
|
||||
#define WNCAN_CHN_TX (DEVIO_CANCMD_BASE + 15)
|
||||
#define WNCAN_CHNMSGLOST_GET (DEVIO_CANCMD_BASE + 16)
|
||||
#define WNCAN_CHNMSGLOST_CLEAR (DEVIO_CANCMD_BASE + 17)
|
||||
|
||||
/* Controller-specific commands */
|
||||
|
||||
#define WNCAN_CTLRCONFIG_SET (DEVIO_CANCMD_BASE + 18)
|
||||
#define WNCAN_CTLRCONFIG_GET (DEVIO_CANCMD_BASE + 19)
|
||||
/* Additinal Device commands */
|
||||
|
||||
#define WNCAN_REG_SET (DEVIO_CANCMD_BASE + 20)
|
||||
#define WNCAN_REG_GET (DEVIO_CANCMD_BASE + 21)
|
||||
|
||||
/* ==== CAN configuration access options ==== */
|
||||
|
||||
/*
|
||||
CAN device options
|
||||
Used in flags field of WNCAN_CONFIG struct
|
||||
*/
|
||||
|
||||
#define WNCAN_CFG_NONE 0 /* selects no elements */
|
||||
#define WNCAN_CFG_INFO 0x1 /* selects information elements only */
|
||||
#define WNCAN_CFG_GBLFILTER 0x2 /* selects global filter only */
|
||||
#define WNCAN_CFG_BITTIMING 0x4 /* selects bit timing only */
|
||||
#define WNCAN_CFG_ALL 0x7 /* selects all elements */
|
||||
|
||||
/*
|
||||
CAN channel options
|
||||
Used in flags field of WNCAN_CHNCONFIG struct
|
||||
*/
|
||||
|
||||
#define WNCAN_CHNCFG_NONE 0x000 /* selects no elements */
|
||||
#define WNCAN_CHNCFG_CHANNEL 0x100 /* selects channel information only */
|
||||
#define WNCAN_CHNCFG_LCLFILTER 0x200 /* selects local filter only */
|
||||
#define WNCAN_CHNCFG_RTR 0x400 /* selects RTR bit only */
|
||||
#define WNCAN_CHNCFG_MODE 0x800 /* selects channel mode only */
|
||||
#define WNCAN_CHNCFG_ALL 0xF00 /* selects all elements */
|
||||
|
||||
|
||||
/* ==== Structures used for setting/getting CAN configuration ==== */
|
||||
|
||||
/* CAN bus information */
|
||||
|
||||
typedef struct _wncan_businfo
|
||||
{
|
||||
WNCAN_BusStatus busStatus; /* bus status */
|
||||
WNCAN_BusError busError; /* bus error */
|
||||
} WNCAN_BUSINFO;
|
||||
|
||||
|
||||
/* CAN device configuration options */
|
||||
|
||||
typedef struct _wncan_config
|
||||
{
|
||||
UINT flags; /* access options */
|
||||
|
||||
/* read-only items */
|
||||
struct
|
||||
{
|
||||
WNCAN_VersionInfo version; /* WNC version */
|
||||
WNCAN_ControllerType ctrlType; /* CAN controller type */
|
||||
XtalFreq xtalfreq; /* crystal frequency */
|
||||
UCHAR numChannels; /* total # of channels */
|
||||
UINT baudRate; /* computed baudrate bits/sec */
|
||||
UINT samplePoint; /* percentage of bit time at
|
||||
which the bit is sampled.*/
|
||||
} info;
|
||||
|
||||
/* read/write items */
|
||||
struct
|
||||
{
|
||||
ULONG mask; /* filter mask */
|
||||
BOOL extended; /* extended flag */
|
||||
} filter;
|
||||
|
||||
struct
|
||||
{
|
||||
UCHAR tseg1; /* time quanta for segment 1 */
|
||||
UCHAR tseg2; /* time quanta for segment 2 */
|
||||
UCHAR brp; /* baud rate prescaler */
|
||||
UCHAR sjw; /* syncro jump width */
|
||||
BOOL oversample; /* normal or over-sampling option */
|
||||
} bittiming;
|
||||
|
||||
} WNCAN_CONFIG;
|
||||
|
||||
|
||||
/* CAN device register get/set configuration */
|
||||
|
||||
typedef struct _wncan_reg
|
||||
{
|
||||
UINT offset; /* Register offset from base to access */
|
||||
UCHAR * pData; /* Pointer to data buffer for read/write */
|
||||
UINT length; /* Length of data in bytes to read/write */
|
||||
} WNCAN_REG;
|
||||
|
||||
|
||||
/* CAN channel configuration options */
|
||||
|
||||
typedef struct _wncan_chnconfig
|
||||
{
|
||||
UINT flags; /* access options */
|
||||
|
||||
/* local filter mask */
|
||||
struct
|
||||
{
|
||||
ULONG mask; /* filter mask */
|
||||
BOOL extended; /* extended flag */
|
||||
} filter;
|
||||
|
||||
struct
|
||||
{
|
||||
ULONG id; /* CAN ID */
|
||||
BOOL extId; /* is ID extended or not? */
|
||||
UCHAR len; /* length */
|
||||
UCHAR data[WNCAN_MAX_DATA_LEN]; /* message data */
|
||||
} channel;
|
||||
|
||||
BOOL rtr; /* RTR bit setting */
|
||||
WNCAN_ChannelMode mode; /* channel mode */
|
||||
|
||||
} WNCAN_CHNCONFIG;
|
||||
|
||||
|
||||
/* CAN controller-specific configuration options */
|
||||
|
||||
typedef struct _wncan_ctlrconfig
|
||||
{
|
||||
WNCAN_ControllerType ctlrType;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
UCHAR propseg; /* propagation segment */
|
||||
} toucanData;
|
||||
|
||||
struct
|
||||
{
|
||||
struct intLevelInfo_t{
|
||||
UCHAR intSrcNum; /*flexcan interrupt source number, always an input for WNCAN_CTLRCONFIG_SET
|
||||
and WNCAN_CTLRCONFIG_GET */
|
||||
UCHAR intLevel; /*flexcan interrupt level, for WNCAN_CTLRCONFIG_SET: input,
|
||||
for WNCAN_CTLRCONFIG_GET: output */
|
||||
UCHAR intPrioLevel;/* priority within interrupt level, for WNCAN_CTLRCONFIG_SET: input,
|
||||
for WNCAN_CTLRCONFIG_GET: output */
|
||||
} intLevelInfo;
|
||||
|
||||
UCHAR propseg;
|
||||
|
||||
enum setFuncSwitch_t{
|
||||
WNCAN_FLEXCAN_DEVIO_SET_INTLEVEL=0,
|
||||
WNCAN_FLEXCAN_DEVIO_SET_PROPSEG
|
||||
}setFuncSwitch;
|
||||
|
||||
} flexcanData;
|
||||
|
||||
/* Other controller-specific structs can be defined here */
|
||||
ULONG dummy; /* placeholder for future defs */
|
||||
|
||||
} ctlrData;
|
||||
|
||||
} WNCAN_CTLRCONFIG;
|
||||
|
||||
/* CAN message */
|
||||
|
||||
typedef struct _wncan_chnmsg
|
||||
{
|
||||
ULONG id; /* CAN ID */
|
||||
BOOL extId; /* is ID extended or not? */
|
||||
BOOL rtr; /* remote frame transmit request */
|
||||
UCHAR len; /* message length */
|
||||
UCHAR data[WNCAN_MAX_DATA_LEN]; /* message data */
|
||||
} WNCAN_CHNMSG;
|
||||
|
||||
|
||||
|
||||
/* ==== Internal Device I/O Structures (maybe move to private header file?) ==== */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FD_WNCAN_NONE,
|
||||
FD_WNCAN_DEVICE,
|
||||
FD_WNCAN_CHANNEL
|
||||
} WNCAN_FD_TYPE;
|
||||
|
||||
|
||||
typedef STATUS (*CTRLRCONFIGFNTYPE)(void*, void*);
|
||||
|
||||
typedef struct /* DevIO driver information */
|
||||
{
|
||||
DEV_HDR devHdr; /* standard I/O System device header */
|
||||
WNCAN_BoardType boardType; /* CAN board type */
|
||||
int boardIdx; /* CAN board index */
|
||||
int ctlrIdx; /* CAN controller index */
|
||||
int numOpenChans; /* number of open CAN channels */
|
||||
BOOL isDeviceOpen; /* whether CAN device has been init'ed;
|
||||
set after CAN_Init() called */
|
||||
SEM_ID mutex; /* mutex semaphore for memory access */
|
||||
WNCAN_DEVICE *wncDevice; /* WNCAN device data structure */
|
||||
|
||||
CTRLRCONFIGFNTYPE ctrlSetConfig; /* controller-specific functions */
|
||||
CTRLRCONFIGFNTYPE ctrlGetConfig;
|
||||
|
||||
} WNCAN_DEVIO_DRVINFO;
|
||||
|
||||
|
||||
typedef struct _devio_fdinfo /* DevIO file descriptor table info */
|
||||
{
|
||||
WNCAN_DEVIO_DRVINFO* wnDevIODrv; /* pointer to WNCAN_DEVIO_DRVINFO struct */
|
||||
WNCAN_FD_TYPE devType; /* indicates which type of data stored here,
|
||||
device or channel */
|
||||
SEL_WAKEUP_LIST selWakeupList; /* wakeup select list */
|
||||
|
||||
union
|
||||
{
|
||||
/* CAN device info */
|
||||
struct {
|
||||
struct _devio_fdinfo **chnInfo; /* allocated channel infos */
|
||||
} device;
|
||||
|
||||
/* CAN channel info */
|
||||
struct {
|
||||
BOOL enabled; /* channel up and running flag */
|
||||
int flag; /* channel access flag */
|
||||
ULONG channel; /* channel identifier */
|
||||
WNCAN_IntType intType; /* interrupt status type, WNCAN_INT_TX
|
||||
or WNCAN_INT_RX */
|
||||
RING_ID inputBuf; /* input data buffer */
|
||||
RING_ID outputBuf; /* output data buffer */
|
||||
} channel;
|
||||
} fdtype;
|
||||
|
||||
} WNCAN_DEVIO_FDINFO;
|
||||
|
||||
|
||||
/* ==== Function Prototypes ==== */
|
||||
|
||||
#if defined(__STDC__)
|
||||
extern STATUS wncDevIODevCreate(char*,int,int,int,WNCAN_DEVIO_DRVINFO**);
|
||||
extern int wncDevIOCreate(WNCAN_DEVIO_DRVINFO*, char*, int);
|
||||
extern int wncDevIODelete(WNCAN_DEVIO_DRVINFO*, char*);
|
||||
extern int wncDevIOOpen(WNCAN_DEVIO_DRVINFO*, char*, int, int);
|
||||
extern STATUS wncDevIOClose(WNCAN_DEVIO_FDINFO*);
|
||||
extern int wncDevIOReadBuf(WNCAN_DEVIO_FDINFO*, char*, size_t);
|
||||
extern int wncDevIOWriteBuf(WNCAN_DEVIO_FDINFO*, char*, size_t);
|
||||
STATUS wncDevIOIoctl(WNCAN_DEVIO_FDINFO*, int, int);
|
||||
#else
|
||||
extern STATUS wncDevIODevCreate();
|
||||
extern int wncDevIOCreate();
|
||||
extern int wncDevIODelete();
|
||||
extern int wncDevIOOpen();
|
||||
extern STATUS wncDevIOClose();
|
||||
extern int wncDevIOReadBuf();
|
||||
extern int wncDevIOWriteBuf();
|
||||
STATUS wncDevIOIoctl();
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCwncanDevIOh */
|
||||
@@ -0,0 +1,203 @@
|
||||
/* wncan_api.h - Wind River's CAN Common API header file. */
|
||||
|
||||
/* Copyright 1984-2001 Wind River Systems, Inc. */
|
||||
#include "copyright_wrs.h"
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01, 18Dec01, jac created
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
|
||||
This file contains the function definitions of Wind River's CAN Common API.
|
||||
|
||||
NOTE
|
||||
|
||||
For normal usage, these function calls are replaced by equivalent macro
|
||||
definitions in CAN/wnCAN.h
|
||||
|
||||
RESTRICTIONS
|
||||
|
||||
INCLUDE FILES
|
||||
|
||||
CAN/wnCAN.h
|
||||
CAN/canBoard.h
|
||||
|
||||
*/
|
||||
|
||||
#ifndef WNCAN_API_H
|
||||
#define WNCAN_API_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Uncomment the next line if you want to use actual function
|
||||
definitions for the CAN Common API */
|
||||
/* #define USE_CAN_FUNCTION_DEFS */
|
||||
|
||||
#ifdef USE_CAN_FUNCTION_DEFS
|
||||
#undef CAN_Open
|
||||
#undef CAN_Close
|
||||
#undef CAN_GetMode
|
||||
#undef CAN_SetMode
|
||||
#undef CAN_GetTxChannel
|
||||
#undef CAN_GetRxChannel
|
||||
#undef CAN_GetRTRRequesterChannel
|
||||
#undef CAN_GetRTRResponderChannel
|
||||
#undef CAN_FreeChannel
|
||||
#undef CAN_GetVersion
|
||||
#undef CAN_GetBusStatus
|
||||
#undef CAN_GetBusError
|
||||
#undef CAN_Init
|
||||
#undef CAN_Start
|
||||
#undef CAN_Stop
|
||||
#undef CAN_SetBitTiming
|
||||
#undef CAN_GetBaudRate
|
||||
#undef CAN_SetIntMask
|
||||
#undef CAN_EnableInt
|
||||
#undef CAN_DisableInt
|
||||
#undef CAN_ReadID
|
||||
#undef CAN_WriteID
|
||||
#undef CAN_ReadData
|
||||
#undef CAN_GetMessageLength
|
||||
#undef CAN_WriteData
|
||||
#undef CAN_Tx
|
||||
#undef CAN_TxMsg
|
||||
#undef CAN_SetGlobalRxFilter
|
||||
#undef CAN_GetGlobalRxFilter
|
||||
#undef CAN_SetLocalMsgFilter
|
||||
#undef CAN_GetLocalMsgFilter
|
||||
#undef CAN_GetIntStatus
|
||||
#undef CAN_IsMessageLost
|
||||
#undef CAN_ClearMessageLost
|
||||
#undef CAN_SetRTR
|
||||
#undef CAN_IsRTR
|
||||
#undef CAN_TxAbort
|
||||
#undef CAN_Sleep
|
||||
#undef CAN_WakeUp
|
||||
#undef CAN_EnableChannel
|
||||
#undef CAN_DisableChannel
|
||||
#undef CAN_WriteReg
|
||||
#undef CAN_ReadReg
|
||||
|
||||
/* variable access */
|
||||
#undef CAN_GetXtalFreq
|
||||
#undef CAN_GetControllerType
|
||||
#undef CAN_GetNumChannels
|
||||
|
||||
/* controller independent function prototypes */
|
||||
struct WNCAN_Device *CAN_Open(unsigned int brdType, unsigned int brdNdx,
|
||||
unsigned int ctrlNdx);
|
||||
|
||||
void CAN_Close(struct WNCAN_Device *pDev);
|
||||
|
||||
WNCAN_ChannelMode CAN_GetMode(struct WNCAN_Device *pDev, UCHAR chn);
|
||||
|
||||
STATUS CAN_SetMode(struct WNCAN_Device *pDev, UCHAR channelNum,
|
||||
WNCAN_ChannelMode mode);
|
||||
|
||||
STATUS CAN_GetTxChannel(struct WNCAN_Device *pDev, UCHAR *channelNum);
|
||||
|
||||
STATUS CAN_GetRxChannel(struct WNCAN_Device *pDev, UCHAR *channelNum);
|
||||
|
||||
STATUS CAN_GetRTRRequesterChannel(struct WNCAN_Device *pDev, UCHAR *channelNum);
|
||||
|
||||
STATUS CAN_GetRTRResponderChannel(struct WNCAN_Device *pDev, UCHAR *channelNum);
|
||||
|
||||
STATUS CAN_FreeChannel(struct WNCAN_Device *pDev, UCHAR channelNum);
|
||||
|
||||
const WNCAN_VersionInfo* CAN_GetVersion(void);
|
||||
|
||||
/* controller dependent function prototypes */
|
||||
|
||||
WNCAN_BusStatus CAN_GetBusStatus(struct WNCAN_Device *pDev);
|
||||
|
||||
WNCAN_BusError CAN_GetBusError(struct WNCAN_Device *pDev);
|
||||
|
||||
STATUS CAN_Init(struct WNCAN_Device *pDev);
|
||||
|
||||
void CAN_Start(struct WNCAN_Device *pDev);
|
||||
|
||||
void CAN_Stop(struct WNCAN_Device *pDev);
|
||||
|
||||
STATUS CAN_SetBitTiming(struct WNCAN_Device *pDev, UCHAR tseg1, UCHAR tseg2,
|
||||
UCHAR brp, UCHAR sjw, BOOL numSamples);
|
||||
|
||||
UINT CAN_GetBaudRate(struct WNCAN_Device *pDev, UINT* samplePoint);
|
||||
|
||||
STATUS CAN_SetIntMask(struct WNCAN_Device *pDev, WNCAN_IntType intMask);
|
||||
|
||||
void CAN_EnableInt(struct WNCAN_Device *pDev);
|
||||
|
||||
void CAN_DisableInt(struct WNCAN_Device *pDev);
|
||||
|
||||
long CAN_ReadID(struct WNCAN_Device *pDev, UCHAR channelNum, BOOL* ext);
|
||||
|
||||
STATUS CAN_WriteID(struct WNCAN_Device *pDev, UCHAR chnNum, ULONG canID, BOOL ext);
|
||||
|
||||
STATUS CAN_ReadData(struct WNCAN_Device *pDev, UCHAR chnNum, UCHAR *data,
|
||||
UCHAR *len, BOOL *newData);
|
||||
|
||||
int CAN_GetMessageLength(struct WNCAN_Device *pDev, UCHAR channelNum);
|
||||
|
||||
STATUS CAN_WriteData(struct WNCAN_Device *pDev, UCHAR channelNum,
|
||||
UCHAR *data, UCHAR len);
|
||||
|
||||
STATUS CAN_Tx(struct WNCAN_Device *pDev, UCHAR channelNum);
|
||||
|
||||
STATUS CAN_TxMsg(struct WNCAN_Device *pDev, UCHAR channelNum, ULONG canId,
|
||||
BOOL ext, UCHAR *data, UCHAR len);
|
||||
|
||||
STATUS CAN_SetGlobalRxFilter(struct WNCAN_Device *pDev, long mask, BOOL ext);
|
||||
|
||||
long CAN_GetGlobalRxFilter(struct WNCAN_Device *pDev, BOOL ext);
|
||||
|
||||
STATUS CAN_SetLocalMsgFilter(struct WNCAN_Device *pDev, UCHAR channel, long mask, BOOL ext);
|
||||
|
||||
long CAN_GetLocalMsgFilter(struct WNCAN_Device *pDev, UCHAR channel, BOOL ext);
|
||||
|
||||
WNCAN_IntType CAN_GetIntStatus(struct WNCAN_Device *pDev, UCHAR *channelNum);
|
||||
|
||||
int CAN_IsMessageLost(struct WNCAN_Device *pDev, UCHAR channelNum);
|
||||
|
||||
STATUS CAN_ClearMessageLost(struct WNCAN_Device *pDev, UCHAR channelNum);
|
||||
|
||||
STATUS CAN_SetRTR(struct WNCAN_Device *pDev, UCHAR channelNum, BOOL rtr);
|
||||
|
||||
int CAN_IsRTR(struct WNCAN_Device *pDev, UCHAR channelNum);
|
||||
|
||||
void CAN_TxAbort(struct WNCAN_Device *pDev);
|
||||
|
||||
STATUS CAN_Sleep(struct WNCAN_Device *pDev);
|
||||
|
||||
STATUS CAN_WakeUp(struct WNCAN_Device *pDev);
|
||||
|
||||
STATUS CAN_EnableChannel(struct WNCAN_Device *pDev, UCHAR channelNum,
|
||||
WNCAN_IntType intSetting);
|
||||
|
||||
STATUS CAN_DisableChannel(struct WNCAN_Device *pDev, UCHAR channelNum);
|
||||
|
||||
STATUS CAN_WriteReg(struct WNCAN_Device *pDev, UINT offset,
|
||||
UCHAR *data, UINT length);
|
||||
|
||||
STATUS CAN_ReadReg(struct WNCAN_Device *pDev, UINT offset,
|
||||
UCHAR *data, UINT length);
|
||||
|
||||
XtalFreq CAN_GetXtalFreq(struct WNCAN_Device *pDev);
|
||||
|
||||
WNCAN_ControllerType CAN_GetControllerType(struct WNCAN_Device *pDev);
|
||||
|
||||
UCHAR CAN_GetNumChannels(struct WNCAN_Device *pDev);
|
||||
|
||||
#endif /* USE_CAN_FUNCTION_DEFS */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* WNCAN_API_H */
|
||||
@@ -0,0 +1,200 @@
|
||||
/* a_out.h - a.out object module header */
|
||||
|
||||
/* Copyright 1984-1992 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01p,22sep92,rrr added support for c++
|
||||
01o,04jul92,jcf cleaned up.
|
||||
01n,19jun92,rrr changed UINT to unsigned to work with the hsp stuff
|
||||
01m,26may92,rrr the tree shuffle
|
||||
-moved define of a_machtype into else part of HOST_SUN
|
||||
01l,15may92,jmm changed UINT8 bitfields to unsigned
|
||||
removed a comma from SPARC enum
|
||||
01k,04oct91,rrr passed through the ansification filter
|
||||
-fixed #else and #endif
|
||||
-changed TINY and UTINY to INT8 and UINT8
|
||||
-changed copyright notice
|
||||
01j,03sep91,wmd removed typedef of NLIST, put back inadvertently by last revision.
|
||||
01i,02aug91,ajm added mips target support
|
||||
01h,21may91,jcc removed useless typedef of NLIST, identical to nlist.
|
||||
01g,15may91,elr added #ifdef HOST_MOTOROLA
|
||||
01f,05oct90,shl added copyright notice.
|
||||
made #endif ANSI style.
|
||||
01e,05oct90,lpf added N_DATOFF macro.
|
||||
01d,30apr90,gae added kludge of a_machtype for HOST_HP.
|
||||
01c,11sep89,shl removed some of the #ifdef HOST_SUN so vxWorks can be
|
||||
made on other hosts as well.
|
||||
added #ifdef HOST_ISI.
|
||||
01b,19apr89,ecs conditional to reflect SunOS 4.0.
|
||||
01a,16feb87,llk created.
|
||||
*/
|
||||
|
||||
/*
|
||||
This file reflects Unix 4.2 a.out format.
|
||||
*/
|
||||
|
||||
#ifndef __INCa_outh
|
||||
#define __INCa_outh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct exec
|
||||
{
|
||||
#if defined(HOST_SUN)
|
||||
unsigned a_dynamic:1; /* has a __DYNAMIC */
|
||||
unsigned a_toolversion:7; /* version of toolset used to create file */
|
||||
unsigned a_machtype: 8; /* machine type */
|
||||
unsigned a_magic:16; /* magic number */
|
||||
#else
|
||||
long a_magic; /* magic number */
|
||||
#define a_machtype a_magic
|
||||
#endif /* HOST_SUN */
|
||||
|
||||
unsigned long a_text; /* size of text segment */
|
||||
unsigned long a_data; /* size of initialized data */
|
||||
unsigned long a_bss; /* size of uninitialized data */
|
||||
unsigned long a_syms; /* size of symbol table */
|
||||
unsigned long a_entry; /* entry point */
|
||||
unsigned long a_trsize; /* size of text relocation */
|
||||
unsigned long a_drsize; /* size of data relocation */
|
||||
};
|
||||
|
||||
|
||||
/* machine types */
|
||||
|
||||
#define M_OLDSUN2 0 /* old sun-2 (or not sun at all) */
|
||||
#define M_68010 1 /* runs on either 68010 or 68020 */
|
||||
#define M_68020 2 /* runs only on 68020 */
|
||||
#define M_SPARC 3 /* runs only on SPARC */
|
||||
#define M_R3000 4 /* runs only on R3000 */
|
||||
|
||||
#define ZMAGIC 0413 /* demand load format */
|
||||
|
||||
/*
|
||||
* Macros which take exec structures as arguments and tell whether
|
||||
* the file has a reasonable magic number or offsets to text|symbols|strings.
|
||||
*/
|
||||
|
||||
#define N_OLDOFF(x) \
|
||||
((x).a_magic==ZMAGIC ? 0 : sizeof (struct exec))
|
||||
|
||||
#define N_TXTOFF(x) \
|
||||
(sizeof (struct exec))
|
||||
|
||||
#define N_DATOFF(x) \
|
||||
(N_TXTOFF(x) + (x).a_text)
|
||||
|
||||
#define N_SYMOFF(x) \
|
||||
(N_OLDOFF(x) + (x).a_text+(x).a_data + (x).a_trsize+(x).a_drsize)
|
||||
|
||||
#define N_STROFF(x) \
|
||||
(N_SYMOFF(x) + (x).a_syms)
|
||||
|
||||
typedef struct /* RINFO_68K - 680X0 relocation datum (a_machtype != M_SPARC) */ {
|
||||
unsigned r_address; /* address which is relocated */
|
||||
unsigned r_symbolnum:24; /* local symbol ordinal */
|
||||
unsigned r_pcrel : 1; /* was relocated pc relative already */
|
||||
unsigned r_length : 2; /* 0=byte, 1=word, 2=long */
|
||||
unsigned r_extern : 1; /* does not include value of sym referenced */
|
||||
unsigned r_baserel : 1; /* linkage table relative */
|
||||
unsigned r_jmptable : 1; /* pc-relative to jump table */
|
||||
unsigned r_relative : 1; /* relative relocation */
|
||||
unsigned : 1; /* <unused> */
|
||||
} RINFO_68K;
|
||||
|
||||
|
||||
typedef enum /* RTYPE_SPARC - sparc relocation types */
|
||||
{
|
||||
RELOC_8, RELOC_16, RELOC_32, /* simplest relocs */
|
||||
RELOC_DISP8, RELOC_DISP16, RELOC_DISP32, /* Disp's (pc-rel) */
|
||||
RELOC_WDISP30, RELOC_WDISP22, /* SR word disp's */
|
||||
RELOC_HI22, RELOC_22, /* SR 22-bit relocs */
|
||||
RELOC_13, RELOC_LO10, /* SR 13&10-bit relocs*/
|
||||
RELOC_SFA_BASE, RELOC_SFA_OFF13, /* SR S.F.A. relocs */
|
||||
RELOC_BASE10, RELOC_BASE13, RELOC_BASE22, /* base_relative pic */
|
||||
RELOC_PC10, RELOC_PC22, /* special pc-rel pic */
|
||||
RELOC_JMP_TBL, /* jmp_tbl_rel in pic */
|
||||
RELOC_SEGOFF16, /* ShLib offset-in-seg*/
|
||||
RELOC_GLOB_DAT, RELOC_JMP_SLOT, RELOC_RELATIVE /* rtld relocs */
|
||||
} RTYPE_SPARC;
|
||||
|
||||
|
||||
typedef struct /* RINFO_SPARC - sparc reloc datum (a_machtype == M_SPARC) */
|
||||
{
|
||||
unsigned r_address; /* relocation addr (offset in segment)*/
|
||||
unsigned r_index :24; /* segment index or symbol index */
|
||||
unsigned r_extern : 1; /* if F, r_index==SEG#; if T, SYM idx */
|
||||
unsigned : 2; /* <unused> */
|
||||
unsigned r_type : 5; /* type of relocation to perform */
|
||||
long r_addend; /* addend for relocation value */
|
||||
} RINFO_SPARC;
|
||||
|
||||
typedef struct /* RINFO_MIPS - mips reloc datum (a_machtype == M_R3000) */
|
||||
{
|
||||
int r_address; /* address which is relocated */
|
||||
unsigned int
|
||||
r_symbolnum:24, /* local symbol ordinal */
|
||||
r_pcrel:1, /* was relocated pc relative already */
|
||||
r_length:2, /* 0=byte, 1=word, 2=long */
|
||||
r_extern:1, /* does not include value of sym referenced */
|
||||
r_type:4; /* relocation type */
|
||||
} RINFO_MIPS;
|
||||
|
||||
/*
|
||||
* Format of a symbol table entry; this file is included by <a.out.h>
|
||||
* and should be used if you aren't interested the a.out header
|
||||
* or relocation information.
|
||||
*/
|
||||
|
||||
struct nlist
|
||||
{
|
||||
union
|
||||
{
|
||||
char *n_name; /* for use when in-core */
|
||||
long n_strx; /* index into file string table */
|
||||
} n_un;
|
||||
unsigned char n_type; /* type flag, i.e. N_TEXT etc; see below */
|
||||
char n_other; /* unused */
|
||||
short n_desc; /* see <stab.h> */
|
||||
unsigned long n_value; /* value of this symbol (or sdb offset) */
|
||||
};
|
||||
|
||||
#define n_hash n_desc /* used internally by ld */
|
||||
|
||||
/*
|
||||
* Simple values for n_type.
|
||||
*/
|
||||
|
||||
#define N_UNDF 0x0 /* undefined */
|
||||
#define N_ABS 0x2 /* absolute */
|
||||
#define N_TEXT 0x4 /* text */
|
||||
#define N_DATA 0x6 /* data */
|
||||
#define N_BSS 0x8 /* bss */
|
||||
#define N_COMM 0x12 /* common (internal to ld) */
|
||||
#define N_FN 0x1f /* file name symbol */
|
||||
|
||||
#define N_EXT 01 /* external bit, or'ed in */
|
||||
#define N_TYPE 0x1e /* mask for all the type bits */
|
||||
|
||||
/*
|
||||
* Sdb entries have some of the N_STAB bits set.
|
||||
* These are given in <stab.h>
|
||||
*/
|
||||
|
||||
#define N_STAB 0xe0 /* if any of these bits set, a SDB entry */
|
||||
|
||||
/*
|
||||
* Format for namelist values.
|
||||
*/
|
||||
|
||||
#define N_FORMAT "%08x"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCa_outh */
|
||||
@@ -0,0 +1,116 @@
|
||||
/* adrSpaceLib.h - Address Space Library header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1998-2005, 2008-2010, 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01z,19jun12,zl added physContigPages to ADR_SPACE_INFO (WIND00354507).
|
||||
01y,29apr10,pad Moved extern C statement after include statements.
|
||||
01x,29jun09,zl updated for LP64 build.
|
||||
01w,26sep08,pcs Added S_adrSpaceLib_MMU_NOT_ENABLED
|
||||
01v,23jul08,pad Added prototype of adrSpaceIsOverlapped().
|
||||
01u,08sep05,zl added adrSpaceVirtReserve() and adrSpaceRAMReserve()
|
||||
prototypes
|
||||
01t,07jul05,zl added new errno-s.
|
||||
01s,22sep04,zl more comments
|
||||
01r,31aug04,zl moved private APIs to private header file
|
||||
01q,07jun04,tam added definition for option ADR_SPACE_OPT_RTP
|
||||
01p,15apr04,yp Adding sysPhysMemDesc and numElems to ADR_SPACE_INFO for
|
||||
testing
|
||||
Added prototype for adrSpaceRAMAddToPool()
|
||||
01o,05apr04,yp reworking adrSpaceLibInit call
|
||||
01n,18mar04,yp removing unused prototype adrSpaceReserve
|
||||
adding the kernel virtual page pool ID to ADR_SPACE_INFO
|
||||
adding adrSpaceLibInit params to ADR_SPACE_INFO
|
||||
01m,25nov03,yp using reserved field in page pool options for kernel space
|
||||
01m,30nov03,yp adding error ADDRESS_OUT_OF_RANGE and removing PD related
|
||||
errors; fixing prototype for adrSpaceLibInit;
|
||||
01l,11nov03,yp adjusting ADR_SPACE_INFO structure for base 6
|
||||
01k,16oct03,yp proted to base 6
|
||||
01j,31aug00,pfl added S_adrSpaceLib_ALLOC_UNIT_IS_INVALID
|
||||
01i,17aug00,tam added ADR_SPACE_OPT_KERNEL_PD
|
||||
01h,13jun99,map added master page pools to ADR_SPACE_INFO struct.
|
||||
01g,27mar00,map support for shared library and IO address space.
|
||||
01f,05nov99,map added support for virtual regions.
|
||||
01e,30apr99,map added support for appl PD region. removed sub-region support.
|
||||
01d,28apr99,wkn added #include pgPoolLibP.h
|
||||
01c,06apr99,map added adrSpace options, fixed prototypes.
|
||||
01b,08feb99,tam added adrSpaceBaseGet().
|
||||
01a,16sep98,map written.
|
||||
*/
|
||||
|
||||
#ifndef __INCadrSpaceLibh
|
||||
#define __INCadrSpaceLibh
|
||||
|
||||
/* includes */
|
||||
|
||||
#include <vxWorks.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* errnos */
|
||||
|
||||
#define S_adrSpaceLib_LIB_NOT_INITIALIZED (M_adrSpaceLib | 1)
|
||||
#define S_adrSpaceLib_CANNOT_REINITIALIZE (M_adrSpaceLib | 2)
|
||||
#define S_adrSpaceLib_PARAMETER_NOT_ALIGNED (M_adrSpaceLib | 3)
|
||||
#define S_adrSpaceLib_REGION_NOT_AVAILABLE (M_adrSpaceLib | 4)
|
||||
#define S_adrSpaceLib_VIRT_ADRS_NOT_ALIGNED (M_adrSpaceLib | 5)
|
||||
#define S_adrSpaceLib_SIZE_IS_INVALID (M_adrSpaceLib | 6)
|
||||
#define S_adrSpaceLib_INVALID_PARAMETER (M_adrSpaceLib | 7)
|
||||
#define S_adrSpaceLib_VIRTUAL_OVERLAP (M_adrSpaceLib | 8)
|
||||
#define S_adrSpaceLib_PHYSICAL_OVERLAP (M_adrSpaceLib | 9)
|
||||
#define S_adrSpaceLib_ADDRESS_OUT_OF_RANGE (M_adrSpaceLib |10)
|
||||
#define S_adrSpaceLib_INSUFFICIENT_SPACE_IN_RGN (M_adrSpaceLib |11)
|
||||
#define S_adrSpaceLib_REGION_CONFLICT (M_adrSpaceLib |12)
|
||||
#define S_adrSpaceLib_MMU_LESS_NONIDENTITY (M_adrSpaceLib |13)
|
||||
#define S_adrSpaceLib_NO_PHYS_PAGES (M_adrSpaceLib |14)
|
||||
#define S_adrSpaceLib_NO_CONTIG_PHYS_PAGES (M_adrSpaceLib |15)
|
||||
#define S_adrSpaceLib_MMU_NOT_ENABLED (M_adrSpaceLib |16)
|
||||
#define S_adrSpaceLib_INVALID_REGION (M_adrSpaceLib |17)
|
||||
#define S_adrSpaceLib_REGION_NOT_CONFIGURED (M_adrSpaceLib |18)
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* typedefs */
|
||||
|
||||
typedef struct adr_space_info
|
||||
{
|
||||
size_t physAllocUnit; /* physical space allocation unit */
|
||||
size_t physTotalPages; /* total system RAM physical pages*/
|
||||
size_t physFreePages; /* unmapped system RAM physical pages */
|
||||
size_t physMaxSize; /* largest unmapped RAM block */
|
||||
size_t physContigPages; /* largest unmapped RAM block in pages */
|
||||
size_t kernelAllocUnit; /* kernel region allocation unit */
|
||||
size_t kernelTotalPages; /* kernel region total pages */
|
||||
size_t kernelFreePages; /* kernel region unmapped pages */
|
||||
size_t kernelMaxSize; /* largest unmapped blk in kernel rgn */
|
||||
size_t userAllocUnit; /* user region allocation unit */
|
||||
size_t userTotalPages; /* user region total pages */
|
||||
size_t userFreePages; /* user region unmapped pages */
|
||||
size_t userMaxSize; /* largest unmapped blk in user rgn */
|
||||
} ADR_SPACE_INFO;
|
||||
|
||||
/* function prototypes */
|
||||
|
||||
extern STATUS adrSpaceInfoGet (ADR_SPACE_INFO *pInfo);
|
||||
extern STATUS adrSpaceRAMAddToPool (PHYS_ADDR startAddr, size_t size);
|
||||
extern PHYS_ADDR adrSpaceRAMReserve (PHYS_ADDR startAddr, size_t size);
|
||||
extern VIRT_ADDR adrSpaceVirtReserve (VIRT_ADDR startAddr, size_t numPages);
|
||||
extern BOOL adrSpaceIsOverlapped (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCadrSpaceLibh */
|
||||
@@ -0,0 +1,28 @@
|
||||
/* adrSpaceShow.h - address space show library header file */
|
||||
|
||||
/* Copyright 2000-1004 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,31aug04,zl moved private APIs to private header file
|
||||
01b,12nov03,yp adding declaration for init routine
|
||||
01a,12jun00,map written.
|
||||
*/
|
||||
|
||||
#ifndef __INCadrSpaceShowLibh
|
||||
#define __INCadrSpaceShowLibh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* funtion declarations */
|
||||
|
||||
extern STATUS adrSpaceShow (UINT level);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCadrSpaceShowLibh */
|
||||
@@ -0,0 +1,265 @@
|
||||
/* aimCacheLib.h - AIM header for Cache Functions */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2003, 2005, 2008, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01k,27may10,pad Added 'extern C' statement.
|
||||
01j,27aug08,jpb Renamed VSB header file
|
||||
01i,18jun08,jpb Added include path for kernel configurations options set in
|
||||
vsb.
|
||||
01h,08may08,jpb Modifications for source build. Renamed INCLUDE_MEM_ALLOT to
|
||||
_WRS_CONFIG_MEM_ALLOT.
|
||||
01g,24aug05,h_k converted INCLUDE_CACHE_xxx to arch feature.
|
||||
01f,19jul05,mil Scaled out features for minimal kernel.
|
||||
01e,19nov03,scm flush out cache AIM lock/unlock...
|
||||
01d,22oct03,jb Incorporating changes from inspection
|
||||
01d,24sep03,jb Continuing Development
|
||||
01c,09jun03,jb Continue development
|
||||
01b,01may03,jb Continue development
|
||||
01a,04apr03,jb written
|
||||
*/
|
||||
|
||||
#ifndef __INCaimCacheLibh
|
||||
#define __INCaimCacheLibh
|
||||
|
||||
/* Includes Section */
|
||||
|
||||
#include <vsbConfig.h>
|
||||
|
||||
#include <cacheLib.h>
|
||||
#include <vwModNum.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Defines Section */
|
||||
|
||||
/*
|
||||
* AIM cache errors
|
||||
*/
|
||||
|
||||
/* temporary until vwModNum.h is updated */
|
||||
|
||||
#define M_aimcacheLib (190 << 16)
|
||||
|
||||
enum aimCacheErrors {
|
||||
S_aimCacheLib_UNKNOWN_CACHE_TYPE = (M_aimcacheLib + 1 ),
|
||||
S_aimCacheLib_UNSUPPORTED_CACHE_FUNC,
|
||||
S_aimCacheLib_UNKNOWN_CACHE_OP
|
||||
};
|
||||
|
||||
/* definitions of function argument types */
|
||||
|
||||
#define C_FLG_MASK 0xFFFFFF00 /* Extract function types */
|
||||
#define C_FLG_OP_MASK 0x000000FF /* Extract cache operation */
|
||||
#define C_FLG_NOOP 0x00000100 /* Operation not supported */
|
||||
#define C_FLG_MGMT 0x00000200 /* Management function, enable/disable */
|
||||
#define C_FLG_VIRT 0x00000400 /* Function takes a Virtual Address */
|
||||
#ifdef _WRS_SUPPORT_CACHE_ISPHYSICAL
|
||||
#define C_FLG_PHYS 0x00000800 /* Function takes a Physical Address */
|
||||
#endif /* _WRS_SUPPORT_CACHE_ISPHYSICAL */
|
||||
#ifdef _WRS_SUPPORT_CACHE_ISINDEXED
|
||||
#define C_FLG_IDX_ONED 0x00001000 /* Function operates on a Indexed, */
|
||||
/* one dimensional array */
|
||||
#define C_FLG_IDX_TWOD 0x00002000 /* Function operates on a Indexed, */
|
||||
/* two dimensional array */
|
||||
#endif /* _WRS_SUPPORT_CACHE_ISINDEXED */
|
||||
#define C_FLG_ALL 0x00004000 /* Operates on the entire cache*/
|
||||
#define C_FLG_DISP 0x00008000 /* Flush uses displacement */
|
||||
#ifdef _WRS_SUPPORT_CACHE_LOCK
|
||||
#define C_FLG_LOCKPRTKT 0x00010000 /* Protect locked areas */
|
||||
#endif /* _WRS_SUPPORT_CACHE_LOCK */
|
||||
#define C_FLG_ORDER_RV 0x00020000 /* Reverse calling order from */
|
||||
/* Primary, Secondary, Tertiary */
|
||||
/* when sub caches are */
|
||||
/* supportable by AIM */
|
||||
#define C_FLG_FORCE 0x10000000 /* Top level API must call */
|
||||
/* this directly, this forces a*/
|
||||
/* passthrough to the architecture */
|
||||
/* defined routine */
|
||||
|
||||
/* Flags used within aimCacheLib.c */
|
||||
|
||||
#define CACHE_IS_VTOP 0x00100000 /* Virt to Phys needed */
|
||||
#define CACHE_IS_PTOV 0x00200000 /* Phys to Virt needed */
|
||||
#define CACHE_IS_VIRTUAL 0x00400000 /* The cache op is virtual */
|
||||
#define CACHE_IS_PHYSICAL 0x00800000 /* The cache op is physical */
|
||||
#define CACHE_IS_INDEXED 0x01000000 /* The cache op is indexed */
|
||||
#define CACHE_IS_HARVARD 0x02000000
|
||||
#define CACHE_IS_UNIFIED 0x04000000
|
||||
#define CACHE_IS_MULTISIZE 0x08000000 /* Different line sizes */
|
||||
|
||||
#define CACHE_MODE_MASK ( CACHE_IS_VIRTUAL | CACHE_IS_PHYSICAL | CACHE_IS_INDEXED)
|
||||
|
||||
/* Typedefs Section */
|
||||
|
||||
/*
|
||||
* enumeration of cache types
|
||||
* Note: The initial enumeration is to assure compatibility
|
||||
* with vxWorks 5.X
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
CACHE_TYPE_I = _INSTRUCTION_CACHE, /* Instruction Cache */
|
||||
CACHE_TYPE_D = _DATA_CACHE, /* Data Cache */
|
||||
#ifdef _WRS_SUPPORT_CACHE_EXTRA
|
||||
CACHE_TYPE_B = _BRANCH_CACHE, /* Branch Cache */
|
||||
CACHE_TYPE_S, /* Secondary Cache */
|
||||
CACHE_TYPE_T, /* Tertiary Cache */
|
||||
CACHE_TYPE_IL, /* Instruction TLB Cache */
|
||||
CACHE_TYPE_DL, /* Data TLB Cache */
|
||||
CACHE_TYPE_A, /* Alternate Primary Cache */
|
||||
/* Xscale has a "mini-cache" */
|
||||
#endif /* _WRS_SUPPORT_CACHE_EXTRA */
|
||||
|
||||
CACHE_TYPE_MAX_SUPPORTED
|
||||
}CACHETYPES;
|
||||
|
||||
/* enumeration of Primitive functions */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
CACHE_OP_NOOP, /* NO OP */
|
||||
CACHE_OP_ENABLE, /* CACHENABLE() */
|
||||
CACHE_OP_DISABLE, /* CACHEDISABLE() */
|
||||
#ifdef _WRS_SUPPORT_CACHE_LOCK
|
||||
CACHE_OP_LOCK, /* CACHELOCK() */
|
||||
CACHE_OP_UNLOCK, /* CACHEUNLOCK() */
|
||||
#endif /* _WRS_SUPPORT_CACHE_LOCK */
|
||||
CACHE_OP_FLUSH, /* CACHEFLUSH() */
|
||||
CACHE_OP_INVALIDATE, /* CACHEINVALIDATE() */
|
||||
CACHE_OP_CLEAR, /* CACHECLEAR() */
|
||||
CACHE_OP_TEXTUPDATE, /* CACHETEXTUPDATE() */
|
||||
CACHE_OP_PIPEFLUSH, /* CACHEPIPEFLUSH() */
|
||||
#ifdef _WRS_SUPPORT_CACHE_XLATE
|
||||
CACHE_OP_DMAVIRTOPHYS, /* VIRTUAL-TO-PHYSICAL TRANSLATION */
|
||||
CACHE_OP_DMAPHYSTOVIRT, /* PHYSICAL-TO-VIRTUAL TRANSLATION */
|
||||
#endif /* _WRS_SUPPORT_CACHE_XLATE */
|
||||
#ifdef _WRS_SUPPORT_CACHE_EXTRA
|
||||
CACHE_OP_FENCE, /* Memory synchronization */
|
||||
CACHE_OP_PREFETCH, /* Prefetch a range of memory */
|
||||
#endif /* _WRS_SUPPORT_CACHE_EXTRA */
|
||||
#ifndef _WRS_CONFIG_MEM_ALLOT
|
||||
CACHE_OP_DMAMALLOC, /* Allocate a dma safe buffer */
|
||||
CACHE_OP_DMAFREE, /* Free buffer allocated via DMAMALLOC */
|
||||
#endif /* !_WRS_CONFIG_MEM_ALLOT */
|
||||
CACHE_OP_ISON, /* Is Cache On */
|
||||
#ifdef _WRS_SUPPORT_CACHE_EXTRA
|
||||
CACHE_OP_EXP_0, /* Architecture specific expansion */
|
||||
CACHE_OP_EXP_1,
|
||||
CACHE_OP_EXP_2,
|
||||
CACHE_OP_LAST = (CACHE_OP_EXP_2 + 3) /* This keeps _ALL functions */
|
||||
/* from overflowing the array */
|
||||
#else /* _WRS_SUPPORT_CACHE_EXTRA */
|
||||
CACHE_OP_LAST = (CACHE_OP_ISON + 3)
|
||||
#endif /* _WRS_SUPPORT_CACHE_EXTRA */
|
||||
} CACHE_OPS;
|
||||
|
||||
/* cache Attributes structure */
|
||||
|
||||
typedef struct cacheAttributes
|
||||
{
|
||||
CACHETYPES cacheType; /* One of CACHETYPES */
|
||||
UINT32 cacheModeDefault; /* copyback, writethrough, etc. */
|
||||
UINT32 cacheModeSupported;/* copyback, writethrough, etc. */
|
||||
UINT32 cacheSize; /* 0 for "not present" */
|
||||
UINT32 lineSize; /* in bytes */
|
||||
UINT32 lineStep; /* increment between cache lines */
|
||||
UINT32 numWays; /* number of way in the cache */
|
||||
UINT32 wayStep; /* increment between cache ways */
|
||||
UINT32 numSegs; /* number of segments in a segmented cache */
|
||||
UINT32 segStep; /* increment between segments */
|
||||
void * cacheBase; /* Index or displacement cache ops */
|
||||
} CACHEATTRIBUTES;
|
||||
|
||||
/* Description of cache primitive */
|
||||
|
||||
typedef struct cacheOp
|
||||
{
|
||||
UINT32 opType; /* From C_FLG defines */
|
||||
FUNCPTR opPtr; /* Pointer to the Primitive */
|
||||
} CACHEOP;
|
||||
|
||||
|
||||
/* Description of a cache or portion of a cache */
|
||||
|
||||
typedef struct cachePrimitive
|
||||
{
|
||||
CACHEATTRIBUTES cacheAttr; /* This could be a pointer */
|
||||
CACHEOP cacheOps[CACHE_OP_LAST];
|
||||
}CACHEPRIMITIVE;
|
||||
|
||||
/*
|
||||
* cacheConfig is the structure that encapsulates a CPU's
|
||||
* cache properties.
|
||||
*/
|
||||
|
||||
typedef struct cacheConfig
|
||||
{
|
||||
UINT32 nCaches; /* Number of caches described in this struct */
|
||||
CACHEPRIMITIVE cachePrimitives[CACHE_TYPE_MAX_SUPPORTED];
|
||||
}CACHECONFIG;
|
||||
|
||||
/* The following data elements are initialized and maintained */
|
||||
/* by the cache AIM based on the data passed to it via the */
|
||||
/* CACHECONFIG structure */
|
||||
|
||||
/*
|
||||
* Cache attributes structure for use in cacheAimInfo.
|
||||
*/
|
||||
|
||||
typedef struct cacheGlobalAttr
|
||||
{
|
||||
UINT32 cacheExists; /* Indicates that this entry in the array is valid */
|
||||
UINT32 cacheType; /* Type of cache, I,D */
|
||||
UINT32 cacheSize; /* Size in bytes of this cache */
|
||||
UINT32 cacheLineSize; /* Line size for this cache */
|
||||
UINT32 cacheModes; /* Modes supported by this cache */
|
||||
UINT32 cacheModeCurrent; /* Current mode of this cache */
|
||||
}CACHEGLOBALATTR;
|
||||
|
||||
/*
|
||||
* Lock database structure.
|
||||
* Keeps track of locked areas, facilitating the protection of locked areas
|
||||
* from invalidates. The Lock database uses virtual addresses, a flat memory
|
||||
* model allows this.
|
||||
*
|
||||
* Dynamically allocated by the AIM for lock management.
|
||||
*/
|
||||
|
||||
typedef struct cacheLockNode *lockNodePtr;
|
||||
typedef struct cacheLockNode
|
||||
{
|
||||
lockNodePtr pNext;
|
||||
lockNodePtr pPrev;
|
||||
UINT32 cacheLockStart;
|
||||
UINT32 cacheLockEnd;
|
||||
}CACHELOCKNODE;
|
||||
|
||||
/* Globally visible array of attributes */
|
||||
|
||||
extern CACHEGLOBALATTR cacheAimInfo[CACHE_TYPE_MAX_SUPPORTED];
|
||||
|
||||
extern UINT32 cacheLineSize; /* Cache line size. Used for alignment */
|
||||
extern UINT32 cacheAddrAlign; /* Increment for address alignment */
|
||||
extern UINT32 cacheLineMask; /* Mask to align to a cache line */
|
||||
|
||||
/* Forward Declarations */
|
||||
|
||||
STATUS aimCacheInit ( CACHECONFIG * cacheConfig );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCaimCacheLibh */
|
||||
@@ -0,0 +1,71 @@
|
||||
/* aimMmuBaseLib.h - Base of the MMU Architecture Independent Manager */
|
||||
|
||||
/* Copyright 1984-2004, 2010 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,29apr10,pad Moved extern C statement after include statements.
|
||||
01b,31aug04,dtr Add new attribute available for tlb locking.
|
||||
01a,07jun04,sru written
|
||||
*/
|
||||
|
||||
#ifndef __INCaimMmuBaseLibh
|
||||
#define __INCaimMmuBaseLibh
|
||||
|
||||
#include "vxWorks.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* typedefs */
|
||||
|
||||
/*
|
||||
* MMU_ARCH_LIB_ATTRS is a data structure that is allocated by the AIM
|
||||
* base library. It is filled in with MMU-specific attributes during
|
||||
* the initialization of the architecture-dependent MMU library. From
|
||||
* that point forward, the data structure is used by the AIM for its
|
||||
* internal management.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/* fields filled in by the AD-MMU */
|
||||
|
||||
UINT pageSizeMask;
|
||||
UINT lockSizeMask;
|
||||
UINT contextMin; /* inclusive */
|
||||
UINT contextMax; /* inclusive */
|
||||
UINT pteSize; /* units are bytes */
|
||||
UINT contextTblAlign;
|
||||
UINT regionTblNumEntries;
|
||||
UINT pageTblNumEntries;
|
||||
UINT tlbNumEntries; /* sum of hardware TLB resources */
|
||||
UINT tlbLockNumEntries; /* sum of hardware TLB resources available
|
||||
for locking */
|
||||
UINT sizeOfRegionTbl;
|
||||
UINT sizeOfPageTbl;
|
||||
UINT sizeOfContextTbl;
|
||||
|
||||
/* fields filled in by the AIM during initialization */
|
||||
|
||||
UINT pageSize;
|
||||
UINT blockSize;
|
||||
UINT regionShift; /* rightward bitshift to create region idx */
|
||||
UINT regionMask; /* post-shift mask of region idx */
|
||||
UINT pageShift; /* rightward bitshift to create page idx */
|
||||
UINT pageMask; /* post-shift mask of page idx */
|
||||
|
||||
} MMU_ARCH_LIB_ATTRS;
|
||||
|
||||
/* externs */
|
||||
|
||||
extern STATUS aimMmuBaseLibInit ();
|
||||
extern MMU_ARCH_LIB_ATTRS mmuArchLibAttrs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCaimMmuBaseLibh */
|
||||
@@ -0,0 +1,596 @@
|
||||
/* aimMmuLib.h - MMU library portion of the Architecture Independent Manager */
|
||||
|
||||
/*
|
||||
* Copyright 2003, 2004, 2006, 2007, 2010-2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01v,28feb12,h_k made TLB sync config flexible to be able to share one binary
|
||||
with different CPU variants. (WIND00320752)
|
||||
01u,01feb11,slk add mmuTlbPoolCreateHook hook for region and page table pool
|
||||
creation
|
||||
01t,21jul10,wiq Remove useless typedef. (WIND00054776)
|
||||
01t,09jun10,d_c Add mmuPostStateSetHook to MMU_ARCH_LIB_FUNCS.
|
||||
01s,29apr10,pad Moved extern C statement after include statements.
|
||||
01r,14jan10,cwl Remove the function aimMmuShowInit(). (WIND00184839)
|
||||
01q,29nov06,sru Added complete prototypes and header comments for the
|
||||
function pointers that make up the AD-MMU interface.
|
||||
01p,29jan07,h_k added an extra argument to MODIFYLOCALPTEFUNC.
|
||||
01o,29nov04,dtr Add region tbl ptr to MMU_TRANS_TBL.
|
||||
01n,23nov04,dtr Mod to API for 860 support.
|
||||
01m,29sep04,dtr Add Show routines externs.
|
||||
01l,17sep04,sru Added 'pWritable' parameter to LOCKIMPORTFUNC.
|
||||
01k,30aug04,dtr Modify allocation buffer for static TLB entries.
|
||||
01j,06aug04,sru Added support for importing locked regions at startup.
|
||||
01i,08jun04,sru Moved attribute definitions to mmuAimBaseLib.h.
|
||||
01h,19may04,dtr Add extra function for ISR callable state.
|
||||
01g,08apr04,dtr Adding in new feature support aimMmuLock/Unlock/optimization.
|
||||
01f,04may04,sru add support for query of TLB size
|
||||
01e,12nov03,jtp Change mmuPteSet global parameter type to BOOL
|
||||
01d,07nov03,sru change model for bufferwrite
|
||||
01c,04nov03,jtp change API for fine-grain PTE get
|
||||
01b,30oct03,sru add AD-MMU hook for TransTblGet
|
||||
01a,07apr03,sru written
|
||||
*/
|
||||
|
||||
#ifndef __INCaimMmuLibh
|
||||
#define __INCaimMmuLibh
|
||||
|
||||
#include <vxWorks.h>
|
||||
#include <aimMmuBaseLib.h>
|
||||
#ifdef _WRS_ENABLE_TLB_POOL_CREATE_HOOK
|
||||
#include <poolLib.h>
|
||||
#endif /* _WRS_ENABLE_TLB_POOL_CREATE_HOOK */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* options for various AIM calls */
|
||||
|
||||
#define AIM_MMU_OPT_LOCK_NONE 0
|
||||
#define AIM_MMU_OPT_LOCK_IMPORT 1
|
||||
|
||||
/* masks for page sizes */
|
||||
|
||||
#define MMU_PAGE_MASK_1K 0x0000001
|
||||
#define MMU_PAGE_MASK_2K 0x0000002
|
||||
#define MMU_PAGE_MASK_4K 0x0000004
|
||||
#define MMU_PAGE_MASK_8K 0x0000008
|
||||
#define MMU_PAGE_MASK_16K 0x0000010
|
||||
#define MMU_PAGE_MASK_32K 0x0000020
|
||||
#define MMU_PAGE_MASK_64K 0x0000040
|
||||
#define MMU_PAGE_MASK_128K 0x0000080
|
||||
#define MMU_PAGE_MASK_256K 0x0000100
|
||||
#define MMU_PAGE_MASK_512K 0x0000200
|
||||
#define MMU_PAGE_MASK_1M 0x0000400
|
||||
#define MMU_PAGE_MASK_2M 0x0000800
|
||||
#define MMU_PAGE_MASK_4M 0x0001000
|
||||
#define MMU_PAGE_MASK_8M 0x0002000
|
||||
#define MMU_PAGE_MASK_16M 0x0004000
|
||||
#define MMU_PAGE_MASK_32M 0x0008000
|
||||
#define MMU_PAGE_MASK_64M 0x0010000
|
||||
#define MMU_PAGE_MASK_128M 0x0020000
|
||||
#define MMU_PAGE_MASK_256M 0x0040000
|
||||
#define MMU_PAGE_MASK_512M 0x0080000
|
||||
#define MMU_PAGE_MASK_1G 0x0100000
|
||||
|
||||
#define MMU_PAGE_SIZE_MIN 1024
|
||||
#define MMU_PAGE_MASK_MIN MMU_PAGE_MASK_1K
|
||||
#define BIT_SHIFT_1K 10
|
||||
#define MAX_BITS 31
|
||||
typedef char MMU_PAGE_TBL; /* placeholder */
|
||||
typedef void *MMU_REGION_TBL;
|
||||
typedef MMU_REGION_TBL *MMU_CONTEXT_TBL;
|
||||
typedef int MMU_CONTEXT;
|
||||
|
||||
typedef struct mmuTransTblStruct
|
||||
{
|
||||
MMU_CONTEXT context;
|
||||
MMU_REGION_TBL *regionTblPtr;
|
||||
} MMU_TRANS_TBL;
|
||||
|
||||
/* PTE_ATTR - a structured used to read/write PTE attribute info. */
|
||||
|
||||
typedef struct mmu_pte_attr
|
||||
{
|
||||
PHYS_ADDR physAddr;
|
||||
VIRT_ADDR virtAddr;
|
||||
UINT pageSize;
|
||||
BOOL global;
|
||||
UINT context;
|
||||
UINT state;
|
||||
BOOL valid; /* AIM-readable valid state */
|
||||
BOOL isrCallable;
|
||||
} PTE_ATTR;
|
||||
|
||||
|
||||
/* MMU_PTE_ATTR mask bits. Used to control PTE set/get functions */
|
||||
|
||||
#define PTE_ATTR_PHYS_ADDR 0x01
|
||||
#define PTE_ATTR_PAGE_SIZE 0x02
|
||||
#define PTE_ATTR_GLOBAL 0x04
|
||||
#define PTE_ATTR_CONTEXT 0x08
|
||||
#define PTE_ATTR_STATE 0x10
|
||||
#define PTE_ATTR_VIRT_ADDR 0x20
|
||||
#define PTE_ATTR_VALID 0x40 /* AIM-readable valid state */
|
||||
#define PTE_ATTR_ISR_CALLABLE 0x80
|
||||
|
||||
/* type of table mmuTlbPoolCreateHook should create */
|
||||
|
||||
#ifdef _WRS_ENABLE_TLB_POOL_CREATE_HOOK
|
||||
typedef enum
|
||||
{
|
||||
PAGE_TABLE,
|
||||
REGION_TABLE
|
||||
} AIM_MMU_TBL_TYPE;
|
||||
#endif /* _WRS_ENABLE_TLB_POOL_CREATE_HOOK */
|
||||
|
||||
extern STATUS aimMmuLibInit ();
|
||||
|
||||
typedef struct
|
||||
{
|
||||
VIRT_ADDR virtAddr;
|
||||
int pageSize;
|
||||
BOOL imported;
|
||||
} STATIC_ENTRY_REGION;
|
||||
|
||||
/*
|
||||
* MMU_ARCH_LIB_FUNCS is a data structure that is allocated by the AIM
|
||||
* library. It is filled in with function pointers that are exported
|
||||
* by the architecture-dependent MMU library. The AIM uses these
|
||||
* function pointers to implement its MMU services.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/*
|
||||
* mmuTlbInvalidateAllDynamic - Required AD-MMU function. Discard
|
||||
* all non-locked TLB entries from the TLB hardware.
|
||||
*/
|
||||
|
||||
void (*mmuTlbInvalidateAllDynamic) (void);
|
||||
|
||||
/*
|
||||
* mmuTlbInvalidate - Required AD-MMU function. Discard
|
||||
* single TLB entry that maps the requested [context,vaddr] pair.
|
||||
*/
|
||||
|
||||
void (*mmuTlbInvalidate)
|
||||
(
|
||||
int context, /* address space identifer for vaddr */
|
||||
VIRT_ADDR vaddr /* virtual address to invalidate in TLB */
|
||||
);
|
||||
|
||||
/*
|
||||
* kmemPtrToPageTablePtr - Optional AD-MMU function. Used when
|
||||
* an architecture needs to perform a transformation on a pointer
|
||||
* allocated from the kernel heap before the pointer placed into
|
||||
* page tables. MIPS uses this to translate KSEGM addresses to
|
||||
* KSEG0 addresses so that accesses to the page tables are made
|
||||
* from non-mapped virtual addresses.
|
||||
*/
|
||||
|
||||
VIRT_ADDR (*kmemPtrToPageTablePtr)
|
||||
(
|
||||
VIRT_ADDR vaddr /* kernel heap address to convert */
|
||||
);
|
||||
|
||||
/*
|
||||
* pageTablePtrToKmemPtr - Optional AD-MMU function. Used to
|
||||
* invert the transformation performed by kmemPtrToPageTablePtr.
|
||||
* If a kmemPtrToPageTablePtr function is provided by the AD-MMU,
|
||||
* this function must be provided as well.
|
||||
*/
|
||||
|
||||
VIRT_ADDR (*pageTablePtrToKmemPtr)
|
||||
(
|
||||
VIRT_ADDR vaddr /* page table address to convert */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuEnable - Required AD-MMU function. Used to enable or disable
|
||||
* the the memory management hardware for the CPU.
|
||||
*/
|
||||
|
||||
STATUS (*mmuEnable)
|
||||
(
|
||||
BOOL enable /* TRUE = enable, FALSE = disable */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPteSet - Required AD-MMU function. Used to completely replace
|
||||
* the contents of a PTE with the provided page attributes.
|
||||
*/
|
||||
|
||||
void (*mmuPteSet)
|
||||
(
|
||||
void * pPte, /* pointer to MMU-dependent PTE */
|
||||
PHYS_ADDR physAddr, /* new physical address */
|
||||
VIRT_ADDR virtAddr, /* virtual address for PTE */
|
||||
UINT newState, /* new MMU-dependent state */
|
||||
BOOL newGlobal, /* new global state */
|
||||
UINT newPageSize, /* new page size */
|
||||
void *pRte /* pointer to MMU-dependent RTE */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPteInit - Required AD-MMU function. Used to initialize a PTE
|
||||
* to a known state. The default known state for a PTE is UNMAPPED.
|
||||
* which must be distinguishable from the VALID/INVALID state.
|
||||
*/
|
||||
|
||||
void (*mmuPteInit)
|
||||
(
|
||||
void * pPte /* pointer to MMU-dependent PTE */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPteStateGet - Required AD-MMU function. This is used to determine
|
||||
* the architecture-dependent state information for the requested PTE.
|
||||
* Both the pointer to the PTE and the pointer to the RTE are provided,
|
||||
* so architectures that store ancilliacy information in the RTE can
|
||||
* access it.
|
||||
*/
|
||||
|
||||
UINT (*mmuPteStateGet)
|
||||
(
|
||||
void * pPte, /* pointer to MMU-dependent PTE */
|
||||
void * pRte /* pointer to MMU-dependent RTE */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPteValidGet - Required AD-MMU function. Returns TRUE or FALSE
|
||||
* depending on whether or not the referenced PTE is in the VALID or
|
||||
* INVALID state.
|
||||
*/
|
||||
|
||||
BOOL (*mmuPteValidGet)
|
||||
(
|
||||
void * pPte /* pointer to MMU-dependent PTE */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPteGlobalGet - Required AD-MMU function. Returns TRUE or FALSE
|
||||
* depending on whether or not the referenced PTE refers to a global
|
||||
* or non-global page.
|
||||
*/
|
||||
|
||||
BOOL (*mmuPteGlobalGet)
|
||||
(
|
||||
void * pPte /* pointer to MMU-dependent PTE */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPtePageSizeGet - Required AD-MMU function. Returns the size in
|
||||
* bytes of the address space spanned by the PTE. For most PTEs, the
|
||||
* value returned by this function will be equal to the default page
|
||||
* size for the architecture. For pages that are part of an optimized
|
||||
* region, the size can be substantially larger.
|
||||
*/
|
||||
|
||||
UINT (*mmuPtePageSizeGet)
|
||||
(
|
||||
void * pPte /* pointer to MMU-dependent PTE */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPtePhysAddrGet - Required AD-MMU function. Returns the physical
|
||||
* address that is mapped by the PTE.
|
||||
*/
|
||||
|
||||
PHYS_ADDR (*mmuPtePhysAddrGet)
|
||||
(
|
||||
void * pPte /* pointer to MMU-dependent PTE */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuStateValidGet - Required AD-MMU function. Returns the validity
|
||||
* of the PTE. Note that PTE's can transition between the valid and
|
||||
* invalid state without losing any other page properties, such as
|
||||
* caching mode or physical address. The "valid" state is distinct
|
||||
* from "unmapped". These two states must be distinguishable at the
|
||||
* AD-MMU level.
|
||||
*/
|
||||
|
||||
BOOL (*mmuStateValidGet)
|
||||
(
|
||||
UINT pteState /* state retrieved from PTE */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuStateCacheModeGet - Required AD-MMU function. Returns the
|
||||
* architecture-dependent cache mode contained within the PTE.
|
||||
*/
|
||||
|
||||
UINT (*mmuStateCacheModeGet)
|
||||
(
|
||||
UINT pteState /* state retrieved from PTE */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuStateWriteEnabledGet - Required AD-MMU function. Returns the
|
||||
* write-enabled state of the PTE. This query is used to determine
|
||||
* whether or not the page is writable from supervisor state.
|
||||
*/
|
||||
|
||||
BOOL (*mmuStateWriteEnabledGet)
|
||||
(
|
||||
UINT pteState /* state retrieved from PTE */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuCurrentSet - Required AD-MMU function. Performs whatever
|
||||
* architecture-dependent operations are required so that the
|
||||
* requested context becomes the current address map. This
|
||||
* may involve touching CPU-specific registers (e.g., ASID registers
|
||||
* on MIPS), or may involve changes to global variables that are used
|
||||
* by TLB miss handlers to find the top of the current translation
|
||||
* tables.
|
||||
*/
|
||||
|
||||
void (*mmuCurrentSet)
|
||||
(
|
||||
MMU_CONTEXT_TBL * pContext, /* pointer to array of contexts */
|
||||
int context /* which context to use */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuCurrentGet - Deprecated function.
|
||||
*/
|
||||
|
||||
UINT (*mmuCurrentGet) (void);
|
||||
|
||||
/*
|
||||
* mmuPageWrite - Required AD-MMU function. Used to copy data to
|
||||
* (possibly) write-protected destination pages. The data referenced
|
||||
* by 'numBytes' is guaranteed to be contained completely within the
|
||||
* pages referenced by the 'src' and 'dst' PTEs. The AD-MMU can
|
||||
* choose to implement this by making modifications to the PTES, or
|
||||
* it may also choose to bypass the MMU entirely if this capability
|
||||
* is provided by the architecture.
|
||||
*/
|
||||
|
||||
void (*mmuPageWrite)
|
||||
(
|
||||
int context, /* context in which to do the operation */
|
||||
void * pPteSrc, /* PTE for source page */
|
||||
VIRT_ADDR virtAddrSrc, /* source address for copy */
|
||||
void * pPteDst, /* PTE for destination page */
|
||||
VIRT_ADDR virtAddrDst, /* destination address for copy */
|
||||
UINT numBytes /* number of bytes of data to copy */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuAttrTranslate - Optional AD-MMU function. If provided by the
|
||||
* AD-MMU, this function is used to translate state information
|
||||
between architecture-independent and architecture-dependent forms.
|
||||
*/
|
||||
|
||||
STATUS (*mmuAttrTranslate)
|
||||
(
|
||||
UINT fromState, /* starting state */
|
||||
UINT * pToState, /* ending state */
|
||||
UINT fromStateMask, /* starting state mask */
|
||||
UINT * pToStateMask, /* ending state mask */
|
||||
BOOL independentoToDependent /* conversion direction */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuTransTblGet - (being deprecated)
|
||||
*/
|
||||
|
||||
UINT * (*mmuTransTblGet)
|
||||
(
|
||||
MMU_CONTEXT_TBL * pContext, /* pointer to array of contexts */
|
||||
int context /* which context to use */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuLockPteUpdate - Optional AD-MMU function. This function is
|
||||
* required only if the AD-MMU supports page size optimization
|
||||
* and the architecture needs to lock a page while modifying the page
|
||||
* size.
|
||||
*/
|
||||
|
||||
STATUS (*mmuLockPteUpdate)
|
||||
(
|
||||
MMU_CONTEXT context, /* which context to use */
|
||||
void * pPte, /* pointer to MMU-dependent PTE */
|
||||
VIRT_ADDR virtAddr, /* virtual address for PTE */
|
||||
UINT size, /* of address range in bytes */
|
||||
BOOL lock /* lock or unlock */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuLock - Optional AD-MMU function. This function is required
|
||||
* only if the AD-MMU supports page locking.
|
||||
*/
|
||||
|
||||
STATUS (*mmuLock)
|
||||
(
|
||||
void * pPte, /* pointer to MMU-dependent PTE */
|
||||
VIRT_ADDR,
|
||||
UINT
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuUnlock - Optional AD-MMU function. This function is
|
||||
* reuired only if the AD-MMU supports page locking.
|
||||
*/
|
||||
|
||||
STATUS (*mmuUnlock)
|
||||
(
|
||||
VIRT_ADDR
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPteLockGet - Optional AD-MMU function. This function is
|
||||
* required only if the AD-MMU supports page locking. This function
|
||||
* returns true if the PTE is locked into the hardware TLB resources
|
||||
* of the CPU, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
BOOL (*mmuPteLockGet)
|
||||
(
|
||||
void * pPte /* pointer to MMU-dependent PTE */
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPteSetLockState - Optional AD-MMU function. This function is
|
||||
* required only if the AD-MMU supports page locking. This function
|
||||
* sets an array of PTEs locked or unlocked accordingly.
|
||||
*/
|
||||
|
||||
STATUS (*mmuPteSetLockState)
|
||||
(
|
||||
void * pPte, /* pointer to MMU-dependent PTE */
|
||||
UINT,
|
||||
BOOL,
|
||||
BOOL
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPteSetForDynamic - Optional AD-MMU function. This function is
|
||||
* required only if the AD-MMU supports page size optimization.
|
||||
* This function sets the optimized page size or resets to the
|
||||
* default page size.
|
||||
*/
|
||||
|
||||
STATUS (*mmuPteSetForDynamic)
|
||||
(
|
||||
void * pPte, /* pointer to MMU-dependent PTE */
|
||||
void * pLocalPte,
|
||||
UINT,
|
||||
PHYS_ADDR,
|
||||
BOOL,
|
||||
BOOL,
|
||||
VIRT_ADDR
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPteMaxPhysBitsGet - Required AD-MMU function unless the number
|
||||
* of address bits in a physical address is 32 bits.
|
||||
* This function returns the number of address bits in a physical
|
||||
* address. This should a value between 32 an 64, depending on
|
||||
* the number of significant physical address bits supported by the MMU.
|
||||
*/
|
||||
|
||||
UINT (*mmuPteMaxPhysBitsGet) (void);
|
||||
|
||||
/*
|
||||
* mmuPteIsrCallableGet - Optional AD-MMU function. This function
|
||||
* returns TRUE if the PTE can be modified from within interrupt
|
||||
* context, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
BOOL (*mmuPteIsrCallableGet)
|
||||
(
|
||||
void * pPte
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuLockImport - Optional AD-MMU function. Architectures that
|
||||
* set up locked TLB entries as part of system initialization must
|
||||
* provide this function. During initialization, the MMU AIM calls
|
||||
* this function with increasing index numbers (0, 1, 2...) to
|
||||
* retrieve the set of address ranges that the architecture has
|
||||
* locked. The AD-MMU returns OK if it has a valid locked region
|
||||
* for the index, and ERROR otherwise. For each valid region, the
|
||||
* AD-MMU returns the virtual address, size, and writeability of
|
||||
* the memory region that is locked.
|
||||
*/
|
||||
|
||||
STATUS (*mmuLockImport)
|
||||
(
|
||||
int index,
|
||||
VIRT_ADDR * pVirtAddr,
|
||||
UINT32 * pSize,
|
||||
BOOL * pWritable
|
||||
);
|
||||
|
||||
/*
|
||||
* mmuPostStateSetHook - Optional AD-MMU function. If set to
|
||||
* non-NULL, this function is called at the end of
|
||||
* aimMmuStateSet(), after all pages in the subject block have
|
||||
* been set to the new state, and the MMU has been invalidated for
|
||||
* those pages.
|
||||
*/
|
||||
|
||||
#ifdef _WRS_ENABLE_MMU_POST_STATE_SET_HOOK
|
||||
STATUS (*mmuPostStateSetHook)
|
||||
(
|
||||
MMU_TRANS_TBL *pTransTbl, /* MMU Translation table pointer */
|
||||
VIRT_ADDR virtAddr, /* Virtual address of memory block */
|
||||
PHYS_ADDR physAddr, /* Physical address */
|
||||
UINT numPages, /* Number of pages in memory block */
|
||||
UINT pageSize, /* Page size in memory block */
|
||||
UINT stateMask, /* State mask */
|
||||
UINT state, /* New arch-dependent state for block */
|
||||
UINT affectedStateBits, /* Mask indicating modified state bits */
|
||||
BOOL optimize /* Optimization flag */
|
||||
);
|
||||
#endif /* _WRS_ENABLE_MMU_POST_STATE_SET_HOOK */
|
||||
|
||||
/*
|
||||
* mmuTlbPoolCreateHook - Optional AD-MMU function. Architectures
|
||||
* can use this hook to supply their version of poolCreate for
|
||||
* the MMU region and page tables. This allows the use of special
|
||||
* memory regions for the tables among other options. This hook is
|
||||
* used as part of the aimMmuLibInit operation.
|
||||
*/
|
||||
|
||||
#ifdef _WRS_ENABLE_TLB_POOL_CREATE_HOOK
|
||||
POOL_ID (*mmuTlbPoolCreateHook)
|
||||
(
|
||||
const char * pName, /* optional name to assign to pool */
|
||||
size_t itmSize, /* size in bytes of a pool item */
|
||||
size_t alignment, /* alignment of a pool item */
|
||||
/* (must be power of 2, or 0) */
|
||||
ULONG initCnt, /* initial number of items to put in pool */
|
||||
ULONG incrCnt, /* min # of items to add to pool */
|
||||
/* (if 0, no pool expansion is done) */
|
||||
PART_ID partId, /* memory partition ID */
|
||||
ULONG options, /* initial options for pool */
|
||||
AIM_MMU_TBL_TYPE tblType /* pool table type (region or page) */
|
||||
);
|
||||
#endif /* _WRS_ENABLE_TLB_POOL_CREATE_HOOK */
|
||||
|
||||
#if defined(_WRS_CONFIG_SMP)
|
||||
/*
|
||||
* mmuTlbInvalidateAllDynamicSMP - Optional AD-MMU function in SMP.
|
||||
* Discard all non-locked TLB entries from the TLB hardware.
|
||||
*/
|
||||
|
||||
void (*mmuTlbInvalidateAllDynamicSMP) (void);
|
||||
|
||||
/*
|
||||
* mmuTlbInvalidateSMP - Optional AD-MMU function in SMP. Discard
|
||||
* single TLB entry that maps the requested [context,vaddr] pair.
|
||||
*/
|
||||
|
||||
void (*mmuTlbInvalidateSMP)
|
||||
(
|
||||
int context, /* address space identifer for vaddr */
|
||||
VIRT_ADDR vaddr /* virtual address to invalidate in TLB */
|
||||
);
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
} MMU_ARCH_LIB_FUNCS;
|
||||
|
||||
extern STATUS aimMmuLibInit ();
|
||||
extern void aimMmuMapShow (UINT);
|
||||
extern void aimMmuOptimizeMemShow (int);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCaimMmuLibh */
|
||||
|
||||
@@ -0,0 +1,108 @@
|
||||
/* aio.h - asynchronous I/O header file */
|
||||
|
||||
/* Copyright 1984-2006, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01l,21jun10,jxu LP64: add prototype for aioVerboseEnable.
|
||||
01k,28apr10,pad Moved extern C statement after include statements.
|
||||
01j,11aug06,jlk Fix: WIND0006174 - lio_listio for pse52
|
||||
01i,15mar06,mil Updated include quotes.
|
||||
01h,18jan06,mil Updated for POSIX namespace conformance (P1).
|
||||
01g,08jan06,hya fixed prototype of aio_return.
|
||||
01f,21nov05,md fix prototypes for lio_listio and aio_suspend
|
||||
01f,19apr05,hya added aio_fsync.
|
||||
01e,30jan04,dat Rework for RTP compatibility
|
||||
01d,18jul96,dbt added aioPxLibInit() and aioShow() prototypes (SPR #3227).
|
||||
01c,23jan96,tpr added ; after lio_listio () prototype definition.
|
||||
added Copyright line.
|
||||
01b,26jan94,kdl removed prototype for aio_fsync(); minor cleanup.
|
||||
01a,04apr93,elh written.
|
||||
*/
|
||||
|
||||
#ifndef __INCaioh
|
||||
#define __INCaioh
|
||||
|
||||
/* includes */
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <signal.h>
|
||||
#include <fcntl.h>
|
||||
#include <private/aioPxLibP.h> /* private APIs, do not use */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* defines */
|
||||
|
||||
/* aio_cancel() return values */
|
||||
|
||||
#define AIO_CANCELED 1 /* operations canceled */
|
||||
#define AIO_NOTCANCELED 2 /* operations are in progress */
|
||||
#define AIO_ALLDONE 3 /* operations complete */
|
||||
|
||||
/* lio_listio() modes */
|
||||
|
||||
#define LIO_WAIT 4 /* wait for completion */
|
||||
#define LIO_NOWAIT 5 /* don't wait for completion */
|
||||
|
||||
/* lio_listio() operations */
|
||||
/* lio op codes */
|
||||
#define LIO_READ 0 /* read operation */
|
||||
#define LIO_WRITE 1 /* write operation */
|
||||
#define LIO_NOP 2 /* no transfer operation*/
|
||||
|
||||
/* Asynchronous I/O control block */
|
||||
|
||||
struct aiocb
|
||||
{
|
||||
int aio_fildes; /* file descriptor */
|
||||
off_t aio_offset; /* file offset */
|
||||
volatile void * aio_buf; /* location of buffer */
|
||||
size_t aio_nbytes; /* length of transfer */
|
||||
int aio_reqprio; /* request priority offset */
|
||||
struct sigevent aio_sigevent; /* signal number and value */
|
||||
int aio_lio_opcode; /* operation to be performed */
|
||||
|
||||
/* WRS addition */
|
||||
struct aio_sys aio_sys; /* implementation-specific */
|
||||
};
|
||||
|
||||
/* forward declarations */
|
||||
|
||||
extern int aio_read (struct aiocb *);
|
||||
extern int aio_write (struct aiocb *);
|
||||
#ifdef _WRS_KERNEL
|
||||
extern int lio_listio (int, struct aiocb * const[], int,
|
||||
struct sigevent *);
|
||||
#else
|
||||
extern int lio_listio (int, struct aiocb * _Restrict const[], int,
|
||||
struct sigevent * _Restrict);
|
||||
#endif
|
||||
extern int aio_error (const struct aiocb *);
|
||||
extern ssize_t aio_return (struct aiocb *);
|
||||
extern int aio_cancel (int, struct aiocb *);
|
||||
extern int aio_suspend (const struct aiocb *const[], int ,
|
||||
const struct timespec *);
|
||||
extern int aio_fsync (int, struct aiocb *);
|
||||
|
||||
#if !defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE) && \
|
||||
!defined(_POSIX_AEP_RT_CONTROLLER_C_SOURCE)
|
||||
extern STATUS aioPxLibInit (int lioMax);
|
||||
extern STATUS aioShow (int notUsed);
|
||||
extern int aioVerboseEnable (void);
|
||||
#endif /* _POSIX_xxx_SOURCE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCaioh */
|
||||
@@ -0,0 +1,51 @@
|
||||
/* aioSysDrv.h - AIO system driver header file */
|
||||
|
||||
/* Copyright 1984-2005, 2010 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01g,24jun10,jxu LP64: changed API STATUS aioSysInit (int, int, int) to
|
||||
STATUS aioSysInit (int, int, size_t);
|
||||
01f,28apr10,pad Moved extern C statement after include statements.
|
||||
01e,07feb05,hya added missing prototype
|
||||
01d,30jan04,dat Rework for RTP compatibility
|
||||
01c,12jan94,kdl changed name from aioSysPxLib to aioSysDrv; general cleanup.
|
||||
01b,06dec93,dvs removed S_aioSysPxLib_NO_PIPES
|
||||
01a,04apr93,elh written.
|
||||
*/
|
||||
|
||||
#ifndef __INCaioSysDrvh
|
||||
#define __INCaioSysDrvh
|
||||
|
||||
/* includes */
|
||||
|
||||
#include "aio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* defines */
|
||||
|
||||
/* project configurable AIO task parameters */
|
||||
|
||||
#define AIO_IO_TASKS_DFLT 2 /* number of I/O tasks */
|
||||
#define AIO_IO_STACK_DFLT 0x7000 /* I/O task stack size */
|
||||
#define AIO_IO_PRIO_DFLT 50 /* I/O task priority */
|
||||
|
||||
/* hardcoded parameters */
|
||||
|
||||
#define AIO_TASK_OPT 0 /* task options */
|
||||
#define AIO_WAIT_STACK 0x7000 /* wait task stack size */
|
||||
|
||||
/* forward declarations */
|
||||
|
||||
extern STATUS aioSysInit (int numTasks, int taskPrio, size_t taskStackSize);
|
||||
extern STATUS aioSysInsert (struct aiocb *pAiocb, int prio);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCaioSysDrvh */
|
||||
@@ -0,0 +1,65 @@
|
||||
/* altivecLib.h - ALTIVEC coprocessor support library header */
|
||||
|
||||
/* Copyright 1984-1997, 2010 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,29apr10,pad Moved extern C statement after include statements.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INCaltivecLibh
|
||||
#define __INCaltivecLibh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#include "taskLib.h"
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#if CPU_FAMILY==PPC
|
||||
#include "arch/ppc/altivecPpcLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#endif /* CPU_FAMILY==PPC */
|
||||
|
||||
/* function declarations */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
|
||||
extern void altivecInit (void);
|
||||
extern void altivecShowInit (void);
|
||||
extern void altivecTaskRegsShow (int task);
|
||||
extern STATUS altivecTaskRegsGet (int task, ALTIVECREG_SET *pAltivecRegSet);
|
||||
extern STATUS altivecTaskRegsSet (int task, ALTIVECREG_SET *pAltivecRegSet);
|
||||
extern STATUS altivecProbe (void);
|
||||
extern void altivecRestore (ALTIVEC_CONTEXT *pAltivecContext);
|
||||
extern void altivecSave (ALTIVEC_CONTEXT *pAltivecContext);
|
||||
extern void altivecRegsToCtx (ALTIVECREG_SET *pAltivecRegSet, ALTIVEC_CONTEXT *pAltivecContext);
|
||||
extern void altivecCtxToRegs (ALTIVEC_CONTEXT *pAltivecContext, ALTIVECREG_SET *pAltivecRegSet);
|
||||
|
||||
#else
|
||||
|
||||
extern void altivecInit ();
|
||||
extern void altivecShowInit ();
|
||||
extern void altivecTaskRegsShow ();
|
||||
extern STATUS altivecTaskRegsGet ();
|
||||
extern STATUS altivecTaskRegsSet ();
|
||||
extern STATUS altivecProbe ();
|
||||
extern void altivecRestore ();
|
||||
extern void altivecSave ();
|
||||
extern void altivecRegsToCtx ();
|
||||
extern void altivecCtxToRegs ();
|
||||
|
||||
#endif /* __STDC__ */
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCaltivecLibh */
|
||||
@@ -0,0 +1,100 @@
|
||||
/* _G_config.h - autogenerated on Tue Feb 3 10:11:41 PST 1998*/
|
||||
|
||||
/* There may be a few (VxWorks related) differences between this file and the
|
||||
* corresponding one in host/$WIND_HOST_TYPE/arm-wrs-vxworks/include
|
||||
*/
|
||||
|
||||
/* AUTOMATICALLY GENERATED; DO NOT EDIT! */
|
||||
#ifndef _G_config_h
|
||||
#define _G_config_h
|
||||
#define _G_LIB_VERSION "2.8.0"
|
||||
#define _G_NAMES_HAVE_UNDERSCORE 1
|
||||
#define _G_VTABLE_LABEL_HAS_LENGTH 1
|
||||
#define _G_VTABLE_LABEL_PREFIX "__vt$"
|
||||
#define _G_HAVE_ST_BLKSIZE 1
|
||||
|
||||
#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 7)
|
||||
typedef int _G_int8_t __attribute__((__mode__(__QI__)));
|
||||
typedef unsigned int _G_uint8_t __attribute__((__mode__(__QI__)));
|
||||
typedef int _G_int16_t __attribute__((__mode__(__HI__)));
|
||||
typedef unsigned int _G_uint16_t __attribute__((__mode__(__HI__)));
|
||||
typedef int _G_int32_t __attribute__((__mode__(__SI__)));
|
||||
typedef unsigned int _G_uint32_t __attribute__((__mode__(__SI__)));
|
||||
typedef int _G_int64_t __attribute__((__mode__(__DI__)));
|
||||
typedef unsigned int _G_uint64_t __attribute__((__mode__(__DI__)));
|
||||
#if defined (__cplusplus)
|
||||
__extension__ typedef long long _G_llong;
|
||||
__extension__ typedef unsigned long long _G_ullong;
|
||||
#else
|
||||
typedef long long _G_llong;
|
||||
typedef unsigned long long _G_ullong;
|
||||
#endif
|
||||
#else
|
||||
typedef short /* deduced */ _G_int16_t;
|
||||
typedef unsigned short /* deduced */ _G_uint16_t;
|
||||
typedef long /* deduced */ _G_int32_t;
|
||||
typedef unsigned long /* deduced */ _G_uint32_t;
|
||||
#endif
|
||||
|
||||
typedef unsigned long _G_clock_t;
|
||||
typedef short _G_dev_t;
|
||||
typedef long _G_fpos_t;
|
||||
typedef unsigned short _G_gid_t;
|
||||
typedef unsigned short _G_ino_t;
|
||||
typedef int _G_mode_t;
|
||||
typedef unsigned short _G_nlink_t;
|
||||
typedef long _G_off_t;
|
||||
typedef int _G_pid_t;
|
||||
#ifndef __PTRDIFF_TYPE__
|
||||
#define __PTRDIFF_TYPE__ long int
|
||||
#endif
|
||||
typedef __PTRDIFF_TYPE__ _G_ptrdiff_t;
|
||||
typedef unsigned long _G_sigset_t;
|
||||
#ifndef __SIZE_TYPE__
|
||||
#define __SIZE_TYPE__ long unsigned int
|
||||
#endif
|
||||
typedef __SIZE_TYPE__ _G_size_t;
|
||||
typedef long _G_time_t;
|
||||
typedef unsigned short _G_uid_t;
|
||||
typedef int _G_wchar_t;
|
||||
|
||||
#define _G_BUFSIZ 1024
|
||||
#define _G_FOPEN_MAX 20
|
||||
#define _G_FILENAME_MAX 1024
|
||||
#if defined (__cplusplus) || defined (__STDC__)
|
||||
#define _G_ARGS(ARGLIST) ARGLIST
|
||||
#else
|
||||
#define _G_ARGS(ARGLIST) ()
|
||||
#endif
|
||||
#if !defined (__GNUG__) || defined (__STRICT_ANSI__)
|
||||
#define _G_NO_NRV
|
||||
#endif
|
||||
#if !defined (__GNUG__)
|
||||
#define _G_NO_EXTERN_TEMPLATES
|
||||
#endif
|
||||
typedef int /* default */ _G_ssize_t;
|
||||
typedef int /* default */ _G_wint_t;
|
||||
typedef void * _G_va_list;
|
||||
#define _G_signal_return_type void
|
||||
#define _G_sprintf_return_type int
|
||||
#define _G_HAVE_ATEXIT 0
|
||||
#define _G_HAVE_SYS_RESOURCE 0
|
||||
#define _G_HAVE_SYS_TIMES 1
|
||||
#define _G_HAVE_SYS_SOCKET 0
|
||||
#define _G_HAVE_SYS_CDEFS 0
|
||||
#define _G_HAVE_SYS_WAIT 1
|
||||
#define _G_HAVE_UNISTD 1
|
||||
#define _G_HAVE_DIRENT 0
|
||||
#define _G_HAVE_CURSES 0
|
||||
#define _G_MATH_H_INLINES 0
|
||||
#define _G_HAVE_BOOL 1
|
||||
#define _G_HAVE_PRINTF_FP 0
|
||||
#define _G_HAVE_LONG_DOUBLE_IO 0
|
||||
#undef NULL
|
||||
#ifdef __cplusplus
|
||||
#define NULL __null
|
||||
#else
|
||||
#define NULL 0
|
||||
#endif
|
||||
#include <stddef.h>
|
||||
#endif /* !_G_config_h */
|
||||
@@ -0,0 +1,397 @@
|
||||
/* archArm.h - ARM specific header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996, 1998, 1999, 2001, 2003-2011, 2013
|
||||
* Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
02t,01jun13,yjw update for ARMARCH7M
|
||||
02s,12aug11,jb WIND00238999 Limit Device Power Mgmt to ARMARCH7
|
||||
02r,17nov10,dbr define _WRS_ARCH_HAS_DEV_PWR_MGMT for device power management
|
||||
02q,16sep10,gls added VX_OBJ_ALIGN_SIZE
|
||||
02p,29jul10,pad Moved extern C statement after include statements.
|
||||
02o,27aug10,rlp Added _WRS_ARCH_HAS_VXDBG_BP_ADDR_CHECK macro.
|
||||
02n,24aug10,jdw Fix _WRS_REV_INSN_SET_CHANGE for Thumb2
|
||||
02m,09jun10,m_h Thumb-2 Support
|
||||
02l,10mar10,j_b define _WRS_PHYS_ADDR_IS_64_BITS for XScale, ARMv6+
|
||||
(WIND00129408)
|
||||
02k,20oct09,z_l add SMP support for ARMARCH7
|
||||
02j,25feb09,j_b merge ARM SMP support, incl adding VSB header file:
|
||||
22feb08,j_b replace intUnlock with intCpuUnlock
|
||||
12nov07,jmp Define _WRS_ARCH_HAS_VXDBG_CPU_CTRL_SUPPORT
|
||||
02nov07,jb Add coherency flag for SMP and build exclusions
|
||||
10oct07,j_b define _WRS_ARCH_HAS_DBG_IPI
|
||||
02i,27feb09,m_h ARMARCH7 Support
|
||||
02h,31jul08,tcr change macro for compatibility
|
||||
02g,19may08,tcr update SV instrumentation
|
||||
02f,16aug07,j_b added _WRS_MMU_HAS_MAP_STATE_API
|
||||
02e,08jun07,j_b Add definition for _WRS_VX_NO_GLOBAL_ERRNO
|
||||
02d,21may07,j_b define _WRS_ARCH_HAS_IDLE_TASK, VX_MAX_SMP_CPUS
|
||||
02c,04may07,zl updated portable library build configuration,
|
||||
added _WRS_CPU_HAS_CLZ_INSTR.
|
||||
02b,21feb07,jmg Added include vxPortableP.h
|
||||
02a,11dec06,kk removed references to _WRS_BASE6_SCHEDULER, no longer needed
|
||||
01z,21jun06,jb Re-enable fast ffs for arch5, make ARMARCH6 64 bit PHYS_ADDR
|
||||
01y,02mar06,jb Fix for SPR 118321 - vfp references in 920t
|
||||
01x,01feb06,jb Adding VFP Support
|
||||
01w,12jan06,jb Enabling 920t variant support
|
||||
01v,10jan06,hya Add ARM CPU variant code for FFS(x) (WRN)
|
||||
01u,19dec05,jb Changing XSCALE to 64 bit PHYS_ADDR
|
||||
01t,24aug05,h_k Added _WRS_SUPPORT_CACHE_XLATE.
|
||||
01s,12apr05,kk remove _WRS_OBJLIB_SUPPORT_VERIFY_TRAP macro (SPR# 106486)
|
||||
01r,28mar05,scm add _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
|
||||
01q,18feb05,dbt Moved some loader specific macros to elfArm.h.
|
||||
01p,17feb05,scm add _WRS_OSM_INIT definition, and clarify
|
||||
PORTABLE/NON-PORTABLE inclussion
|
||||
01o,17jan05,jb Adding architecture specific objVerify support
|
||||
01n,08sep04,scm move INSTR to archArmCommon.h
|
||||
01m,10aug04,scm undef "OPTIMIZE", define "PORTABLE"...
|
||||
01l,27apr04,cjj Defined workQLib_PORTABLE
|
||||
01k,01dec03,scm clean up, SPR #90358... remove obnoxious warning...
|
||||
01j,25nov03,pes Move setting of _BYTE_ORDER macro into archArmCommon.h
|
||||
01i,14nov03,job Moved some blib stuff to archArmCommon.h
|
||||
01h,13nov03,pes Add include of archArmCommon.h
|
||||
01h,29oct03,sn gcc 3.3.2 does not currently support arm or sh
|
||||
01g,27aug03,to added defines for semLib.
|
||||
01f,07may03,pes PAL conditional compilation cleanup. Phase 2.
|
||||
01e,29apr03,pes PAL conditional compilation cleanup.
|
||||
01d,13mar01,sn SPR 73723 - define supported toolchains
|
||||
01c,20jan99,cdp removed support for old ARM libraries.
|
||||
01b,17aug98,cdp added big-endian and multiple cachelib support.
|
||||
01a,08may96,cdp written based on archI86.h
|
||||
*/
|
||||
|
||||
#ifndef __INCarchArmh
|
||||
#define __INCarchArmh
|
||||
|
||||
#include <vsbConfig.h>
|
||||
|
||||
/* In the cases where vxWorks.h is not defined first... */
|
||||
|
||||
#if !defined (TRUE)
|
||||
#define TRUE 1
|
||||
#endif
|
||||
|
||||
#if !defined (FALSE)
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#undef _ARCH_SUPPORTS_GCC
|
||||
#define _ARCH_SUPPORTS_DCC
|
||||
|
||||
/* define to indicate ARM supports device power management */
|
||||
|
||||
#if (CPU==ARMARCH7) || (CPU==ARMARCH7_T2)
|
||||
#define _WRS_ARCH_HAS_DEV_PWR_MGMT
|
||||
#endif /* (CPU==ARMARCH7) || (CPU==ARMARCH7_T2) */
|
||||
|
||||
/* temporary macro to indicate ARM uses the idle task stack */
|
||||
|
||||
#define _WRS_ARCH_HAS_IDLE_TASK
|
||||
|
||||
/* temporary define to indicate ARM uses task-specific errnos */
|
||||
|
||||
#define _WRS_VX_NO_GLOBAL_ERRNO
|
||||
|
||||
/* temporary define to indicate ARM supports MMU state info with map request */
|
||||
|
||||
#define _WRS_MMU_HAS_MAP_STATE_API
|
||||
|
||||
/* temporary macro to indicate ARM has Debug IPI */
|
||||
|
||||
#define _WRS_ARCH_HAS_DBG_IPI
|
||||
|
||||
/* indicates that ARM has VxDBG CPU control support */
|
||||
|
||||
#define _WRS_ARCH_HAS_VXDBG_CPU_CTRL_SUPPORT
|
||||
|
||||
/*
|
||||
* Indicate that the ARM architecture has the VxDBG support to check the
|
||||
* alignment of the breakpoint address.
|
||||
*/
|
||||
|
||||
#define _WRS_ARCH_HAS_VXDBG_BP_ADDR_CHECK
|
||||
|
||||
#undef VX_MAX_SMP_CPUS
|
||||
#define VX_MAX_SMP_CPUS 4 /* maximum processors in SMP configuration */
|
||||
|
||||
/*
|
||||
* For SMP, any shared data region that is created from the RAM need
|
||||
* to be memory coherent.
|
||||
* So we need to set the page attribute to MMU_ATTR_CACHE_COHERENCY.
|
||||
* The arches, need to specify this via the macro
|
||||
* VM_DEFAULT_CACHE_COHERENCY_ATTR
|
||||
*/
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
|
||||
/* Limit SMP build to ARMARCH6 and ARMARCH7 little endian */
|
||||
|
||||
#if ((CPU == ARMARCH6) || (CPU == ARMARCH7)) && !defined(ARMEB) && !defined(__ARMEB__)
|
||||
#define VM_DEFAULT_CACHE_COHERENCY_ATTR MMU_ATTR_CACHE_COHERENCY
|
||||
#else
|
||||
#error SMP build is NOT supported by this architecture/tool combination
|
||||
#endif /* (CPU == ARMARCH6) && !defined(ARMEB) && !defined(__ARMEB__) */
|
||||
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#define _DYNAMIC_BUS_SIZING FALSE /* require alignment for swap */
|
||||
|
||||
#define _ARCH_MULTIPLE_CACHELIB TRUE /* multiple cache libraries */
|
||||
|
||||
/* macros for AIM Cache */
|
||||
|
||||
#define _WRS_SUPPORT_CACHE_XLATE /* cache virt-phys translate */
|
||||
|
||||
#if !defined(ARMCPU920T)
|
||||
|
||||
/* Say VFP is Supported */
|
||||
|
||||
#define _WRS_HW_VFP_SUPPORT
|
||||
|
||||
#endif /* !defined(ARMCPU920T) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if ((CPU == XSCALE) || (CPU == ARMARCH6) || (CPU == ARMARCH7) \
|
||||
|| (CPU == ARMARCH7_T2))
|
||||
|
||||
/* physical addresses are represented with 64 bits for these CPUs */
|
||||
|
||||
#define _TYPE_PHYS_ADDR typedef UINT64 PHYS_ADDR
|
||||
#define _WRS_PHYS_ADDR_IS_64_BITS
|
||||
#endif /* ((CPU == XSCALE, ARMARCH6, ARMARCH7, ARMARCH7_T2)) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#include "arm.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* PAL additions */
|
||||
|
||||
/*
|
||||
* VX_OBJ_ALIGN_SIZE is the default allocation boundary for kernel objects.
|
||||
* This is used for both statically and dynamically allocated objects.
|
||||
*/
|
||||
|
||||
#define VX_OBJ_ALIGN_SIZE 8 /* 8-byte alignment */
|
||||
|
||||
/* moved here from h/private/eventP.h */
|
||||
|
||||
/*
|
||||
* (Borrowed from PPC.)
|
||||
*
|
||||
* Macro for event logging of intEnt events for ARM architectures.
|
||||
* The ARM architecture is different in that there is only one external
|
||||
* interrupt line coming into the CPU. At the time of the intEnt, the
|
||||
* external interrupt number is unknown, meaning that logging cannot
|
||||
* take place at this time. In this architecture, the logging of an
|
||||
* intEnt event is deferred until the interrupt controller driver
|
||||
* is executed.
|
||||
* Since the logging has to take place in drivers and/or BSP world files,
|
||||
* the details of how the logging to be done has been deferred to a macro
|
||||
* which is defined here.
|
||||
*
|
||||
* Note: This replaces the previous technique of saving the timestamp
|
||||
* during the intEnt code to be used later, when the logging was done.
|
||||
* SPR 21868 refers to a problem in which this can give rise to out-of-order
|
||||
* timestamps in the event log.
|
||||
*/
|
||||
|
||||
#define WV_EVT_INT_ENT(intNum) EVT_CTX_1(EVENT_INT_ENTER, intNum);
|
||||
|
||||
/* moved here from h/private/classLibP.h */
|
||||
|
||||
#define OBJ_CLASS_initRtn 0x24 /* Offsets into OBJ_CLASS */
|
||||
|
||||
/* status codes */
|
||||
|
||||
#define S_vmLib_NO_FREE_REGIONS (M_vmLib | 6)
|
||||
#define S_vmLib_ADDRS_NOT_EQUAL (M_vmLib | 7)
|
||||
|
||||
/* from dbgLib.c */
|
||||
|
||||
#define _WRS_FRAME_PRINT_STRING " : "
|
||||
|
||||
/* from loadElfLib.c */
|
||||
|
||||
#define _WRS_USE_ELF_LOAD_FORMAT
|
||||
|
||||
/* from periodHost.c, repeatHost.c, shell.c, and taskLib.c */
|
||||
|
||||
#if (ARM_THUMB) || (ARM_THUMB2)
|
||||
#define _WRS_CHANGE_INSN_SET_ENABLE
|
||||
#define _WRS_CHANGE_INSN_SET(p) (p) = ((FUNCPTR)(((UINT32)(p))|1))
|
||||
#define _WRS_CHANGE_INSN_SET_PTR(p) ((FUNCPTR)(((UINT32)(p))|1))
|
||||
#define _WRS_REV_INSN_SET_CHANGE(p) ((FUNCPTR)(((UINT32)(p)) & ~1))
|
||||
#endif /* ARM_THUMB || (ARM_THUMB2) */
|
||||
|
||||
/* OSM support for stack protection, used in sysOsmLib.c */
|
||||
|
||||
#define _WRS_OSM_INIT
|
||||
|
||||
/* Interrupt stack protection, used in usrDepend.c and usrKernelStack.c */
|
||||
|
||||
#define _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
|
||||
|
||||
/*
|
||||
* if OSM support not available for stack protection,
|
||||
* then support can not be available for interrupt
|
||||
* stack protection.
|
||||
*/
|
||||
|
||||
#if !defined(_WRS_OSM_INIT)
|
||||
#undef _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
|
||||
#endif
|
||||
|
||||
#if defined(_ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK)
|
||||
#undef _WRS_SVC_INT_STACK
|
||||
#undef _WRS_IRQ_INT_STACK
|
||||
#undef _WRS_DUAL_INT_STACK
|
||||
#undef _WRS_SPLIT_STACKS
|
||||
#else
|
||||
|
||||
/*
|
||||
* Old split interrupt stack method...,
|
||||
* not used when OSM stack protection is
|
||||
* enabled...
|
||||
*/
|
||||
|
||||
/* from usrLib.c */
|
||||
|
||||
#define _WRS_SVC_INT_STACK
|
||||
#define _WRS_IRQ_INT_STACK
|
||||
#define _WRS_DUAL_INT_STACK
|
||||
|
||||
/* from kernelLib.c */
|
||||
|
||||
/*
|
||||
* The ARM family uses 3 interrupt stacks. The ratio of the sizes of
|
||||
* these stacks is dependent on the interrupt structure of the board
|
||||
* and so is handled in the BSP code. Note that FIQ is now external to
|
||||
* VxWorks.
|
||||
*/
|
||||
|
||||
#define _WRS_SPLIT_STACKS {if (_func_armIntStackSplit != NULL) \
|
||||
(_func_armIntStackSplit)(vxIntStackBase, intStackSize);}
|
||||
#endif /* _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK */
|
||||
|
||||
/* from xdr_float.c */
|
||||
|
||||
#define FLOAT_NORM
|
||||
|
||||
/* Set to force the use of the big-endian call to XDR_GETLONG() */
|
||||
|
||||
#define _WRS_XDR_FORCE_BE
|
||||
|
||||
#define _WRS_ENABLE_IDLE_INTS {intCpuUnlock(0);}
|
||||
|
||||
/* macros for getting frame and return PC from a jmp_buf */
|
||||
|
||||
#define _WRS_FRAMEP_FROM_JMP_BUF(env) ((char *) (env)[0].reg.reg_sp)
|
||||
#define _WRS_RET_PC_FROM_JMP_BUF(env) ((INSTR *) (env)[0].reg.reg_pc)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <arch/arm/archArmCommon.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* variants that support the clz instruction, "count leading zeroes" */
|
||||
|
||||
#if ((CPU == XSCALE) || (CPU == ARMARCH6) || (CPU == ARMARCH5) \
|
||||
|| (CPU == ARMARCH7) || (CPU == ARMARCH7_T2) || (CPU == ARMARCH7M))
|
||||
#define _WRS_CPU_HAS_CLZ_INSTR
|
||||
#endif /* CPU = XSCALE ... ARMARCH7_T2 */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#ifdef _WRS_CPU_HAS_CLZ_INSTR
|
||||
|
||||
/* optimize FFS(x) in network code for CPUs supporting clz instruction */
|
||||
|
||||
#undef FFS
|
||||
#define FFS(x) (31 - _countLeadingZeroes(x))
|
||||
|
||||
#if defined (__GNUC__)
|
||||
|
||||
/*
|
||||
* Return the number of zero bits in bit positions more significant
|
||||
* than the first set bit.
|
||||
* We don't have to handle the x=0 case, this is only called
|
||||
* when x != 0. Returns a value y in the range 31 >= y >= 0.
|
||||
* 0 indicates the most significant bit.
|
||||
*/
|
||||
|
||||
static __inline__ unsigned int _countLeadingZeroes
|
||||
(
|
||||
unsigned int x
|
||||
)
|
||||
{
|
||||
unsigned int y;
|
||||
|
||||
__asm__ ("clz %0, %1"
|
||||
: "=r" (y)
|
||||
: "r" (x)
|
||||
);
|
||||
|
||||
return y;
|
||||
}
|
||||
#elif defined (_DIAB_TOOL)
|
||||
|
||||
#pragma pure_function _countLeadingZeroes
|
||||
|
||||
__asm unsigned int _countLeadingZeroes
|
||||
(
|
||||
unsigned int x
|
||||
)
|
||||
{
|
||||
% reg x
|
||||
! "r0"
|
||||
clz r0, x
|
||||
}
|
||||
|
||||
#else /* !_DIAB_TOOL */
|
||||
|
||||
/* Unknown compiler, use default */
|
||||
|
||||
#undef FFS
|
||||
#define FFS(x) (ffsMsb(x) - 1)
|
||||
|
||||
#endif /* _DIAB_TOOL */
|
||||
|
||||
#else /* _WRS_CPU_HAS_CLZ_INSTR */
|
||||
|
||||
/* use default */
|
||||
|
||||
#undef FFS
|
||||
#define FFS(x) (ffsMsb(x) - 1)
|
||||
|
||||
#endif /* _WRS_CPU_HAS_CLZ_INSTR */
|
||||
#endif /* ! _ASMLANGUAGE */
|
||||
|
||||
/* End PAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCarchArmh */
|
||||
@@ -0,0 +1,82 @@
|
||||
/* archArmCommon.h - common Arm architecture specific header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2003-2004, 2006-2007, 2010, 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01l,21mar12,jpb Updated for POSIX namespace isolation conformance (part of
|
||||
defect Defect WIND000307800).
|
||||
01k,22jul10,jdw Update size of INSTR for Thumb2
|
||||
01j,09jun10,fao add SWAP32_BE8 and SWAP16_BE8 macro.
|
||||
01i,04may07,zl updated portable library build configuration.
|
||||
01h,02feb06,mil Updated for POSIX namespace conformance.
|
||||
01g,08sep04,scm move INSTR from archArm.h
|
||||
01e,25aug04,scm move to portable trcLib...
|
||||
01d,03aug04,scm Enable Coprocessor Abstraction, disable Portable trcLib.
|
||||
01c,25nov03,pes Move setting of _BYTE_ORDER macro into archArmCommon.h
|
||||
01b,12nov03,job Moved some blib stuff from archArm.h
|
||||
01a,11nov03,pes written.
|
||||
*/
|
||||
|
||||
#ifndef __INCarchArmCommonh
|
||||
#define __INCarchArmCommonh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(ARMEB) || defined(__ARMEB__)
|
||||
#define _BYTE_ORDER _BIG_ENDIAN
|
||||
#else
|
||||
#define _BYTE_ORDER _LITTLE_ENDIAN
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#if ((ARM_THUMB) || (ARM_THUMB2))
|
||||
typedef unsigned short _Vx_INSTR; /* 16 bit instructions */
|
||||
#else /* ((ARM_THUMB) || (ARM_THUMB2)) */
|
||||
typedef unsigned long _Vx_INSTR; /* 32 bit word-aligned instructions */
|
||||
#endif /* ((ARM_THUMB) || (ARM_THUMB2)) */
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#if !defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE) && \
|
||||
!defined(_POSIX_AEP_RT_CONTROLLER_C_SOURCE)
|
||||
|
||||
#ifdef ARMBE8
|
||||
#define SWAP32_BE8(x) ((((x) & 0x000000ff) << 24) | \
|
||||
(((x) & 0x0000ff00) << 8) | \
|
||||
(((x) & 0x00ff0000) >> 8) | \
|
||||
(((x)) >> 24))
|
||||
#define SWAP16_BE8(x) ((((x) & 0x00ff0000) >> 8) | \
|
||||
(((x)) >> 24))
|
||||
#else
|
||||
#define SWAP32_BE8(x) x
|
||||
#define SWAP16_BE8(x) x
|
||||
#endif /* ARMBE8 */
|
||||
|
||||
/* from bLib.c */
|
||||
|
||||
#define _WRS_BLIB_ALIGNMENT 3 /* quad byte alignment mask */
|
||||
#define _WRS_IMPROVED_PORTABLE_SWAB
|
||||
|
||||
/* Enable Coprocessor Abstraction. Must do all or none. */
|
||||
|
||||
#define _WRS_PAL_COPROC_LIB
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
typedef _Vx_INSTR INSTR;
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
#endif /* !_POSIX_xxx_SOURCE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCarchArmCommonh */
|
||||
@@ -0,0 +1,284 @@
|
||||
|
||||
/* arm-m.h - ARM CPU registers and flags for ARM-M architecture */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012-2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01f,01aug13,yjw add cache support
|
||||
01e,03aug12,jdw Add boot macro _WRS_ARM_BOOT_THUMB2
|
||||
01d,06jun12,j_b add core control registers and initialization values
|
||||
01c,29may12,j_b add control and configuration registers
|
||||
01b,24may12,m_h Add CPUID address
|
||||
01a,03feb12,jdw Created
|
||||
*/
|
||||
|
||||
#ifndef __INCarm_mh
|
||||
#define __INCarm_mh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
extern int cacheArchAlignSize;
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#undef _CACHE_ALIGN_SIZE
|
||||
#define _CACHE_ALIGN_SIZE cacheArchAlignSize
|
||||
|
||||
/* Define Arch features which are supported by ARM-M */
|
||||
|
||||
/* ARM-M only operates in Thumb2 mode */
|
||||
|
||||
#define ARM_THUMB2 TRUE
|
||||
#define PORTABLE
|
||||
|
||||
/* multiple cache libraries */
|
||||
|
||||
#define _ARCH_MULTIPLE_CACHELIB TRUE
|
||||
|
||||
/* ARMv7-M support exclusive load/store */
|
||||
|
||||
#define ARM_HAS_LDREX_STREX TRUE
|
||||
|
||||
#define ARM_HAS_HALFWORD_INSTRUCTIONS TRUE
|
||||
|
||||
/* MPU is optional on some ARM-M cores */
|
||||
|
||||
#define ARM_HAS_NO_MMU TRUE
|
||||
|
||||
/* ARM-M always boots in Thumb2 mode */
|
||||
|
||||
#define _WRS_ARM_BOOT_THUMB2 TRUE
|
||||
|
||||
#define _WRS_ARCH_HAS_CPU_PWR_MGMT
|
||||
|
||||
/* bits in the PSR */
|
||||
|
||||
#define Q_BIT (1<<27)
|
||||
#define V_BIT (1<<28)
|
||||
#define C_BIT (1<<29)
|
||||
#define Z_BIT (1<<30)
|
||||
#define N_BIT (1<<31)
|
||||
#define T_BIT (1<<24)
|
||||
|
||||
/*
|
||||
* On entry to an exception the processor will use xPSR bit 9
|
||||
* to indicate if the SP has been aligned to an 8-byte boundary
|
||||
*/
|
||||
|
||||
#define PSR_STK_ALIGN (1<<9)
|
||||
|
||||
/* masks for getting bits from PSR */
|
||||
|
||||
#define MASK_EXC_NUM 0x000001FF
|
||||
#define MASK_ICIIT 0x0600FC00
|
||||
#define MASK_GE 0x000F0000
|
||||
#define MASK_T 0x01000000
|
||||
#define MASK_CC 0xF8000000
|
||||
|
||||
/* PRIMASK, FAULTMASK, & BASEMASK fields */
|
||||
|
||||
#define PRIMASK_PM 0x00000001
|
||||
#define FAULTMASK_FM 0x00000001
|
||||
#define MASK_BASEPRI 0x000000FF
|
||||
|
||||
/* Bits in EXC_RETURN */
|
||||
|
||||
#define EXC_RTN_BASE 0xFFFFFFF1
|
||||
#define EXC_RTN_MODE_THREAD 0x00000008
|
||||
#define EXC_RTN_MODE_HANDLER 0x00000000
|
||||
#define EXC_RTN_STACK_PROCESS 0x00000004
|
||||
#define EXC_RTN_STACK_MAIN 0x00000000
|
||||
|
||||
#define MASK_EXC_RTN_MODE 0x00000008
|
||||
#define MASK_EXC_RTN_STACK 0x00000004
|
||||
|
||||
|
||||
/*
|
||||
* System Control Block Registers
|
||||
*/
|
||||
|
||||
|
||||
/* CPU ID Base Register */
|
||||
|
||||
#define CORTEXM_CPUID_BASE_REGISTER (0xE000ED00)
|
||||
|
||||
/* Interrupt Controller Type Register */
|
||||
|
||||
#define CORTEXM_ICTR (0xE000E004)
|
||||
|
||||
#define CORTEXM_ICTR_INTNUM_MASK (0xF) /* # of interrupt lines field */
|
||||
#define CORTEXM_ICTR_INTNUM_MAX (0xF) /* # of interrupt lines field max */
|
||||
|
||||
/* Auxiliary Control Register - usage is implementation-defined/core-specific */
|
||||
|
||||
#define CORTEXM_ACTLR (0xE000E008)
|
||||
|
||||
/* Interrupt Controller State Register */
|
||||
|
||||
#define CORTEXM_ICSR (0xE000ED04)
|
||||
|
||||
/* Vector Table Offset Register */
|
||||
|
||||
#define CORTEXM_VTOR (0xE000ED08)
|
||||
|
||||
#define CORTEXM_VTOR_MASK (0xFFFFFF80) /* reserved bits 6:0 */
|
||||
|
||||
/*
|
||||
* Application Interrupt and Reset Control Register
|
||||
*
|
||||
* Note that the proper access key must be included in a write to this
|
||||
* regsiter or the write is ignored.
|
||||
*/
|
||||
|
||||
#define CORTEXM_AIRCR (0xE000ED0C)
|
||||
|
||||
#define CORTEXM_AIRCR_VECTKEY 0x05FA0000 /* Access Key for writes */
|
||||
#define CORTEXM_AIRCR_VECTKEY_MASK 0xFFFF0000 /* (0xFA05 is the read value) */
|
||||
|
||||
#define CORTEXM_AIRCR_PRIGROUP_SHIFT 8 /* Priority Group */
|
||||
#define CORTEXM_AIRCR_PRIGROUP_MASK (0x7 << CORTEXM_AIRCR_PRIGROUP_SHIFT)
|
||||
|
||||
/* System Control and Register */
|
||||
|
||||
#define CORTEXM_SCR (0xE000ED10)
|
||||
|
||||
/* Configuration and Control Register */
|
||||
|
||||
#define CORTEXM_CCR (0xE000ED14)
|
||||
|
||||
#define CORTEXM_CCR_DIV0TRP (0x00000010) /* divide by zero trap enable */
|
||||
#define CORTEXM_CCR_STKALIGN (0x00000200) /* 8-byte stacking align enable */
|
||||
|
||||
/*
|
||||
* System Handler Priority Level Registers
|
||||
* (aka System Exception Priority Level Registers)
|
||||
*/
|
||||
|
||||
#define CORTEXM_SHPR1 (0xE000ED18) /* Pri lvl for Exceptions 4-7 */
|
||||
#define CORTEXM_SHPR2 (0xE000ED1C) /* Pri lvl for Exceptions 8-11 */
|
||||
#define CORTEXM_SHPR3 (0xE000ED20) /* Pri lvl for Exceptions 12-15 */
|
||||
|
||||
/*
|
||||
* Note: SHPR actually starts with PRI_4. There is no such thing as PRI_0 but
|
||||
* this makes the address calculation easier.
|
||||
*/
|
||||
|
||||
#define CORTEXM_SHPR_PRI_0 (0xE000ED14)
|
||||
#define CORTEXM_SHPR_PRI_15 (0xE000ED23)
|
||||
|
||||
#define CORTEXM_SHPR_PENDSV (CORTEXM_SHPR_PRI_14)
|
||||
#define CORTEXM_SHPR_SYSTICK (CORTEXM_SHPR_PRI_15)
|
||||
|
||||
/* system priority register address, calculated by exception # (= offset) */
|
||||
|
||||
#define CORTEXM_SHPR_PRI_BYTE(n) (CORTEXM_SHPR_PRI_0 + (n))
|
||||
|
||||
/* System Handler Control and State Register */
|
||||
|
||||
#define CORTEXM_SHCSR (0xE000ED24)
|
||||
|
||||
#define CORTEXM_SHCSR_USGFLT_EN (0x00040000) /* Usage Fault Enable bit */
|
||||
#define CORTEXM_SHCSR_BUSFLT_EN (0x00020000) /* Bus Fault Enable bit */
|
||||
#define CORTEXM_SHCSR_MEMFLT_EN (0x00010000) /* Memory Mgt Fault Enable bit */
|
||||
|
||||
#define CORTEXM_SHCSR_SVC_PEND (0x00008000) /* SVCall Pending bit */
|
||||
#define CORTEXM_SHCSR_BUSFLT_PEND (0x00004000) /* Bus Fault Pend bit */
|
||||
#define CORTEXM_SHCSR_MEMFLT_PEND (0x00002000) /* Memory Mgt Pend bit */
|
||||
#define CORTEXM_SHCSR_USGFLT_PEND (0x00001000) /* Usage Fault Pend bit */
|
||||
|
||||
#define CORTEXM_SHCSR_SYSTCK_ACT (0x00000800) /* SysTick Active bit */
|
||||
#define CORTEXM_SHCSR_PENDSV_ACT (0x00000400) /* PendSV Active bit */
|
||||
#define CORTEXM_SHCSR_DBGMON_ACT (0x00000100) /* Debug Monitor Active */
|
||||
#define CORTEXM_SHCSR_SVC_ACT (0x00000080) /* SVCall Active */
|
||||
#define CORTEXM_SHCSR_USGFLT_ACT (0x00000008) /* Usage Fault Active */
|
||||
#define CORTEXM_SHCSR_BUSFLT_ACT (0x00000002) /* Usage Fault Active */
|
||||
#define CORTEXM_SHCSR_MEMFLT_ACT (0x00000001) /* Usage Fault Active */
|
||||
|
||||
/* Debug Exception and Monitor Control Register */
|
||||
|
||||
#define CORTEXM_DEMCR (0xE000EDFC)
|
||||
#define CORTEXM_DEMCR_MON_STEP (0x00040000)
|
||||
#define CORTEXM_DEMCR_MON_PEND (0x00020000)
|
||||
#define CORTEXM_DEMCR_MON_EN (0x00010000)
|
||||
|
||||
/* ROM table for debug */
|
||||
|
||||
#define CORTEXM_ROM_TABLE (0xE00FF000)
|
||||
#define CORTEXM_ROM_TABLE_FPB_OFFSET (0x00000008)
|
||||
#define CORTEXM_FPB_VALID (0xFFF03003)
|
||||
|
||||
/* FlashPatch Control Register */
|
||||
|
||||
#define CORTEXM_FP_CTRL (0xE0002000)
|
||||
#define CORTEXM_FP_CTRL_ENABLE (3)
|
||||
|
||||
/* FlashPatch Comparatorregister */
|
||||
|
||||
#define CORTEXM_FP_COMP0 (0xE0002008)
|
||||
|
||||
/*
|
||||
* Configurable Fault Status Register
|
||||
* This register includes the:
|
||||
* - 8-bit Memory Management Fault Status Register
|
||||
* - 8-bit Bus Fault Status Register; and
|
||||
* - 16-bit Usage Fault Status Register;
|
||||
*/
|
||||
|
||||
#define CORTEXM_CFSR (0xE000ED28)
|
||||
#define CORTEXM_BFSR_SHIFT (8) /* Bus Fault Status bit shift */
|
||||
#define CORTEXM_UFSR_SHIFT (16) /* Usage Fault Status bit shift */
|
||||
|
||||
#define CORTEXM_DFSR (0xE000ED30)
|
||||
#define CORTEXM_HALTED (0x1) /* trace */
|
||||
#define CORTEXM_BKPT (0x2) /* FPB break point */
|
||||
|
||||
#define CORTEXM_MMFSR CORTEXM_CFSR /* Mem Manage Fault Status byte */
|
||||
#define CORTEXM_MMFSR_FARVALID (0x80) /* fault address valid mask */
|
||||
|
||||
#define CORTEXM_BFSR (0xE000ED29) /* Bus Fault Status byte */
|
||||
#define CORTEXM_BFSR_FARVALID (0x80) /* fault address valid mask */
|
||||
|
||||
#define CORTEXM_UFSR (0xE000ED2A) /* Usage Fault Status halfword */
|
||||
|
||||
/* Usage Fault Status fields */
|
||||
|
||||
#define CORTEXM_UFSR_DIV0 (0x00000200) /* Divide by Zero */
|
||||
#define CORTEXM_UFSR_UNALIGN (0x00000100) /* Unaligned Access */
|
||||
#define CORTEXM_UFSR_NOCP (0x00000008) /* Coprocessor Access */
|
||||
#define CORTEXM_UFSR_INVPC (0x00000004) /* Invalid EXC_RETURN */
|
||||
#define CORTEXM_UFSR_INVSTATE (0x00000002) /* Invalid State */
|
||||
#define CORTEXM_UFSR_UNDEF (0x00000001) /* Undefined Instruction */
|
||||
|
||||
/* Hard Fault Status Register */
|
||||
|
||||
#define CORTEXM_HFSR (0xE000ED2C)
|
||||
|
||||
#define CORTEXM_HFSR_FORCED (0x40000000) /* escalated configurable fault */
|
||||
/* (bus/mem mgt/usage fault) */
|
||||
#define CORTEXM_HFSR_CLRALL (0xC0000002) /* clear all Hard faults */
|
||||
|
||||
/* Memory Manage Fault Address Register */
|
||||
|
||||
#define CORTEXM_MMFAR (0xE000ED34)
|
||||
|
||||
/* Bus Fault Address Register */
|
||||
|
||||
#define CORTEXM_BFAR (0xE000ED38)
|
||||
|
||||
/* MPU Control Register */
|
||||
|
||||
#define CORTEXM_MPU_CTRL (0xE000ED94)
|
||||
|
||||
/* Software Trigger Interrupt Register */
|
||||
|
||||
#define CORTEXM_STIR (0xE000EF00)
|
||||
|
||||
#define INVALID_INST (0xFF00FF00) /* invalid opcode */
|
||||
#endif /* __INCarm_mh */
|
||||
@@ -0,0 +1,57 @@
|
||||
/* esfArm-m.h - ARM exception stack frames */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,10may12,j_b fix tabs/spacing
|
||||
01b,03may12,j_b replace "-" in filename include macro
|
||||
01a,03apr12,j_b created from target/h/arch/arm/esfArm.f version 01b
|
||||
*/
|
||||
|
||||
#ifndef __INCesfArm_mh
|
||||
#define __INCesfArm_mh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* The Exception Stack Frame
|
||||
* On ARMv7-M, this is faked by a stub and the pointer
|
||||
* passed back points to the PC and PSR at the end of the
|
||||
* register structure. If that changes, so must this.
|
||||
*
|
||||
* I.E., REG_SET struct & ESF struct 'overlap' on last 4
|
||||
* elements of REG_SET (pc, psr, primask and basepri).
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
INSTR *pc; /* program counter */
|
||||
ULONG psr; /* combined A/I/E PSR */
|
||||
ULONG basepri; /* BASEPRI */
|
||||
ULONG demcr; /* MON_STEP in DEMCR */
|
||||
ULONG primask; /* PRIMASK */
|
||||
ULONG faultmask; /* FAULTMASK */
|
||||
ULONG control; /* CONTROL */
|
||||
UINT32 vecNum; /* exception number */
|
||||
} ESF;
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCesfArm_mh */
|
||||
@@ -0,0 +1,160 @@
|
||||
/* excArmLib-m.h - ARMv7-M exception library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,05sep12,rec add excClearFault prototype
|
||||
01c,24may12,j_b add fault status to EXC_INFO
|
||||
01b,22may12,jdw Add exception vector offset mapping for scopetools
|
||||
01a,14may12,m_h create from target/h/arch/arm/excArmLib.h version 01f
|
||||
*/
|
||||
|
||||
#ifndef __INCexcArmLib_mh
|
||||
#define __INCexcArmLib_mh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* NOTE: if this structure changes, the TCB offsets in h/private/taskLibP.h
|
||||
* must be updated. See also taskLib.h.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT32 valid; /* flags indicate following fields are valid */
|
||||
UINT32 vecNum; /* exception number */
|
||||
INSTR * pc; /* PC */
|
||||
UINT32 psr; /* combined A/I/E PSR */
|
||||
UINT32 primask; /* PRIMASK */
|
||||
UINT32 faultmask; /* FAULTMASK */
|
||||
UINT32 basepri; /* BASEPRI */
|
||||
UINT32 control; /* Control Register */
|
||||
UINT32 sysHandlrStat; /* System Handler Control and State Register */
|
||||
UINT32 hardFltStat; /* Hard Fault Status Register */
|
||||
UINT32 configFltStat; /* Configurable Fault Status Register */
|
||||
UINT32 memFltAddr; /* Memory Manage Fault Address Register */
|
||||
UINT32 busFltAddr; /* Bus Fault Address Register */
|
||||
} EXC_INFO;
|
||||
|
||||
extern FUNCPTR excExcepHook; /* add'l rtn to call when exceptions occur */
|
||||
extern VOIDFUNCPTR _func_excBreakpoint; /* called to handle breakpoints */
|
||||
|
||||
extern void excVecBaseSet (UINT32 base); /* non-zero exception base address */
|
||||
|
||||
extern STATUS excIntConnect (VOIDFUNCPTR * vector, VOIDFUNCPTR routine);
|
||||
|
||||
extern void excVecSet (FUNCPTR * vector, FUNCPTR function);
|
||||
extern FUNCPTR excVecGet (FUNCPTR * vector);
|
||||
|
||||
extern STATUS excVecPrioSet (VOIDFUNCPTR * vector, UINT8 priority);
|
||||
extern STATUS excVecPrioGet (VOIDFUNCPTR * vector, UINT8 * pPriority);
|
||||
extern void excClearFault (void);
|
||||
|
||||
#endif /* ASMLANGUAGE */
|
||||
|
||||
/* exception information valid bits */
|
||||
|
||||
#define EXC_INFO_VECNUM 0x01 /* vector is valid */
|
||||
#define EXC_INFO_PC 0x02 /* PC is valid */
|
||||
#define EXC_INFO_XPSR 0x04 /* xPSR is valid */
|
||||
#define EXC_INFO_PRIMASK 0x08 /* PRIMASK is valid */
|
||||
#define EXC_INFO_FAULTMASK 0x10 /* FAULTMASK is valid */
|
||||
#define EXC_INFO_BASEPRI 0x20 /* BASEPRI is valid */
|
||||
#define EXC_INFO_CONTROL 0x40 /* Control Register is valid */
|
||||
#define EXC_INFO_SYSHDLRSTAT 0x80 /* System Handler Ctrl/State is valid */
|
||||
#define EXC_INFO_HRDFLTSTAT 0x100 /* Hard Fault Status is valid */
|
||||
#define EXC_INFO_CFGFLTSTAT 0x200 /* Configurable Fault Status is valid */
|
||||
#define EXC_INFO_MEMFLTADDR 0x400 /* Mem Manage Fault Address is valid */
|
||||
#define EXC_INFO_BUSFLTADDR 0x800 /* Bus Fault Address is valid */
|
||||
|
||||
#define EXC_INFO_ALL_VALID 0xFFF /* all EXC_INFO fields are valid */
|
||||
|
||||
/*
|
||||
* Exception Numbers
|
||||
*
|
||||
* Note there is no Exception number 0. If the IPSR contains zero then we are
|
||||
* in thread mode and therefore not servicing an exception or interrupt.
|
||||
*/
|
||||
|
||||
#define EXC_NUM_THREAD_MODE 0 /* IPSR is 0 when in thread mode */
|
||||
|
||||
#define EXC_NUM_RESET 1 /* Reset */
|
||||
#define EXC_NUM_NMI 2 /* Nonmaskable Interrupt */
|
||||
#define EXC_NUM_HARD_FAULT 3 /* unimplemented fault handler */
|
||||
#define EXC_NUM_MEM_MANAGE 4 /* MPU Violation */
|
||||
#define EXC_NUM_BUS_FAULT 5 /* Bus Error */
|
||||
#define EXC_NUM_USAGE_FAULT 6 /* Program error or coprocessor */
|
||||
#define EXC_NUM_SVCALL 11 /* Supervisor Call */
|
||||
#define EXC_NUM_DEBUG_MONITOR 12 /* Debug Monitor */
|
||||
#define EXC_NUM_PENDSV 14 /* PendSV */
|
||||
#define EXC_NUM_SYSTICK 15 /* System Tick Timer */
|
||||
#define EXC_NUM_IRQ_BASE 16 /* First External Interrupt */
|
||||
|
||||
#define EXC_NUM_IRQ(num) (EXC_NUM_IRQ_BASE + (num))
|
||||
|
||||
#define EXC_NUM_LAST_IRQ 511
|
||||
|
||||
/* Exception Vectors
|
||||
*
|
||||
* The values at these offsets are 32-bit addresses of exception handlers.
|
||||
* This is different from traditional arm architectures (such as ARMv7) which
|
||||
* expect branch instructions or some other executable instructions.
|
||||
*
|
||||
* Note: the first entry (entry 0) in the exception vector table is the
|
||||
* initial value of the stack pointer after reset, and not an exception vector
|
||||
* address. Although not actually an exception vector, it is included here
|
||||
* for completeness.
|
||||
*/
|
||||
|
||||
#define EXC_OFF_INITIAL_SP 0x00
|
||||
|
||||
#define EXC_OFF_RESET (EXC_NUM_RESET * 4)
|
||||
#define EXC_OFF_NMI (EXC_NUM_NMI * 4)
|
||||
#define EXC_OFF_HARD_FAULT (EXC_NUM_HARD_FAULT * 4)
|
||||
#define EXC_OFF_MEM_MANAGE (EXC_NUM_MEM_MANAGE * 4)
|
||||
#define EXC_OFF_BUS_FAULT (EXC_NUM_BUS_FAULT * 4)
|
||||
#define EXC_OFF_USAGE_FAULT (EXC_NUM_USAGE_FAULT * 4)
|
||||
#define EXC_OFF_SVCALL (EXC_NUM_SVCALL * 4)
|
||||
#define EXC_OFF_DEBUG_MONITOR (EXC_NUM_DEBUG_MONITOR * 4)
|
||||
#define EXC_OFF_PENDSV (EXC_NUM_PENDSV * 4)
|
||||
#define EXC_OFF_SYSTICK (EXC_NUM_SYSTICK * 4)
|
||||
#define EXC_OFF_IRQ_BASE (EXC_NUM_IRQ_BASE * 4)
|
||||
|
||||
#define EXC_OFF_IRQ(num) (EXC_OFF_IRQ_BASE + ((num)*4))
|
||||
|
||||
#define EXC_OFF_LAST_IRQ EXC_OFF_IRQ(EXC_NUM_LAST_IRQ)
|
||||
|
||||
/* Exception Vector Base */
|
||||
#define ARM_EXC_VEC_BASE 0x00
|
||||
|
||||
/*
|
||||
* Map the traditional ARM definition to the ARM-M exception offset.
|
||||
*/
|
||||
|
||||
/* Scope tools needs to know which vector handles undefined instructions. */
|
||||
#define EXC_OFF_UNDEF (EXC_NUM_USAGE_FAULT)
|
||||
|
||||
/* ObjVerify needs to know which vector handles Page Faults */
|
||||
#define EXC_OFF_DATA (EXC_NUM_MEM_MANAGE)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCexcArmLib_mh */
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,116 @@
|
||||
/* intArmLib.h - ARM-specific interrupt library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,12apr12,jdw created.
|
||||
*/
|
||||
|
||||
#ifndef __INCintArmLibh
|
||||
#define __INCintArmLibh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef _WRS_ENABLE_IRQ_TRACING
|
||||
/*
|
||||
* For tracing we can define some "no-op" instructions which can be
|
||||
* inserted and identified in the ICE trace buffer.
|
||||
*/
|
||||
#define WRS_ICE_TRACE_IRQ_LOCK orr r5,r5,r5
|
||||
#define WRS_ICE_TRACE_IRQ_UNLOCK orr r6,r6,r6
|
||||
#else /* _WRS_ENABLE_IRQ_TRACING */
|
||||
#define WRS_ICE_TRACE_IRQ_LOCK
|
||||
#define WRS_ICE_TRACE_IRQ_UNLOCK
|
||||
#endif /* _WRS_ENABLE_IRQ_TRACING */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* inline intCpuLock()/intCpuUnlock() and intCpuMicroLock/Unlock() */
|
||||
|
||||
#if defined (__DCC__)
|
||||
|
||||
__asm volatile int _inline_intCpuLock ()
|
||||
{
|
||||
! "r0"
|
||||
mrs r0, BASEPRI /* get current status */
|
||||
mov r1, #0x10
|
||||
mrs BASEPRI, r1
|
||||
WRS_ICE_TRACE_IRQ_LOCK
|
||||
}
|
||||
|
||||
__asm volatile void _inline_intCpuUnlock (int key)
|
||||
{
|
||||
% reg key; lab label ! "r0" /* input: key in r0 */
|
||||
|
||||
mrs BASEPRI, r0
|
||||
WRS_ICE_TRACE_IRQ_UNLOCK
|
||||
}
|
||||
|
||||
#elif defined (__GNUC__)
|
||||
|
||||
static __inline__ int _inline_intCpuLock (void)
|
||||
{
|
||||
int key;
|
||||
__asm__ volatile
|
||||
(
|
||||
"mrs r0, BASEPRI; " /* get current status */
|
||||
"mov r1, #0x10 " /* set new status */
|
||||
"mrs BASEPRI, r1 "
|
||||
: "=&r" (key) /* output: key is %0 */
|
||||
: /* no input */
|
||||
: "r0", "r1"
|
||||
);
|
||||
return key;
|
||||
}
|
||||
|
||||
static __inline__ void _inline_intCpuUnlock (int key)
|
||||
{
|
||||
__asm__ volatile
|
||||
(
|
||||
"mrs BASEPRI, r0 " /* set new status */
|
||||
: "r" (key) /* input: key is %0 */
|
||||
: "r0" /* r0, r1 clobbered; memory */
|
||||
/* clobber for code barrier */
|
||||
);
|
||||
}
|
||||
|
||||
#endif /* __DCC__ */
|
||||
|
||||
/*
|
||||
* For ARM-M these functions are identical
|
||||
*/
|
||||
|
||||
#define _inline_intCpuMicroLock() _inline_intCpuLock()
|
||||
#define _inline_intCpuMicroUnlock(key) _inline_intCpuUnlock(key)
|
||||
|
||||
/* functions in intArchLib.c and intALib.s */
|
||||
|
||||
extern STATUS intArchConnect (VOIDFUNCPTR * vector,
|
||||
VOIDFUNCPTR routine, int argument);
|
||||
extern STATUS intArchDisconnect (VOIDFUNCPTR * vector,
|
||||
VOIDFUNCPTR routine, int argument);
|
||||
extern int intLevelSet (int level);
|
||||
|
||||
extern STATUS intEnable (int level);
|
||||
extern STATUS intDisable (int level);
|
||||
|
||||
extern unsigned int getBasePri( void );
|
||||
extern unsigned int setBasePri( unsigned int level );
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCintArmLibh */
|
||||
@@ -0,0 +1,106 @@
|
||||
/* regsArm-m.h - ARMv7-M registers */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,19jul12,jdw Add missing TCB offset register definitions
|
||||
01d,23may12,jdw Add PRIMASK and BASEPRI offsets
|
||||
01c,10may12,j_b fix tabs/spacing
|
||||
01b,03may12,j_b replace "-" in filename include macro
|
||||
01a,03apr12,j_b created from target/h/arch/arm/regsArm.f version 01f
|
||||
*/
|
||||
|
||||
#ifndef __INCregsArm_mh
|
||||
#define __INCregsArm_mh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define GREG_NUM 15 /* has 15 32-bit general registers */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* REG_SET - ARMv7-M Register set
|
||||
* Note that the exception stack frame relies on the order of items
|
||||
* in this so don't change this without changing the ESF and the stub
|
||||
* in excALib which creates it.
|
||||
*/
|
||||
|
||||
typedef struct /* REG_SET - ARMv7-M register set */
|
||||
{
|
||||
ULONG r[GREG_NUM]; /* general purpose registers 0-14 */
|
||||
INSTR *pc; /* program counter */
|
||||
ULONG psr; /* combined A/I/E PSR */
|
||||
ULONG basepri; /* BASEPRI */
|
||||
ULONG demcr; /* MON_STEP in DEMCR */
|
||||
} REG_SET;
|
||||
|
||||
typedef struct wind_cpu_state
|
||||
{
|
||||
REG_SET regs;
|
||||
} WIND_CPU_STATE;
|
||||
|
||||
#define fpReg r[11] /* frame pointer */
|
||||
#define spReg r[13] /* stack pointer */
|
||||
#define lrReg r[14] /* link reg pointer */
|
||||
|
||||
#define reg_pc pc /* program counter */
|
||||
|
||||
#define reg_lr lrReg /* link reg pointer */
|
||||
#define reg_sp spReg /* stack pointer */
|
||||
#define reg_fp fpReg /* frame pointer */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#define ARM_REG_SIZE 4
|
||||
#define REG_SET_G_REG_BASE 0x00 /* data reg's base offset to REG_SET */
|
||||
#define REG_SET_G_REG_OFFSET(n) (REG_SET_G_REG_BASE + (n)*ARM_REG_SIZE)
|
||||
#define REG_SET_PC_OFFSET (REG_SET_G_REG_OFFSET(GREG_NUM))
|
||||
#define REG_SET_CPSR_OFFSET (REG_SET_PC_OFFSET + ARM_REG_SIZE)
|
||||
#define REG_SET_BASEPRI_OFFSET (REG_SET_CPSR_OFFSET + ARM_REG_SIZE)
|
||||
#define REG_SET_DEMCR_OFFSET (REG_SET_BASEPRI_OFFSET + ARM_REG_SIZE)
|
||||
|
||||
#define PC_OFFSET REG_SET_PC_OFFSET
|
||||
|
||||
/* PAL additions */
|
||||
|
||||
/* moved here from h/private/taskLibP.h */
|
||||
|
||||
#define WIND_TCB_R0 WIND_TCB_REGS
|
||||
#define WIND_TCB_R1 (WIND_TCB_R0+4*1)
|
||||
#define WIND_TCB_R2 (WIND_TCB_R0+4*2)
|
||||
#define WIND_TCB_R3 (WIND_TCB_R0+4*3)
|
||||
#define WIND_TCB_R4 (WIND_TCB_R0+4*4)
|
||||
#define WIND_TCB_R5 (WIND_TCB_R0+4*5)
|
||||
#define WIND_TCB_R6 (WIND_TCB_R0+4*6)
|
||||
#define WIND_TCB_R7 (WIND_TCB_R0+4*7)
|
||||
#define WIND_TCB_R8 (WIND_TCB_R0+4*8)
|
||||
#define WIND_TCB_R9 (WIND_TCB_R0+4*9)
|
||||
#define WIND_TCB_R10 (WIND_TCB_R0+4*10)
|
||||
#define WIND_TCB_R11 (WIND_TCB_R0+4*11)
|
||||
#define WIND_TCB_R12 (WIND_TCB_R0+4*12)
|
||||
#define WIND_TCB_SP (WIND_TCB_R0+4*13)
|
||||
#define WIND_TCB_LR (WIND_TCB_R0+4*14)
|
||||
#define WIND_TCB_PC (WIND_TCB_R0+4*15)
|
||||
#define WIND_TCB_CPSR (WIND_TCB_PC+4)
|
||||
#define WIND_TCB_BASEPRI (WIND_TCB_PC+8)
|
||||
#define WIND_TCB_DEMCR (WIND_TCB_PC+12)
|
||||
|
||||
|
||||
/* End PAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCregsArm_mh */
|
||||
@@ -0,0 +1,196 @@
|
||||
/* vfpArmLib.h - Arm Version of Vector Floating-Point Include File */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,07may13,c_t VFPv4 SP written based on standard version
|
||||
*/
|
||||
|
||||
#ifndef __INCvfpArmLibSph
|
||||
#define __INCvfpArmLibSph
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* for cortex M the following register are memory mapped and the addresses
|
||||
* are architectural defined.
|
||||
*/
|
||||
|
||||
/* Coprocessor Access Control Register, CPACR, enable CP10 & CP11 for VFP */
|
||||
|
||||
#define CPACR (0xE000ED88)
|
||||
#define CPACR_CP_FULL(x) (3<<(2*(x))) /* 0b11 : Full access for this cp */
|
||||
|
||||
/* Floating-Point Context Control Register, FPCCR */
|
||||
|
||||
#define FPCCR (0xE000EF34)
|
||||
#define FPCCR_ASPEN (1<<31) /* enable auto FP context stacking */
|
||||
#define FPCCR_LSPEN (1<<30) /* enable lazy FP context stacking */
|
||||
#define FPCCR_MONRDY (1<<8)
|
||||
#define FPCCR_BFRDY (1<<6)
|
||||
#define FPCCR_MMRDY (1<<5)
|
||||
#define FPCCR_HFRDY (1<<4)
|
||||
#define FPCCR_THREAD (1<<3) /* allocated FP stack in thread */
|
||||
#define FPCCR_USER (1<<1) /* allocated FP stack in priviledged */
|
||||
#define FPCCR_LSPACT (1<<0) /* lazy stacking is active */
|
||||
|
||||
/* Floating-Point Context Address Register, FPCAR */
|
||||
/* this register contains the FP context address in the exception stack */
|
||||
|
||||
#define FPCAR (0xE000EF38)
|
||||
|
||||
/* Floating-Point Default Status Control Register, FPDSCR */
|
||||
|
||||
/*
|
||||
* set the initial value of FPSCR, however we can set it manually to FPSCR
|
||||
* when creating the VFP task, so let it as is at this time.
|
||||
*/
|
||||
|
||||
#define FPDSCR (0xE000EF3C)
|
||||
#define FPDSCR_AHP (1<<26)
|
||||
#define FPDSCR_DN (1<<25)
|
||||
#define FPDSCR_FZ (1<<24)
|
||||
#define FPDSCR_RMODE 0x00C00000
|
||||
#define FPDSCR_RN 0x00000000 /* round to nearest */
|
||||
#define FPDSCR_RP 0x00400000 /* round toward plus infinity */
|
||||
#define FPDSCR_RM 0x00800000 /* round toward minus infinity */
|
||||
#define FPDSCR_RZ 0x00C00000 /* round toward zero */
|
||||
|
||||
/* Media and FP Feature Register 0, MVFR0 & Register 1, MVFR1*/
|
||||
|
||||
/* these read only registers are using to detect feature that supported */
|
||||
|
||||
#define MVFR0 (0xE000EF40)
|
||||
#define MVFR0_SP_MSK (0x000000F0) /* bit 4~7 = 0x2, support sp */
|
||||
#define MVFR0_SP_EN (0x20) /* bit 4~7 = 0x2, support sp */
|
||||
#define MVFR1 (0xE000EF44)
|
||||
|
||||
/* FPSCR (Floating Status and Control Register) bit definitions for VFPv4SP */
|
||||
|
||||
/*
|
||||
* At the time of implementation bits 27, 21-8, and 6-5,
|
||||
* are described as reserved, one must employ
|
||||
* read/modify/write techniques when handling the FPSCR in order
|
||||
* to ensure that these bits are not modified...
|
||||
*/
|
||||
|
||||
#define FPSCR_N_BIT (1<<31) /* less than result */
|
||||
#define FPSCR_Z_BIT (1<<30) /* equal result */
|
||||
#define FPSCR_C_BIT (1<<29) /* equal, greater than, or unordered result */
|
||||
#define FPSCR_V_BIT (1<<28) /* unordered result */
|
||||
|
||||
#define FPSCR_AHP (1<<26)
|
||||
|
||||
#define FPSCR_DN_BIT (1<<25) /* Default NaN mode control */
|
||||
#define FPSCR_DN_MSK FPSCR_DN_BIT
|
||||
#define FPSCR_DN_ENABLE FPSCR_DN_BIT
|
||||
#define FPSCR_DN_DISABLE 0x00000000
|
||||
|
||||
#define FPSCR_FZ_BIT (1<<24) /* flush to zero mode control */
|
||||
#define FPSCR_FZ_MSK FPSCR_FZ_BIT
|
||||
#define FPSCR_FZ_ENABLE FPSCR_FZ_BIT
|
||||
#define FPSCR_FZ_DISABLE 0x00000000
|
||||
|
||||
/* Cumulative Exception Bits */
|
||||
|
||||
#define FPSCR_IDC_BIT (1<<7) /* Input Subnormal */
|
||||
#define FPSCR_IXC_BIT (1<<4) /* Inexact */
|
||||
#define FPSCR_UFC_BIT (1<<3) /* Underflow */
|
||||
#define FPSCR_OFC_BIT (1<<2) /* Overflow */
|
||||
#define FPSCR_DZC_BIT (1<<1) /* Division By Zero */
|
||||
#define FPSCR_IOC_BIT (1<<0) /* Invalid Operation */
|
||||
|
||||
/* Round Mode Control Bits */
|
||||
|
||||
#define FPSCR_RMODES_MSK 0x00C00000 /* round mode */
|
||||
#define FPSCR_RN 0x00000000 /* round to nearest */
|
||||
#define FPSCR_RP 0x00400000 /* round toward plus infinity */
|
||||
#define FPSCR_RM 0x00800000 /* round toward minus infinity */
|
||||
#define FPSCR_RZ 0x00C00000 /* round toward zero */
|
||||
|
||||
#ifdef _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO
|
||||
#define FPSCR_INIT FPSCR_DN_MSK
|
||||
#else /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
|
||||
#define FPSCR_INIT (FPSCR_DN_MSK | FPSCR_FZ_BIT)
|
||||
#endif /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
|
||||
|
||||
#define VFPREG_SET VFP_CONTEXT
|
||||
|
||||
#define _VFP_ALIGN_SIZE 8 /* Not sure if this is needed */
|
||||
|
||||
/* vfpv4 sp only support D16/S32. */
|
||||
|
||||
#define VFP_DGPR_NUM 16 /* 16-double precision general purpose */
|
||||
#define VFP_SGPR_NUM 32 /* 32-single precision general purpose */
|
||||
|
||||
/* FP_CONTEXT structure offsets */
|
||||
|
||||
#define VFP_FPSCR 0x00
|
||||
#define VFP_PAD -
|
||||
#define VFP_GPR 0x08 /* OFFSET(FP_CONTEXT, vfp_gpr[0]) */
|
||||
#define VFP_GPR_OFFSET(n) (VFP_GPR + (n)*4) /* vfp_gpr[n]) */
|
||||
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* standard interface to fp lib. */
|
||||
|
||||
/* vfpv4 sp context is different with standard vfp. */
|
||||
|
||||
typedef struct vfpContext /* VFP Context */
|
||||
{
|
||||
UINT32 fpscr; /* status and control register */
|
||||
UINT32 pad; /* pad to match 8 byte alignment */
|
||||
UINT32 vfp_gpr[VFP_SGPR_NUM]; /* general purpose registers */
|
||||
/* TOTAL */
|
||||
} WRS_PACK_ALIGN(_VFP_ALIGN_SIZE) VFP_CONTEXT;
|
||||
|
||||
/* function declarations */
|
||||
|
||||
IMPORT void vfpArchInit (void);
|
||||
IMPORT void vfpArchTaskCreateInit (VFP_CONTEXT *pDspContext);
|
||||
|
||||
IMPORT void vfpSave (VFP_CONTEXT *);
|
||||
IMPORT void vfpRestore (VFP_CONTEXT *);
|
||||
|
||||
IMPORT STATUS vfpProbe (void);
|
||||
IMPORT STATUS vfpEnable (void);
|
||||
IMPORT STATUS vfpDisable (void);
|
||||
|
||||
IMPORT VFP_CONTEXT * vfpCtxCreate (int);
|
||||
IMPORT STATUS vfpCtxDelete (VFP_CONTEXT *);
|
||||
IMPORT void vfpCtxShow (VFP_CONTEXT *);
|
||||
|
||||
void vfpRegsToCtx (VFPREG_SET *, VFP_CONTEXT *);
|
||||
void vfpCtxToRegs (VFP_CONTEXT *, VFPREG_SET *);
|
||||
|
||||
#ifdef _WRS_HW_VFP_SUPPORT
|
||||
IMPORT int vfpIsEnabled (void);
|
||||
IMPORT int vfpHasException (void);
|
||||
IMPORT STATUS vfpProbeSup (void);
|
||||
IMPORT UINT32 vfpFpSidGet (void);
|
||||
IMPORT UINT32 vfpFpScrGet (void);
|
||||
IMPORT void vfpFpScrSet (UINT32);
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __INCvfpArmLibSph */
|
||||
|
||||
|
||||
@@ -0,0 +1,505 @@
|
||||
/* arm.h - ARM CPU flags etc */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996-2006, 2008-2014 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
17apr14,c_l add the write protection of L2 page table. (VXW6-73478)
|
||||
02l,16mar13,yjw Update for ARMv7M
|
||||
02k,08oct12,jdw Update FAST MATH for ARMARCH7
|
||||
02j,14sep12,j_b fix whitespace issues
|
||||
02i,28jun12,j_b add Cortex-A15 cache support
|
||||
02h,09feb12,jdw Update definitions for __ieee_status(), WIND00332894
|
||||
02g,01feb12,rec WIND00329076 - cleanup assembly macros to be consistent
|
||||
02f,11aug11,jdw Add support for ARMv7 core optimizations
|
||||
02e,23aug11,rec WIND00292261 - transition to common power management API
|
||||
02d,15apr11,jdw Enable cached page tables
|
||||
02c,13jan11,m_h Define _CACHE_ALIGN_SIZE as cacheArchAlignSize for ARMARCH7
|
||||
02b,09jul10,fao add endianness state bit define
|
||||
02a,21may10,m_h Thumb-2 Support
|
||||
01z,02feb10,j_b add _WRS_ARM_HAS_ASID macro, defined for ARMv6+
|
||||
01y,23sep09,j_b add LDREX/STREX support for ARMARCH7
|
||||
01x,06jun09,mdo Don't check IEEE status for FAST_MATH
|
||||
01w,25feb09,j_b merge ARM SMP:
|
||||
11jul07,j_b add ARMMMU_11MPCORE support
|
||||
11jul07,to added ARM_HAS_LDREX_STREX feature macro
|
||||
02jul07,m_h Adding types for MPCore varient
|
||||
01v,27feb09,m_h ARMARCH7 Support
|
||||
01u,12jun08,j_b add Cortex-A MMU and Cortex-A/-R cache support
|
||||
01t,28apr08,m_h Create macro for NOP after LDM^ and STM^
|
||||
01s,13jul06,m_h MPU support
|
||||
01r,25jan06,m_h Manzano support
|
||||
01o,10oct05,scm correct SPR 111664
|
||||
01n,04apr05,jb Adding ARMARCH6 and 1136 support
|
||||
01m,21mar05,mdo Add define for ansiMath testing
|
||||
01l,02mar05,mdo Add prototype for __ieee_status() and definitions for
|
||||
exception flags
|
||||
01k,10aug04,scm remove MPU support...
|
||||
01j,25nov03,sn Avoid gcc 3.3.2 preprocessor token pasting error
|
||||
01i,26aug03,rec remove SYS_PWR_MGMT conditional
|
||||
01h,07jul03,rec revert to non-portable kernel
|
||||
01g,01jul03,rec code review comments
|
||||
01f,28may03,rec Power Management
|
||||
01f,17dec02,jb Adding ARM10 and 926E support
|
||||
01e,15jan02,m_h ARMARCH5 thumb problem
|
||||
01d,05nov01,t_m remove leading underscores via FUNC/VAR macros
|
||||
01c,05nov01,t_m Undo underscores
|
||||
01b,19jul01,ed Fixing to be compatible with Diab compiler.
|
||||
01d,17oct01,t_m Merge in DIAB
|
||||
01c,10oct01,jb Enabling removal of pre-pended underscores for new compilers
|
||||
(Diab/Gnu elf)
|
||||
01b,23jul01,scm change XScale name to conform to coding standards...
|
||||
01a,11dec00,scm replace references to ARMSA2 with XScale
|
||||
01g,16oct00,scm reverse back I & F bits for SA2
|
||||
01f,01sep00,scm add sa2 support...
|
||||
01e,08feb99,jpd added further MMU/CACHE types.
|
||||
01d,20jan99,cdp removed support for old ARM libraries.
|
||||
01c,24aug98,cdp added MMU/cache types, ARM_HAS_MPU/ARM_THUMB, ARMST16/ARMST32.
|
||||
01b,21aug97,cdp added _?_FUNCTION macros and HAS_HALFWORD_
|
||||
01a,08may96,cdp written
|
||||
*/
|
||||
|
||||
#ifndef __INCarmh
|
||||
#define __INCarmh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if (CPU == ARMARCH7M)
|
||||
|
||||
#include "arch/arm/arm-m/arm-m.h"
|
||||
|
||||
#else /* (CPU == ARMARCH7M) */
|
||||
|
||||
|
||||
/* Make sure excArmLib.h also has same settings */
|
||||
|
||||
/* bits in the PSR */
|
||||
|
||||
#define V_BIT (1<<28)
|
||||
#define C_BIT (1<<29)
|
||||
#define Z_BIT (1<<30)
|
||||
#define N_BIT (1<<31)
|
||||
#define E_BIT (1<<9)
|
||||
#define I_BIT (1<<7)
|
||||
#define F_BIT (1<<6)
|
||||
#define T_BIT (1<<5)
|
||||
|
||||
|
||||
/* mode bits */
|
||||
|
||||
#define MODE_SYSTEM32 0x1F
|
||||
#define MODE_UNDEF32 0x1B
|
||||
#define MODE_ABORT32 0x17
|
||||
#define MODE_SVC32 0x13
|
||||
#define MODE_IRQ32 0x12
|
||||
#define MODE_FIQ32 0x11
|
||||
#define MODE_USER32 0x10
|
||||
#define MODE_MONITOR 0x16
|
||||
|
||||
/* masks for getting bits from PSR */
|
||||
|
||||
#ifdef ARM_INTERWORKINGSUPPORT
|
||||
#define MASK_MODE 0x0000003F
|
||||
#else /*ARM_INTERWORKINGSUPPORT*/
|
||||
#define MASK_MODE 0x0000001F
|
||||
#endif /*ARM_INTERWORKINGSUPPORT*/
|
||||
#define MASK_32MODE 0x0000001F
|
||||
#define MASK_SUBMODE 0x0000000F
|
||||
#define MASK_INT 0x000000C0
|
||||
#define MASK_CC 0xF0000000
|
||||
|
||||
|
||||
/* shifts to access bits in the PSR */
|
||||
|
||||
#define INT_MASK_SHIFT 6
|
||||
|
||||
|
||||
/* The coprocessor number of the MMU System Control Processor */
|
||||
|
||||
#define CP_MMU 15
|
||||
|
||||
|
||||
/* ARM MMU types */
|
||||
|
||||
#define ARMMMU_NONE 0
|
||||
#define ARMMMU_710A 1
|
||||
#define ARMMMU_810 2
|
||||
#define ARMMMU_SA110 3
|
||||
#define ARMMMU_940T 4
|
||||
#define ARMMMU_740T 5
|
||||
#define ARMMMU_SA1100 6
|
||||
#define ARMMMU_SA1500 7
|
||||
#define ARMMMU_720T 8
|
||||
#define ARMMMU_920T 9
|
||||
#define ARMMMU_946E 10
|
||||
#define ARMMMU_XSCALE 11
|
||||
#define ARMMMU_926E 12
|
||||
#define ARMMMU_1020E 13
|
||||
#define ARMMMU_1022E 14
|
||||
#define ARMMMU_1136JF 15
|
||||
#define ARMMMU_MANZANO 16
|
||||
#define ARMMMU_CORTEXA8 17
|
||||
#define ARMMMU_11MPCORE 18
|
||||
|
||||
#define ARMMPU_940T ARMMMU_940T
|
||||
#define ARMMPU_740T ARMMMU_740T
|
||||
#define ARMMPU_946E ARMMMU_946E
|
||||
|
||||
/* ARM cache types */
|
||||
|
||||
#define ARMCACHE_NONE 0
|
||||
#define ARMCACHE_710A 1
|
||||
#define ARMCACHE_810 2
|
||||
#define ARMCACHE_SA110 3
|
||||
#define ARMCACHE_940T 4
|
||||
#define ARMCACHE_740T 5
|
||||
#define ARMCACHE_SA1100 6
|
||||
#define ARMCACHE_SA1500 7
|
||||
#define ARMCACHE_720T 8
|
||||
#define ARMCACHE_920T 9
|
||||
#define ARMCACHE_946E 10
|
||||
#define ARMCACHE_XSCALE 11
|
||||
#define ARMCACHE_926E 12
|
||||
#define ARMCACHE_1020E 13
|
||||
#define ARMCACHE_1022E 14
|
||||
#define ARMCACHE_1136JF 15
|
||||
#define ARMCACHE_MANZANO 16
|
||||
#define ARMCACHE_CORTEXA8 17
|
||||
#define ARMCACHE_11MPCORE 18
|
||||
#define ARMCACHE_CORTEXA15 19
|
||||
|
||||
|
||||
/* check CPU/cache/MMU features */
|
||||
|
||||
/* Cache Line sizes */
|
||||
|
||||
#if defined (_WRS_CONFIG_ARMV7_CORE_CTX_A8) || \
|
||||
defined (_WRS_CONFIG_ARMV7_CORE_CTX_A15)
|
||||
|
||||
#define _CPU_CACHE_ALIGN_SIZE 64 /* Cortex-A8 and Cortex-A15 use 64 bytes */
|
||||
|
||||
#else /* _WRS_CONFIG_ARMV7_CORE_CTX_A8 || _WRS_CONFIG_ARMV7_CORE_CTX_A15 */
|
||||
|
||||
/*
|
||||
* Most ARM cores have a cache line size of 32 bytes.
|
||||
*
|
||||
* This can be overridden through use of the global variable
|
||||
* cacheArchAlignSize. See below.
|
||||
*/
|
||||
|
||||
#define _CPU_CACHE_ALIGN_SIZE 32
|
||||
|
||||
#endif /* _WRS_CONFIG_ARMV7_CORE_CTX_A8 || _WRS_CONFIG_ARMV7_CORE_CTX_A15 */
|
||||
|
||||
/*
|
||||
* The way in which _CACHE_ALIGN_SIZE is defined has been changed
|
||||
* somewhat and is no longer strictly related to the CPU type defined,
|
||||
* but is instead related to the cache type selected. Therefore, it would
|
||||
* be better if drivers that need to know the cache line size, use this
|
||||
* variable, rather than the constant. The variable will be initialized
|
||||
* to the appropriate cache-type-dependent value by the variant of the
|
||||
* cache library initialisation code.
|
||||
*/
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
extern int cacheArchAlignSize;
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/*
|
||||
* Cached page tables are supported by ARM v6 and ARM v7 processors by
|
||||
* default. Turn them on here for default builds (e.g. builds not
|
||||
* configured by vxprj / VSBs).
|
||||
*/
|
||||
|
||||
#if (!defined(_WRS_CONFIG_ARM_PRJ_BUILD) && \
|
||||
((CPU == ARMARCH6) || (CPU == ARMARCH7) || (CPU == ARMARCH7_T2)))
|
||||
#define _WRS_CONFIG_ENABLE_CACHED_PAGE_TBL
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Cached page tables are not supported for ARMv6 MPCore BSPs, so
|
||||
* disable this feature here for default & VSB builds
|
||||
*/
|
||||
|
||||
#if ((defined (_WRS_CONFIG_SMP) && (CPU == ARMARCH6)) && \
|
||||
defined (_WRS_CONFIG_ENABLE_CACHED_PAGE_TBL))
|
||||
#undef _WRS_CONFIG_ENABLE_CACHED_PAGE_TBL
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Cached page tables are not supported for ARM v4 and ARM v5 processors, so
|
||||
* disable this feature here for default & VSB builds
|
||||
*/
|
||||
|
||||
#if (((CPU == ARMARCH4) || (CPU == ARMARCH5) || (CPU == XSCALE)) && \
|
||||
defined (_WRS_CONFIG_ENABLE_CACHED_PAGE_TBL))
|
||||
#undef _WRS_CONFIG_ENABLE_CACHED_PAGE_TBL
|
||||
#endif
|
||||
|
||||
#if ((CPU == ARMARCH7) || (CPU == ARMARCH7_T2))
|
||||
|
||||
/*
|
||||
* By default cache alignment for ARMv7 is 32 bytes. This is accomplished by
|
||||
* assigning cacheArchAlignSize as _CPU_CACHE_ALIGN_SIZE where it is declared
|
||||
* in cacheArchVars.c. But some cores can have a cache alignment that is not
|
||||
* 32 bytes. These cores will adjust the global variable cacheAlignSize
|
||||
* during runtime initialization. See cacheAimCortexA8LibInit for an example
|
||||
* of this.
|
||||
*/
|
||||
|
||||
#undef _CACHE_ALIGN_SIZE
|
||||
#define _CACHE_ALIGN_SIZE cacheArchAlignSize
|
||||
|
||||
/* this cpu family supports power management framework */
|
||||
|
||||
#define _WRS_ARCH_HAS_CPU_PWR_MGMT
|
||||
|
||||
#else /* ((CPU == ARMARCH7) || (CPU == ARMARCH7_T2)) */
|
||||
|
||||
/* Cache alignment is 32 bytes */
|
||||
|
||||
#undef _CACHE_ALIGN_SIZE
|
||||
#define _CACHE_ALIGN_SIZE _CPU_CACHE_ALIGN_SIZE
|
||||
|
||||
#endif /* ((CPU == ARMARCH7) || (CPU == ARMARCH7_T2)) */
|
||||
|
||||
#if (CPU == ARMARCH3)
|
||||
#define ARM_HAS_HALFWORD_INSTRUCTIONS FALSE
|
||||
#else
|
||||
#define ARM_HAS_HALFWORD_INSTRUCTIONS TRUE
|
||||
#endif
|
||||
|
||||
#define ARM_HAS_MPU FALSE
|
||||
|
||||
#if defined(ARMMMU) && (ARMMMU == ARMMMU_NONE)
|
||||
#define ARM_HAS_NO_MMU TRUE
|
||||
#else
|
||||
#define ARM_HAS_NO_MMU FALSE
|
||||
#endif
|
||||
|
||||
#if (CPU == ARMARCH4_T) || (CPU == ARMARCH5_T)
|
||||
#define ARM_THUMB TRUE
|
||||
#else
|
||||
#define ARM_THUMB FALSE
|
||||
#endif
|
||||
|
||||
#if (CPU == ARMARCH7_T2)
|
||||
#define ARM_THUMB2 TRUE
|
||||
#else /* (CPU == ARMARCH7_T2) */
|
||||
#define ARM_THUMB2 FALSE
|
||||
#endif /* (CPU == ARMARCH7_T2) */
|
||||
|
||||
#if (ARM_THUMB2)
|
||||
#define PORTABLE
|
||||
#endif /* ARM_THUMB2 */
|
||||
|
||||
/*
|
||||
* For ARMv5 and earlier, STM(2) and LDM(2) instructions
|
||||
* must not be immediately followed by an
|
||||
* instruction that accesses a banked register.
|
||||
* Banked registers are: R8-R14. STM(2) and LDM(2) are
|
||||
* the variations of the OP codes that end with "^"
|
||||
* (load or store registers from a different mode -- user mode)
|
||||
* and do not load the PC (do not branch).
|
||||
*
|
||||
* One possible solution to this (suggested by the
|
||||
* ARM Architecture Reference Manual) is to insert
|
||||
* a NOP between the STM or LDM call and the access
|
||||
* to a banked register.
|
||||
*
|
||||
* Here is an example of where a NOP would be required
|
||||
* because sp is one of the banked registers:
|
||||
*
|
||||
* LDMIA r1, {sp, lr}^
|
||||
* NOP
|
||||
* LDR r1, [sp, #SC_SAVE_USERSR]
|
||||
*
|
||||
* The asm macro ARM_NOP_AFTER_USER_LDM_STM is used for
|
||||
* inserting the NOP only if the version of the architecture
|
||||
* requires it.
|
||||
*/
|
||||
|
||||
|
||||
#if (CPU == ARMARCH4) || (CPU == ARMARCH5) || (CPU == XSCALE)
|
||||
#define ARM_NOP_AFTER_USER_LDM_STM NOP
|
||||
#else
|
||||
#define ARM_NOP_AFTER_USER_LDM_STM
|
||||
#endif
|
||||
|
||||
#if (CPU == ARMARCH6) || (CPU==ARMARCH7) || (CPU==ARMARCH7_T2)
|
||||
#define ARM_HAS_LDREX_STREX TRUE
|
||||
#define _WRS_ARM_HAS_ASID TRUE
|
||||
#else /* (CPU == ARMARCH6) || (CPU==ARMARCH7) || (CPU==ARMARCH7_T2) */
|
||||
#define ARM_HAS_LDREX_STREX FALSE
|
||||
#define _WRS_ARM_HAS_ASID FALSE
|
||||
#endif /* (CPU == ARMARCH6) || (CPU==ARMARCH7) || (CPU==ARMARCH7_T2) */
|
||||
|
||||
/** Power management for XSCALE **/
|
||||
|
||||
#if (CPU==XSCALE)
|
||||
|
||||
/* The coprocessor number of the Power Mode Register */
|
||||
|
||||
#define CP_CCLKCFG 14
|
||||
|
||||
/* OPCODE for idle */
|
||||
|
||||
#define PWRMODE_IDLE 1
|
||||
|
||||
#endif /* Power management for XSCALE */
|
||||
|
||||
/** Power management for ARM **/
|
||||
|
||||
#if (CPU==ARMARCH5) || (CPU==ARMARCH5_T) || (CPU==ARMARCH6) \
|
||||
|| (CPU==ARMARCH7) || (CPU==ARMARCH7_T2)
|
||||
|
||||
/* The coprocessor number of the Power Mode Register */
|
||||
|
||||
#define CP_CORECTL 15
|
||||
|
||||
/* OPCODE for idle */
|
||||
|
||||
#define PWRMODE_IDLE 1
|
||||
|
||||
#endif /* CPU==ARMARCH5 ... ARMARCH7_T2 */
|
||||
|
||||
#if !defined(_WRS_CONFG_FAST_MATH) || (VFPVARIANT != VFPV3)
|
||||
|
||||
/* Define __ieee_status exception flags */
|
||||
#define FE_IEEE_FLUSHZERO (0x01000000)
|
||||
#define FE_IEEE_ROUND_TONEAREST (0x00000000)
|
||||
#define FE_IEEE_ROUND_UPWARD (0x00400000)
|
||||
#define FE_IEEE_ROUND_DOWNWARD (0x00800000)
|
||||
#define FE_IEEE_ROUND_TOWARDZERO (0x00C00000)
|
||||
#define FE_IEEE_ROUND_MASK (0x00C00000)
|
||||
#define FE_IEEE_MASK_INVALID (0x00000100)
|
||||
#define FE_IEEE_MASK_DIVBYZERO (0x00000200)
|
||||
#define FE_IEEE_MASK_OVERFLOW (0x00000400)
|
||||
#define FE_IEEE_MASK_UNDERFLOW (0x00000800)
|
||||
#define FE_IEEE_MASK_INEXACT (0x00001000)
|
||||
#define FE_IEEE_MASK_ALL_EXCEPT (0x00001F00)
|
||||
#define FE_IEEE_INVALID (0x00000001)
|
||||
#define FE_IEEE_DIVBYZERO (0x00000002)
|
||||
#define FE_IEEE_OVERFLOW (0x00000004)
|
||||
#define FE_IEEE_UNDERFLOW (0x00000008)
|
||||
#define FE_IEEE_INEXACT (0x00000010)
|
||||
#define FE_IEEE_ALL_EXCEPT (0x0000001F)
|
||||
|
||||
/* Define which of the IEEE status bits are reserved */
|
||||
#define IEEE_RESERVED_MASK (0xF63FE0E0)
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
extern unsigned int __ieee_status (unsigned int mask, unsigned int flags);
|
||||
#endif
|
||||
|
||||
/* Define for ansiMath Testing */
|
||||
#define _WRS_ARM_IEEE_STATUS
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The default for ARMARCH7 and ARMARCH7_T2 is to use _WRS_CONFIG_FAST_MATH to
|
||||
* optimize builds created with VFP enabled. The flag to enable this behavior
|
||||
* is from the make fragments for a CPU/TOOL pair.
|
||||
*
|
||||
* Builds that use a SW FP tool chain should not use FAST MATH to get best
|
||||
* performance.
|
||||
*
|
||||
* Override VSB options here because VSB configuration does not detect the
|
||||
* tool chain / floating point configuration properly.
|
||||
*/
|
||||
|
||||
#if defined(ARM_USE_VFP)
|
||||
/* Vector floating point builds use FAST MATH */
|
||||
#undef _WRS_CONFIG_FAST_MATH
|
||||
#define _WRS_CONFIG_FAST_MATH 1
|
||||
#else
|
||||
/* Software floating point build does NOT use FAST MATH */
|
||||
#undef _WRS_CONFIG_FAST_MATH
|
||||
#endif /* defined(USE_ARM_FP) ... */
|
||||
|
||||
/*
|
||||
* The default for ARMARCH7 and ARMARCH7_T2 is to use _WRS_CONFIG_FAST_MATH to
|
||||
* optimize builds created with VFP enabled. The flag to enable this behavior
|
||||
* is from the make fragments for a CPU/TOOL pair.
|
||||
*
|
||||
* Builds that use a SW FP tool chain should not use FAST MATH to get best
|
||||
* performance.
|
||||
*
|
||||
* Override VSB options here because VSB configuration does not detect the
|
||||
* tool chain / floating point configuration properly.
|
||||
*/
|
||||
|
||||
#if defined(ARM_USE_VFP)
|
||||
/* Vector floating point builds use FAST MATH */
|
||||
#undef _WRS_CONFIG_FAST_MATH
|
||||
#define _WRS_CONFIG_FAST_MATH 1
|
||||
#else
|
||||
/* Software floating point build does NOT use FAST MATH */
|
||||
#undef _WRS_CONFIG_FAST_MATH
|
||||
#endif /* defined(USE_ARM_FP) ... */
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* File below inclusion must be after ARCH specific defines such as ARM_THUMB2.
|
||||
*/
|
||||
|
||||
#include <asm.h>
|
||||
|
||||
|
||||
/** I80310 (coyanosa) specific helper macros **/
|
||||
#if ((CPU==XSCALE) || (CPU==ARMSA110))
|
||||
/*
|
||||
* The following macro should be used when software needs to be assured that a
|
||||
* CP15 update has taken effect. It may only used while in a privileged mode,
|
||||
* because it accesses CP15. Ref. Coyanosa EAS 2.3.4 Additions to CP15
|
||||
* functionality
|
||||
*/
|
||||
#define CPWAIT(a) \
|
||||
mrc p15, 0, a, c2, c0, 0 /* arbitrary read of CP15 */ ;\
|
||||
mov a, a /* wait for it */ ;\
|
||||
sub pc, pc, IMMED4 /* branch to next instruction */ ;
|
||||
#define IMMED4 #4
|
||||
|
||||
/*
|
||||
* at this point, any previous CP15 writes are guaranteed
|
||||
* to have taken effect
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* The following macro should be used when software needs to be assure that
|
||||
* BCU has finish all outstanding operations.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CAUTION: This macro should be used only from the cacheable region, or it may
|
||||
* keep the BCU eternally busy fetching the code.
|
||||
*/
|
||||
|
||||
#define BCUWAIT(a) \
|
||||
mrc p13, 0, a, c0, c1, 0; /* Read BCUCTL,updates conditon code */ \
|
||||
submi pc, pc, IMMED12 ; /* If BCU busy (bit 31 set) try again */
|
||||
#define IMMED12 #12
|
||||
|
||||
#endif /* if CPU=XSCALE */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* (CPU == ARMARCH7M) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCarmh */
|
||||
@@ -0,0 +1,201 @@
|
||||
/* asmArm.h - ARM assembler definitions header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996, 2004, 2010, 2012, 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01g,20feb13,yjw add macros to support Thumb-2
|
||||
01f,16oct12,jdw Add SPSR set macro (WIND00259770)
|
||||
01e,18jan12,rec WIND00329076 - add FUNC_END, cleanup macros to be consistent
|
||||
with other arch defines. Remove THUMB support.
|
||||
01d,09jan12,jdw Add macro definitions for pld instructions
|
||||
01c,21may10,m_h Thumb-2 Support
|
||||
01b,06jul04,md added function definition macros
|
||||
01a,09may96,cdp created
|
||||
*/
|
||||
|
||||
#ifndef __INCasmArmh
|
||||
#define __INCasmArmh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
|
||||
#ifdef __GNUC__
|
||||
.syntax unified
|
||||
#endif
|
||||
|
||||
/* Build for Gnu elf or Diab compiler */
|
||||
/* useful, assembly-language macros */
|
||||
#define FUNC(a) a
|
||||
#define VAR(name) name
|
||||
|
||||
/*
|
||||
* These macros are used to declare assembly language symbols that need
|
||||
* to be typed properly(func or data) to be visible to the OMF tool.
|
||||
* So that the build tool could mark them as an entry point to be linked
|
||||
* correctly.
|
||||
*/
|
||||
|
||||
#ifdef __DCC__
|
||||
#if ARM_THUMB2
|
||||
#define GTEXT(sym) FUNC(sym) ; .type FUNC(sym),@tfunc
|
||||
#else /* ARM_THUMB2 */
|
||||
#define GTEXT(sym) FUNC(sym) ; .type FUNC(sym),@function
|
||||
#endif /* ARM_THUMB2 */
|
||||
#define GDATA(sym) VAR(sym) ; .type VAR(sym),@object
|
||||
#elif (defined __GNUC__) /* GNU macros */
|
||||
#define GTEXT(sym) FUNC(sym) ; .type FUNC(sym),STT_FUNC
|
||||
#define GDATA(sym) VAR(sym) ; .type VAR(sym),STT_OBJECT
|
||||
#else /* neither __DCC__ nor __GNUC__ */
|
||||
#error "error!!! unsupported compiler!!!"
|
||||
#endif /* __DCC__ */
|
||||
|
||||
/* abstract assembler idiosyncrasies */
|
||||
|
||||
#define FUNC_LABEL(func) func:
|
||||
#define VAR_LABEL(name) name:
|
||||
|
||||
#define FUNC_EXPORT(func) .globl GTEXT(func)
|
||||
#define DATA_EXPORT(var) .globl GDATA(var)
|
||||
#define FUNC_IMPORT(func) .extern FUNC(func)
|
||||
#define DATA_IMPORT(var) .extern VAR(var)
|
||||
#define FUNC_END(func) .size FUNC(func), . - FUNC(func)
|
||||
|
||||
|
||||
#if ((!defined __GNUC__) && (!defined __DCC__))
|
||||
#error "error!!! unsupported assembler!!!"
|
||||
#endif /* (defined __GNUC__) && (!defined __DCC__) */
|
||||
|
||||
/*
|
||||
* The DCC assembler has problems with spaces before the function label.
|
||||
* To avoid assembler parse problems, the FUNC_LABEL macros below are
|
||||
* not indented.
|
||||
*/
|
||||
|
||||
#if ARM_THUMB2
|
||||
#if (defined __GNUC__)
|
||||
#define FUNC_BEGIN(func) \
|
||||
.thumb;\
|
||||
.thumb_func;\
|
||||
.balign 4;\
|
||||
FUNC_LABEL(func)
|
||||
#else /* !__GNUC__ */
|
||||
#define FUNC_BEGIN(func) \
|
||||
.thumb;\
|
||||
.balign 4;\
|
||||
FUNC_LABEL(func)
|
||||
#endif /* __GNUC__ */
|
||||
#else /* !ARM_THUMB2 */
|
||||
#define FUNC_BEGIN(func) \
|
||||
.code 32;\
|
||||
.balign 4;\
|
||||
FUNC_LABEL(func)
|
||||
#endif /* ARM_THUMB2 */
|
||||
|
||||
/*
|
||||
* The following two macros are deprecated. Definitions are provided for
|
||||
* backward compatibility.
|
||||
*/
|
||||
|
||||
#define _ARM_FUNCTION_CALLED_FROM_C FUNC_BEGIN
|
||||
#define _ARM_FUNCTION FUNC_BEGIN
|
||||
|
||||
/* Define macros to use the PLD instruction on ARM v7 processors */
|
||||
#if (CPU == ARMARCH7 || CPU == ARMARCH7_T2)
|
||||
#define PLD(...) pld __VA_ARGS__
|
||||
#else
|
||||
/* if not ARM v7, do nothing */
|
||||
#define PLD(...)
|
||||
#endif
|
||||
|
||||
#if (CPU == ARMARCH7M)
|
||||
/*
|
||||
* Macro to perform a 32-bit MOV operation, using the ARMv7-M encoding of the
|
||||
* MOV and MOVT instructions to copy the lower and upper 16-bits of a 32-bit
|
||||
* constant to a register.
|
||||
*/
|
||||
|
||||
#define _ARM_M_MOV32(reg, val) \
|
||||
LDR reg, =val
|
||||
|
||||
/* External interrupt toggle */
|
||||
|
||||
#define INT_LOCK \
|
||||
PUSH {r0}; \
|
||||
MOV r0, #0x10; \
|
||||
MSR basepri, r0; \
|
||||
POP {r0}
|
||||
|
||||
#define INT_UNLOCK \
|
||||
PUSH {r0}; \
|
||||
MOV r0, #0x00; \
|
||||
MSR basepri, r0; \
|
||||
POP {r0}
|
||||
|
||||
#endif /* CPU == ARMARCH7M */
|
||||
|
||||
#define TEMP_STACK_ADR 0x20000800
|
||||
|
||||
/*
|
||||
* The SPSR has changed and additional bits have been added as newer ARM
|
||||
* architecture versions have been released. The new bit definitions are
|
||||
* marked as RAZ/SBZP in older architecture revisions and shouldn't be
|
||||
* modified. Newer versions of the Diab compiler have changed the behavior of
|
||||
* the 'MSR spsr, <reg>' operation and no longer assumes modification of only
|
||||
* spsr_cf fields when specific mask fields are not specified. GCC translates
|
||||
* 'MSR spsr, <reg>' to only modify spsr_cf fields by default, if specific
|
||||
* fields are not specified. See the ARM Architecture Reference Manual for
|
||||
* definitions of the SPSR fields and MSR instruction behavior.
|
||||
*
|
||||
* The _ARM_SPSR_SET() macro abstracts arch and compiler issues from common
|
||||
* code.
|
||||
*/
|
||||
#if (CPU != ARMARCH7M)
|
||||
#if ((_VX_CPU == _VX_ARMARCH7) || (_VX_CPU == _VX_ARMARCH7_T2))
|
||||
|
||||
/*
|
||||
* For ARMv7 (ARM & Thumb2) SPSR <23:20> are RAZ/SBZP, all others are
|
||||
* defined... Write all bits.
|
||||
*/
|
||||
|
||||
#define _ARM_SPSR_SET(reg) \
|
||||
MSR spsr_cxsf, reg
|
||||
|
||||
#else /* ((_VX_CPU == _VX_ARMARCH7) || (_VX_CPU == _VX_ARMARCH7_T2)) */
|
||||
|
||||
/*
|
||||
* For ARMv4, ARMv5, & ARMv6 architectures only the 'c' (bits <7:0>) and 'f'
|
||||
* (bits <31:24>) fields are restored in order to remain consistent with
|
||||
* earlier versions of VxWorks and older Diab compiler revisions.
|
||||
*
|
||||
* NOTES:
|
||||
* 1) The IMX31 may crash if reserved SPSR bits are modified,
|
||||
* see WIND00253307 for details
|
||||
* 2) For ARMARCH6 the GE[3:0] bits (SPSR <19:16>) are not preserved
|
||||
* because VxWorks does not support SIMD instructions
|
||||
*/
|
||||
|
||||
#define _ARM_SPSR_SET(reg) \
|
||||
MSR spsr_cf, reg
|
||||
|
||||
#endif /* ((_VX_CPU == _VX_ARMARCH7) || (_VX_CPU == _VX_ARMARCH7_T2)) */
|
||||
|
||||
#endif /* CPU != ARMARCH7M */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCasmArmh */
|
||||
@@ -0,0 +1,71 @@
|
||||
/* cacheArm1136jfLib.h - ARM 1136JF cache library header file */
|
||||
|
||||
/* Copyright 2005, 2010 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,29apr10,pad Moved extern C statement after include statements.
|
||||
01b,18apr05,jb Fix for SPR 108034
|
||||
01a,07dec04,jb created
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheArm1136jfLibh
|
||||
#define __INCcacheArm1136jfLibh
|
||||
|
||||
/*
|
||||
* Include ARCH6 common defines.
|
||||
*/
|
||||
|
||||
#include "arch/arm/cacheArmArch6.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some cache designs (e.g. Harvard) have D-cache either fully or
|
||||
* partially not coherent with I-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NOT_COHERENT TRUE
|
||||
|
||||
/*
|
||||
* This is a writethrough cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_WRITETHROUGH TRUE
|
||||
|
||||
/*
|
||||
* Does not have a mini-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_MINICACHE FALSE
|
||||
|
||||
/*
|
||||
* Do not need an Instruction Memory Barrier
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NEEDS_IMB TRUE
|
||||
|
||||
/*
|
||||
* Most of the cache designs are virtually addressed, but some newer
|
||||
* ones have physically addressed caches. Note that this is the method of
|
||||
* addressing, not whether the cache has physical address tags within
|
||||
* it.
|
||||
*/
|
||||
|
||||
#define ARMCACHE_IS_PHYSICALLY_ADDRESSED TRUE
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void cacheArm1136jfLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheArm1136jfLibh */
|
||||
@@ -0,0 +1,89 @@
|
||||
/* cacheArm11MPCoreLib.h - ARM 11 MPCore cache library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,29apr10,pad Moved extern C statement after include statements.
|
||||
01a,10jul07,m_h created
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheArm11MPCoreLibh
|
||||
#define __INCcacheArm11MPCoreLibh
|
||||
|
||||
/*
|
||||
* Include ARCH6 common defines.
|
||||
*/
|
||||
|
||||
#include "arch/arm/cacheArmArch6.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some cache designs (e.g. Harvard) have D-cache either fully or
|
||||
* partially not coherent with I-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NOT_COHERENT TRUE
|
||||
|
||||
/*
|
||||
* This is a writethrough cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_WRITETHROUGH TRUE
|
||||
|
||||
/*
|
||||
* Does not have a mini-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_MINICACHE FALSE
|
||||
|
||||
/*
|
||||
* Do not need an Instruction Memory Barrier
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NEEDS_IMB TRUE
|
||||
|
||||
/*
|
||||
* Most of the cache designs are virtually addressed, but some newer
|
||||
* ones have physically addressed caches. Note that this is the method of
|
||||
* addressing, not whether the cache has physical address tags within
|
||||
* it.
|
||||
*/
|
||||
|
||||
#define ARMCACHE_IS_PHYSICALLY_ADDRESSED TRUE
|
||||
|
||||
/* Offsets from PERIPHBASE into MPCore Private Memory Region */
|
||||
|
||||
#define MPCORE_PMR_SNU_CTRL_OFFSET (0x00)
|
||||
#define MPCORE_PMR_SNU_CONFIG_OFFSET (0x04)
|
||||
#define MPCORE_PMR_CPU_STATUS_OFFSET (0x08)
|
||||
#define MPCORE_PMR_INVALIDATE_ALL_OFFSET (0x0C)
|
||||
|
||||
/* Snoop Control Unit -- control register masks */
|
||||
|
||||
#define MPCORE_PMR_SNU_CTRL_EN (0x00000001)
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT UINT32 arm11MPCorePeriphBaseAddr;
|
||||
|
||||
IMPORT void cacheArm11MPCoreLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheArm11MPCoreLibh */
|
||||
@@ -0,0 +1,67 @@
|
||||
/* cacheArm920tLib.h - ARM 920T cache library header file */
|
||||
|
||||
/* Copyright 1998-2005 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01c,09dec04,jb Further Palify ARM Aim cache
|
||||
01b,11dec03,scm flushing out aim...
|
||||
01a,04feb99,jpd created
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheArm920tLibh
|
||||
#define __INCcacheArm920tLibh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define D_CACHE_SIZE (16*1024) /* 16 kbytes DCache */
|
||||
#define I_CACHE_SIZE (16*1024) /* 16 kbytes ICache */
|
||||
|
||||
/*
|
||||
* Some cache designs (e.g. Harvard) have D-cache either fully or
|
||||
* partially not coherent with I-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NOT_COHERENT TRUE
|
||||
|
||||
/*
|
||||
* This is a writethrough cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_WRITETHROUGH TRUE
|
||||
|
||||
/*
|
||||
* Does not have a mini-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_MINICACHE FALSE
|
||||
|
||||
/*
|
||||
* Do not need an Instruction Memory Barrier
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NEEDS_IMB FALSE
|
||||
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void cacheArm920tLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
|
||||
/* definitions to allow for non-cacheAiIM direct calls */
|
||||
|
||||
#define cacheArm920tDClearDisable cacheAim920tDClearDisable
|
||||
#define cacheArm920tIClearDisable cacheAim920tIClearDisable
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheArm920tLibh */
|
||||
@@ -0,0 +1,58 @@
|
||||
/* cacheArm926eLib.h - ARM 926E cache library header file */
|
||||
|
||||
/* Copyright 2002-2005 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01c,07dec04,jb Further Palify ARM Aim cache
|
||||
01b,11dec03,scm flushing out aim...
|
||||
01a,09dec02,jpd created, based on cacheArm946eLib.h
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheArm926eLibh
|
||||
#define __INCcacheArm926eLibh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some cache designs (e.g. Harvard) have D-cache either fully or
|
||||
* partially not coherent with I-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NOT_COHERENT TRUE
|
||||
|
||||
/*
|
||||
* This is a writethrough cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_WRITETHROUGH TRUE
|
||||
|
||||
/*
|
||||
* Does not have a mini-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_MINICACHE FALSE
|
||||
|
||||
/*
|
||||
* Do not need an Instruction Memory Barrier
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NEEDS_IMB FALSE
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void cacheArm926eLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheArm926eLibh */
|
||||
@@ -0,0 +1,89 @@
|
||||
/* cacheArm940tLib.h - ARM 940T cache library header file */
|
||||
|
||||
/* Copyright 1998-2005 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,27jul06,m_h vxWorks 6.x Support
|
||||
01c,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01b,11dec03,scm flushing out aim...
|
||||
01a,24nov98,jpd created
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheArm940tLibh
|
||||
#define __INCcacheArm940tLibh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define D_CACHE_SIZE (4*1024) /* 4 kbytes DCache */
|
||||
|
||||
/*
|
||||
* Some cache designs (e.g. Harvard) have D-cache either fully or
|
||||
* partially not coherent with I-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NOT_COHERENT TRUE
|
||||
|
||||
/*
|
||||
* This is a writethrough cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_WRITETHROUGH TRUE
|
||||
|
||||
/*
|
||||
* Does not have a mini-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_MINICACHE FALSE
|
||||
|
||||
/*
|
||||
* Do not need an Instruction Memory Barrier
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NEEDS_IMB FALSE
|
||||
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void cacheArm940tLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
|
||||
#if 0
|
||||
|
||||
/* if true, not building with cacheAIM support... */
|
||||
|
||||
/* The following prototypes are pre-cacheAIM support */
|
||||
|
||||
IMPORT void cacheArm940tDClearDisable (void);
|
||||
IMPORT void cacheArm940tDFlush (void * addr);
|
||||
IMPORT void cacheArm940tDFlushAll (void);
|
||||
IMPORT void cacheArm940tDInvalidateAll (void);
|
||||
IMPORT void cacheArm940tIInvalidateAll (void);
|
||||
IMPORT void cacheArm940tIInvalidate (void * addr);
|
||||
IMPORT void cacheArm940tDClearAll (void);
|
||||
IMPORT void cacheArm940tDClear (void * addr);
|
||||
IMPORT void cacheArm940tIClearDisable (void);
|
||||
IMPORT void cacheArm940tArchPipeFlush (void);
|
||||
|
||||
#else
|
||||
|
||||
/* else, cacheAIM support... */
|
||||
|
||||
/* definitions to allow for non-cacheAiIM direct calls */
|
||||
|
||||
#define cacheArm940tDClearDisable cacheAim940tDClearDisable
|
||||
#define cacheArm940tIClearDisable cacheAim940tIClearDisable
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheArm940tLibh */
|
||||
@@ -0,0 +1,71 @@
|
||||
/* cacheArm946eLib.h - ARM 946E cache library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000-2006 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,16jun06,m_h non-cacheAIM direct calls
|
||||
01d,22may06,m_h Palify
|
||||
01c,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01b,11dec03,scm flushing out aim...
|
||||
01a,20jul00,jpd created, based on cacheArm940tLib.h
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheArm946eLibh
|
||||
#define __INCcacheArm946eLibh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some cache designs (e.g. Harvard) have D-cache either fully or
|
||||
* partially not coherent with I-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NOT_COHERENT TRUE
|
||||
|
||||
/*
|
||||
* This is a writethrough cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_WRITETHROUGH TRUE
|
||||
|
||||
/*
|
||||
* Does not have a mini-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_MINICACHE FALSE
|
||||
|
||||
/*
|
||||
* Do not need an Instruction Memory Barrier
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NEEDS_IMB FALSE
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void cacheArm946eLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
|
||||
/* definitions to allow for non-cacheAIM direct calls */
|
||||
|
||||
#define cacheArm946eDClearDisable cacheAim946eDClearDisable
|
||||
|
||||
IMPORT void cacheArm946eDClearDisable (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheArm946eLibh */
|
||||
@@ -0,0 +1,109 @@
|
||||
/* cacheArmArch6.h - ARM ARCH6 cache library header file */
|
||||
|
||||
/* Copyright 2004-2005, 2009, 2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,30sep11,cwl define functions for cache enable/disable. (WIND00284079)
|
||||
01d,18feb11,my_ Declare new functions which support L2 cache.
|
||||
01c,18sep09,j_b add core-specific function ptr for DClearDisable operation
|
||||
01b,20apr05,jb Fix for SPR 108034
|
||||
01a,07dec04,jb created
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheArmArch6h
|
||||
#define __INCcacheArmArch6h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* Common definitions for Arm Arch6 Cache support
|
||||
*/
|
||||
|
||||
extern STATUS cacheAimArch6IEnable (void);
|
||||
extern STATUS cacheAimArch6DEnable (void);
|
||||
|
||||
extern STATUS cacheAimArch6IDisable (void);
|
||||
extern STATUS cacheAimArch6DDisable (void);
|
||||
|
||||
extern STATUS cacheAimArch6IProbe (void);
|
||||
extern STATUS cacheAimArch6DProbe (void);
|
||||
|
||||
extern BOOL cacheAimArch6IIsOn (void);
|
||||
extern BOOL cacheAimArch6DIsOn (void);
|
||||
|
||||
extern STATUS cacheAimArch6TextUpdate (void * start, UINT32 count, UINT32 IcacheLineSize, UINT32 DcacheLineSize);
|
||||
|
||||
extern void * cacheAimArch6DmaMalloc (size_t bytes);
|
||||
extern STATUS cacheAimArch6DmaFree (void * pBuf);
|
||||
|
||||
extern BOOL cacheAimArch6MmuIsOn (void);
|
||||
|
||||
extern STATUS cacheAimArch6DInvalidate (void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheAimArch6DInvalidateAll (void);
|
||||
|
||||
extern STATUS cacheAimArch6IInvalidate (void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheAimArch6IInvalidateAll (void);
|
||||
|
||||
extern STATUS cacheAimArch6DFlush (void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheAimArch6DFlushAll (void);
|
||||
|
||||
extern STATUS cacheAimArch6DClear (void * start, void * end, UINT32 step);
|
||||
|
||||
extern STATUS cacheAimArch6PipeFlush (void);
|
||||
|
||||
extern void cacheAimArch6IMB (void);
|
||||
|
||||
extern void cacheAimArch6IClearDisable (void);
|
||||
extern void cacheAimArch6DClearDisableWithVerify (void);
|
||||
extern void cacheAimArch6DClearDisableNoVerify (void);
|
||||
|
||||
extern UINT32 cacheAimArch6Identify (void);
|
||||
|
||||
extern FUNCPTR sysCacheLibInit;
|
||||
extern UINT32 cacheArchState;
|
||||
|
||||
extern STATUS cacheArchIInvalidate(void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheArchIInvalidateAll(void);
|
||||
extern STATUS cacheArchDFlush(void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheArchDFlushAll(void);
|
||||
extern STATUS cacheArchDInvalidate(void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheArchDInvalidateAll(void);
|
||||
extern STATUS cacheArchDClear(void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheArchDClearAll (void);
|
||||
|
||||
/*
|
||||
* Core-specific function pointer for D-cache ClearDisable operation.
|
||||
* These must be initialized by the cacheAim<core>LibInit() routine.
|
||||
*/
|
||||
|
||||
extern VOIDFUNCPTR _func_cacheAimArch6DClearDisable;
|
||||
|
||||
extern void (*_pSysL2CacheEnable)(CACHE_TYPE cacheType);
|
||||
extern void (*_pSysL2CacheDisable)(CACHE_TYPE cacheType);
|
||||
extern void (*_pSysL2CacheInvFunc)(CACHE_TYPE cacheType, void * start, void * end);
|
||||
extern void (*_pSysL2CacheFlush)(CACHE_TYPE cacheType, void * start, void * end);
|
||||
extern void (*_pSysL2CacheClear)(CACHE_TYPE cacheType, void * start, void * end);
|
||||
|
||||
extern void cacheArchL2CacheEnable(void);
|
||||
extern void cacheArchL2CacheDisable(void);
|
||||
|
||||
extern BOOL cacheArchL2CacheIsOn(void);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheArmArch6h */
|
||||
@@ -0,0 +1,298 @@
|
||||
/* cacheArmArch7.h - ARM ARCH7 cache library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008, 2010, 2012, 2014 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
06jan14,c_l Improve cache operation. (VXW6-27040)
|
||||
01h,09nov12,j_b remove unnecessary L1 data cache operation macro
|
||||
01g,04oct12,j_b add macro to operate only on entire L1 D-cache
|
||||
01f,21sep12,j_b Add DSB to end of _CORTEX_AR_ENTIRE_DATA_CACHE_OP
|
||||
01e,10sep12,m_h L2 cachePipeFlush (WIND00240234)
|
||||
01d,02jun10,m_h Thumb-2 Support
|
||||
01c,19may10,z_l Declare new functions which support L2 cache.
|
||||
01b,01aug08,j_b fix _CORTEX_AR_ENTIRE_DATA_CACHE_OP labels
|
||||
01a,11jun08,j_b Created from cacheArmArch6.h, rev 01b
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheArmArch7h
|
||||
#define __INCcacheArmArch7h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* Common definitions for Arm Arch7 Cache support
|
||||
*/
|
||||
|
||||
/* cache levels: 7 possible, indexed starting from 0 */
|
||||
|
||||
#define ARMV7_CACHE_LVL1 0
|
||||
#define ARMV7_CACHE_LVL2 1
|
||||
#define ARMV7_CACHE_LVL3 2
|
||||
#define ARMV7_CACHE_LVL4 3
|
||||
#define ARMV7_CACHE_LVL5 4
|
||||
#define ARMV7_CACHE_LVL6 5
|
||||
#define ARMV7_CACHE_LVL7 6
|
||||
|
||||
/* cache types from Cache Level ID register (CLIDR) */
|
||||
|
||||
#define ARMV7_CLID_ICACHE_TYPE 0x1 /* instruction cache */
|
||||
#define ARMV7_CLID_DCACHE_TYPE 0x2 /* data cache */
|
||||
#define ARMV7_CLID_UCACHE_TYPE 0x4 /* unified cache */
|
||||
|
||||
/* cache types for Cache Size Selection register (CSSEL) */
|
||||
|
||||
#define ARMV7_CSSEL_ICACHE_TYPE 0x1 /* select instruction cache */
|
||||
#define ARMV7_CSSEL_DCACHE_TYPE 0x0 /* select data or unified cache */
|
||||
|
||||
/* cache size info from Cache Size ID register (CCSIDR) */
|
||||
|
||||
#define ARMV7_CCSID_LINESIZE_MSK 0x7 /* line size bit mask */
|
||||
#define ARMV7_CCSID_WAYNUM_MSK 0x1FF8 /* associativity bit mask */
|
||||
#define ARMV7_CCSID_SETNUM_MSK 0xFFFE000 /* set number bit mask */
|
||||
#define ARMV7_CCSID_MODE_MSK 0xF0000000 /* mode bit mask */
|
||||
|
||||
#define ARMV7_CCSID_WAYNUM_SHFT 3 /* associativity field shift */
|
||||
#define ARMV7_CCSID_SETNUM_SHFT 13 /* set number field shift */
|
||||
|
||||
#define ARMV7_CCSID_MODE_WT 0x80000000 /* write-through mode */
|
||||
#define ARMV7_CCSID_MODE_WB 0x40000000 /* write-back mode */
|
||||
#define ARMV7_CCSID_MODE_RA 0x20000000 /* read-allocate mode */
|
||||
#define ARMV7_CCSID_MODE_WA 0x10000000 /* write-allocate mode */
|
||||
|
||||
/*
|
||||
* Common routines for Arm Arch7 Cache support
|
||||
*
|
||||
* Note that many of the Arch 6 routines are still valid for Arch 7 and
|
||||
* have been brought forward.
|
||||
*/
|
||||
|
||||
extern STATUS cacheAimArch7IEnable (void);
|
||||
extern STATUS cacheAimArch7DEnable (void);
|
||||
|
||||
extern STATUS cacheAimArch7IDisable (void);
|
||||
extern STATUS cacheAimArch7DDisable (void);
|
||||
|
||||
extern STATUS cacheAimArch7IProbe (void);
|
||||
extern STATUS cacheAimArch7DProbe (void);
|
||||
|
||||
extern BOOL cacheAimArch7IIsOn (void);
|
||||
extern BOOL cacheAimArch7DIsOn (void);
|
||||
|
||||
extern STATUS cacheAimArch7TextUpdate (void * start,
|
||||
UINT32 count,
|
||||
UINT32 IcacheLineSize,
|
||||
UINT32 DcacheLineSize);
|
||||
|
||||
extern void * cacheAimArch7DmaMalloc (size_t bytes);
|
||||
extern STATUS cacheAimArch7DmaFree (void * pBuf);
|
||||
|
||||
extern BOOL cacheAimArch7MmuIsOn (void);
|
||||
|
||||
extern STATUS cacheAimArch6DInvalidate (void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheAimArch7DInvalidateAll (void);
|
||||
|
||||
extern STATUS cacheAimArch6IInvalidate (void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheAimArch6IInvalidateAll (void);
|
||||
|
||||
extern STATUS cacheAimArch6DFlush (void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheAimArch7DFlushAll (void);
|
||||
extern STATUS cacheAimArch7DFlushPoU (void * start, void * end, UINT32 step);
|
||||
|
||||
extern STATUS cacheAimArch6DClear (void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheAimArch7DClearAll (void);
|
||||
|
||||
extern STATUS cacheAimArch6PipeFlush (void);
|
||||
|
||||
extern void cacheAimArch7IMB (void);
|
||||
|
||||
extern void cacheAimArch6IClearDisable (void);
|
||||
|
||||
extern UINT32 cacheAimArch7Identify (UINT32 level);
|
||||
extern UINT32 cacheAimArch7SizeInfoGet (UINT32 level, UINT32 type);
|
||||
|
||||
extern STATUS cacheArchIInvalidate(void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheArchIInvalidateAll(void);
|
||||
extern STATUS cacheArchDFlush(void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheArchDFlushAll(void);
|
||||
extern STATUS cacheArchDInvalidate(void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheArchDInvalidateAll(void);
|
||||
extern STATUS cacheArchDClear(void * start, void * end, UINT32 step);
|
||||
extern STATUS cacheArchDClearAll (void);
|
||||
extern STATUS cacheArchPipeFlush (void);
|
||||
|
||||
extern size_t cacheArchLocSizeGet (void);
|
||||
extern size_t cacheArchLouSizeGet (void);
|
||||
|
||||
extern FUNCPTR sysCacheLibInit;
|
||||
extern UINT32 cacheArchState;
|
||||
|
||||
/*
|
||||
* Core-specific function pointers for ARMv7 multilevel cache handling.
|
||||
* These must be initialized by the cacheAim<core>LibInit() routine.
|
||||
*/
|
||||
|
||||
extern VOIDFUNCPTR _func_cacheAimArch7IClearDisable;
|
||||
extern VOIDFUNCPTR _func_cacheAimArch7DClearDisable;
|
||||
|
||||
extern void (*_pSysL2CacheEnable)(CACHE_TYPE cacheType);
|
||||
extern void (*_pSysL2CacheDisable)(CACHE_TYPE cacheType);
|
||||
extern void (*_pSysL2CacheInvFunc)(CACHE_TYPE cacheType, void * start, void * end);
|
||||
extern void (*_pSysL2CacheFlush)(CACHE_TYPE cacheType, void * start, void * end);
|
||||
extern void (*_pSysL2CacheClear)(CACHE_TYPE cacheType, void * start, void * end);
|
||||
|
||||
extern void cacheArchL2CacheEnable(void);
|
||||
extern void cacheArchL2CacheDisable(void);
|
||||
|
||||
extern BOOL cacheArchL2CacheIsOn(void);
|
||||
|
||||
#else /* _ASMLANGUAGE */
|
||||
|
||||
/*
|
||||
* Using "#" in the middle of a complex #define generates garbage
|
||||
* passed to the assembler which results in a syntax error. ARM_IMM is
|
||||
* used by this file in order to tell the assembler to use an immediate
|
||||
* value.
|
||||
*/
|
||||
|
||||
#define ARM_IMM #
|
||||
|
||||
#define ARM_LOC_MASK #0x7000000 /* level of coherency mask of CLIDR */
|
||||
|
||||
/*
|
||||
* Common code for cache operations on entire data/unified caches,
|
||||
* performed by set/way to the point of coherency (PoC).
|
||||
* This code is based on 'Example code for cache maintenance operations'
|
||||
* provided in "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
|
||||
* (ARM DDI 0406)" .
|
||||
*
|
||||
* Registers used: For ARM ISA, r0-r8, though r4-r8 are saved/restored.
|
||||
* For THUMB-2, r0-r9, though r4-r9 are saved/restored.
|
||||
* Also, note that r0 is 0 when this code completes.
|
||||
*/
|
||||
|
||||
#if ARM_THUMB2 /* LSL is less capable in Thumb-2 */
|
||||
|
||||
#define _CORTEX_AR_ENTIRE_DATA_CACHE_OP(crm) \
|
||||
STMFD sp!, {r4-r9} /* save registers */;\
|
||||
\
|
||||
MRC p15, 1, r0, c0, c0, 1 /* r0 = Cache Lvl ID register info */;\
|
||||
ANDS r3, r0, ARM_LOC_MASK /* get level of coherency (LoC) */;\
|
||||
MOV r3, r3, LSR ARM_IMM 23 /* r3 = LoC << 1 */;\
|
||||
BEQ 5f ;\
|
||||
\
|
||||
MOV r7, ARM_IMM 0 /* r7 = cache level << 1; start at 0 */;\
|
||||
\
|
||||
1: ;\
|
||||
AND r1, r0, ARM_IMM 0x7 /* r1 = cache type(s) for this level */;\
|
||||
CMP r1, ARM_IMM 2 ;\
|
||||
BLT 4f /* no data cache at this level */;\
|
||||
\
|
||||
MCR p15, 2, r7, c0, c0, 0 /* select the Cache Size ID register */;\
|
||||
ISB /* ISB: sync change to Cache Size ID */;\
|
||||
MRC p15, 1, r1, c0, c0, 0 /* r1 = current Cache Size ID info */;\
|
||||
AND r2, r1, ARM_IMM 0x7 /* r2 = line length */;\
|
||||
ADD r2, r2, ARM_IMM 4 /* add line length offset = log2(16 bytes) */;\
|
||||
LDR r4, =0x3FF ;\
|
||||
ANDS r4, r4, r1, LSR ARM_IMM 3 /* r4 = (# of ways - 1); way index */;\
|
||||
CLZ r5, r4 /* r5 = bit position of way size increment */;\
|
||||
LDR r6, =0x00007FFF ;\
|
||||
ANDS r6, r6, r1, LSR ARM_IMM 13/* r6 = (# of sets - 1); set index */;\
|
||||
\
|
||||
2: ;\
|
||||
MOV r1, r4 /* r1 = working copy of way number */;\
|
||||
3: ;\
|
||||
LSL r9, r1, r5 /* r8 = set/way operation data word: */;\
|
||||
ORR r8, r7, r9 ;\
|
||||
LSL r9, r6, r2 /* cache level, way and set info */;\
|
||||
ORR r8, r8, r9 ;\
|
||||
\
|
||||
MCR p15, 0, r8, c7, crm, 2 /* dcache operation by set/way */;\
|
||||
\
|
||||
SUBS r1, r1, ARM_IMM 1 /* decrement the way index */;\
|
||||
BGE 3b ;\
|
||||
SUBS r6, r6, ARM_IMM 1 /* decrement the set index */;\
|
||||
BGE 2b ;\
|
||||
\
|
||||
4: ;\
|
||||
ADD r7, r7, ARM_IMM 2 /* increment cache index = level << 1 */;\
|
||||
CMP r3, r7 /* done when LoC is reached */;\
|
||||
MOVGT r0, r0, LSR ARM_IMM 3 /* rt-align type of next cache level */;\
|
||||
BGT 1b ;\
|
||||
\
|
||||
5: ;\
|
||||
DSB ;\
|
||||
LDMIA sp!, {r4-r9} /* restore registers */;
|
||||
|
||||
#else /* !ARM_THUMB2 */
|
||||
|
||||
#define _CORTEX_AR_ENTIRE_DATA_CACHE_OP(crm) \
|
||||
STMFD sp!, {r4-r8} /* save registers */;\
|
||||
\
|
||||
MRC p15, 1, r0, c0, c0, 1 /* r0 = Cache Lvl ID register info */;\
|
||||
ANDS r3, r0, ARM_LOC_MASK /* get level of coherency (LoC) */;\
|
||||
MOV r3, r3, LSR ARM_IMM 23 /* r3 = LoC << 1 */;\
|
||||
BEQ 5f ;\
|
||||
\
|
||||
MOV r7, ARM_IMM 0 /* r7 = cache level << 1; start at 0 */;\
|
||||
\
|
||||
1: ;\
|
||||
AND r1, r0, ARM_IMM 0x7 /* r1 = cache type(s) for this level */;\
|
||||
CMP r1, ARM_IMM 2 ;\
|
||||
BLT 4f /* no data cache at this level */;\
|
||||
\
|
||||
MCR p15, 2, r7, c0, c0, 0 /* select the Cache Size ID register */;\
|
||||
ISB /* ISB: sync change to Cache Size ID */;\
|
||||
MRC p15, 1, r1, c0, c0, 0 /* r1 = current Cache Size ID info */;\
|
||||
AND r2, r1, ARM_IMM 0x7 /* r2 = line length */;\
|
||||
ADD r2, r2, ARM_IMM 4 /* add line length offset = log2(16 bytes) */;\
|
||||
LDR r4, =0x3FF ;\
|
||||
ANDS r4, r4, r1, LSR ARM_IMM 3 /* r4 = (# of ways - 1); way index */;\
|
||||
CLZ r5, r4 /* r5 = bit position of way size increment */;\
|
||||
LDR r6, =0x00007FFF ;\
|
||||
ANDS r6, r6, r1, LSR ARM_IMM 13/* r6 = (# of sets - 1); set index */;\
|
||||
\
|
||||
2: ;\
|
||||
MOV r1, r4 /* r1 = working copy of way number */;\
|
||||
3: ;\
|
||||
ORR r8, r7, r1, LSL r5 /* r8 = set/way operation data word: */;\
|
||||
ORR r8, r8, r6, LSL r2 /* cache level, way and set info */;\
|
||||
\
|
||||
MCR p15, 0, r8, c7, crm, 2 /* dcache operation by set/way */;\
|
||||
\
|
||||
SUBS r1, r1, ARM_IMM 1 /* decrement the way index */;\
|
||||
BGE 3b ;\
|
||||
SUBS r6, r6, ARM_IMM 1 /* decrement the set index */;\
|
||||
BGE 2b ;\
|
||||
\
|
||||
4: ;\
|
||||
ADD r7, r7, ARM_IMM 2 /* increment cache index = level << 1 */;\
|
||||
CMP r3, r7 /* done when LoC is reached */;\
|
||||
MOVGT r0, r0, LSR ARM_IMM 3 /* rt-align type of next cache level */;\
|
||||
BGT 1b ;\
|
||||
\
|
||||
5: ;\
|
||||
DSB ;\
|
||||
LDMIA sp!, {r4-r8} /* restore registers */;
|
||||
|
||||
#endif /*ARM_THUMB2*/
|
||||
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheArmArch7h */
|
||||
@@ -0,0 +1,151 @@
|
||||
/* cacheArmLib.h - ARM cache library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996-2008, 2010-2012, 2014 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
06jan14,c_l Improve cache operation. (VXW6-27040)
|
||||
01w,17jul12,j_b Add Cortex-A15 cache support
|
||||
01v,07feb12,c_l Fix compiling error. (WIND00294062)
|
||||
01u,13jan11,m_h moving cacheArchAlignSize to arm.h
|
||||
01t,29apr10,pad Moved extern C statement after include statements.
|
||||
01s,02jul07,m_h Adding support for MPCore
|
||||
01r,12jun08,j_b add Cortex-A/-R cache support
|
||||
01q,22may06,m_h 946 Support
|
||||
01p,22feb06,m_h Manzano Support
|
||||
01o,28mar05,jb Adding 1136jfs Support
|
||||
01n,25jan05,jb Removing in-advertant addition of 1136
|
||||
01m,07dec04,jb Restructure for Base6
|
||||
01l,01dec03,scm modify for AIM support...
|
||||
01k,17dec02,jb Adding ARM10 and 926E support
|
||||
01k,24jan03,jb Resolve SPR 81285 and 82533
|
||||
01j,02oct01,jpd added definitions to support simplifications in source.
|
||||
01i,12nov01,to added cacheArchIntMask (merged from AE)
|
||||
01h,23jul01,scm change XScale name to conform to coding standards...
|
||||
01g,11dec00,scm replace references to ARMSA2 with XScale
|
||||
01f,01sep00,scm add sa2 support...
|
||||
01e,07sep99,jpd added ARM920T support.
|
||||
01d,24nov98,jpd added ARM940T, ARMSA1100, ARMSA1500 support;
|
||||
cdp restructured for multiple cache/MMU libraries.
|
||||
01c,09mar98,jpd tidied.
|
||||
01b,16sep97,jpd added cacheIMBRange(), 810 definitions for cacheDClear() and
|
||||
cacheArchIntLock().
|
||||
01a,09may96,cdp created
|
||||
*/
|
||||
|
||||
/*
|
||||
* N.B. although this library contains code written for the ARM810
|
||||
* CPU, at the time of writing, this code has not been fully tested on
|
||||
* that CPU. YOU HAVE BEEN WARNED.
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheArmLibh
|
||||
#define __INCcacheArmLibh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* Variable used to hold the interrupt mask used when disabling
|
||||
* interrupts for lengthy cache operations such as cache flushing. This
|
||||
* is preinitialised to a mask that disables IRQs and FIQs. The BSP may
|
||||
* change this. Do not do so unless you are sure that you understand the
|
||||
* consequences. In particular, if interrupts are allowed to occur
|
||||
* during these operations, the state of the cache afterwards may be
|
||||
* indeterminate.
|
||||
*/
|
||||
|
||||
IMPORT UINT32 cacheArchIntMask;
|
||||
|
||||
/* routine that locks interrupts according to the mask above */
|
||||
|
||||
IMPORT UINT32 cacheArchIntLock (void);
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/*
|
||||
* Arm Arch HW specific bits used by cache routines...
|
||||
*/
|
||||
|
||||
#define CACHE_MM_ENABLE (1<<0) /* MMU enable */
|
||||
#define CACHE_DC_ENABLE (1<<2) /* (data) cache enable */
|
||||
#define CACHE_WB_ENABLE (1<<3) /* write buffer enable */
|
||||
#define CACHE_IC_ENABLE (1<<12) /* Instruction cache enable */
|
||||
|
||||
#define LoC_MASK 0x07000000 /* level of coherency mask of CLIDR */
|
||||
#define LoC_SHIFT 23 /* level of coherency shift of CLIDR */
|
||||
#define LoUU_MASK 0x38000000 /* level of coherency mask of CLIDR */
|
||||
#define LoUU_SHIFT 26 /* level of coherency shift of CLIDR */
|
||||
|
||||
/*
|
||||
* Reset Architecture specific cache behavior.
|
||||
* It is set with the cpu include file.
|
||||
*/
|
||||
|
||||
#undef ARMCACHE_NOT_COHERENT
|
||||
#undef ARMCACHE_HAS_WRITETHROUGH
|
||||
#undef ARMCACHE_HAS_MINICACHE
|
||||
#undef ARMCACHE_NEEDS_IMB
|
||||
|
||||
#if (ARMCACHE == ARMCACHE_926E)
|
||||
#include "cacheArm926eLib.h"
|
||||
#elif (ARMCACHE == ARMCACHE_946E)
|
||||
#include "cacheArm946eLib.h"
|
||||
#elif (ARMCACHE == ARMCACHE_920T)
|
||||
#include "cacheArm920tLib.h"
|
||||
#elif (ARMCACHE == ARMCACHE_940T)
|
||||
#include "cacheArm940tLib.h"
|
||||
#elif (ARMCACHE == ARMCACHE_1022E)
|
||||
#include "cacheArm1022eLib.h"
|
||||
#elif (ARMCACHE == ARMCACHE_1136JF)
|
||||
#include "cacheArm1136jfLib.h"
|
||||
#elif (ARMCACHE == ARMCACHE_XSCALE)
|
||||
#include "cacheArmXSCALELib.h"
|
||||
#elif (ARMCACHE == ARMCACHE_MANZANO)
|
||||
#include "cacheArmManzanoLib.h"
|
||||
#elif (ARMCACHE == ARMCACHE_CORTEXA8)
|
||||
#include "cacheCortexA8Lib.h"
|
||||
#elif (ARMCACHE == ARMCACHE_11MPCORE)
|
||||
#include "cacheArm11MPCoreLib.h"
|
||||
#elif (ARMCACHE == ARMCACHE_CORTEXA15)
|
||||
#include "cacheCortexA15Lib.h"
|
||||
#endif /* ARMCACHE == ARMCACHE_926E */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if (ARMCACHE != ARMCACHE_NONE)
|
||||
|
||||
/*
|
||||
* Verify the cpu has established some special attributes
|
||||
*/
|
||||
|
||||
#ifndef ARMCACHE_NOT_COHERENT
|
||||
#error ARMCACHE value not supported in definition of ARMCACHE_NOT_COHERENT
|
||||
#endif
|
||||
|
||||
#ifndef ARMCACHE_HAS_WRITETHROUGH
|
||||
#error ARMCACHE value not supported in definition of ARMCACHE_HAS_WRITETHROUGH
|
||||
#endif
|
||||
|
||||
#ifndef ARMCACHE_HAS_MINICACHE
|
||||
#define ARMCACHE_HAS_MINICACHE FALSE
|
||||
#endif
|
||||
|
||||
#ifndef ARMCACHE_NEEDS_IMB
|
||||
#error ARMCACHE value not supported in definition of ARMCACHE_NEEDS_IMB
|
||||
#endif
|
||||
|
||||
#endif /* ARMCACHE_NONE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheArmLibh */
|
||||
@@ -0,0 +1,78 @@
|
||||
/* cacheArmManzanoLib.h - ARM XScale cache library header file */
|
||||
|
||||
/* Copyright 199-2005 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01i,22feb06,m_h Manzano Support
|
||||
01h,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01g,07dec04,jb Further Palify ARM Aim cache
|
||||
01f,01dec03,scm flushing out aim...
|
||||
01e,25jul01,scm add btbInvalidate...
|
||||
01d,23jul01,scm change XScale name to conform to coding standards...
|
||||
01c,09feb01,scm add support for cache & TLB locking...
|
||||
01b,19dec00,scm correct cache sizes...
|
||||
01a,31aug00,scm created
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheArmManzanoLibh
|
||||
#define __INCcacheArmManzanoLibh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define D_CACHE_SIZE (32*1024) /* 32 kbytes DCache */
|
||||
#define I_CACHE_SIZE (32*1024) /* 32 kbytes ICache */
|
||||
|
||||
#define MINI_CACHE_SIZE (2*1024) /* 2 kbytes minicache */
|
||||
#define MINI_CACHE_LINE_SIZE 32 /* 32 bytes per line*/
|
||||
|
||||
/*
|
||||
* Some cache designs (e.g. Harvard) have D-cache either fully or
|
||||
* partially not coherent with I-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NOT_COHERENT TRUE
|
||||
|
||||
/*
|
||||
* This is a writethrough cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_WRITETHROUGH TRUE
|
||||
|
||||
/*
|
||||
* Has a mini-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_MINICACHE TRUE
|
||||
|
||||
/*
|
||||
* Does not need an Instruction Memory Barrier
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NEEDS_IMB FALSE
|
||||
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void cacheArmManzanoLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
|
||||
|
||||
/* definitions to allow for non-cacheAim direct calls */
|
||||
|
||||
#define cacheArmManzanoDClearDisable cacheAimManzanoDClearDisable
|
||||
#define cacheArmManzanoIClearDisable cacheAimManzanoIClearDisable
|
||||
|
||||
IMPORT void cacheAimManzanoDClearDisable (void);
|
||||
IMPORT void cacheAimManzanoIClearDisable (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheArmManzanoLibh */
|
||||
@@ -0,0 +1,77 @@
|
||||
/* cacheArmXSCALELib.h - ARM XScale cache library header file */
|
||||
|
||||
/* Copyright 199-2005 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01h,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01g,07dec04,jb Further Palify ARM Aim cache
|
||||
01f,01dec03,scm flushing out aim...
|
||||
01e,25jul01,scm add btbInvalidate...
|
||||
01d,23jul01,scm change XScale name to conform to coding standards...
|
||||
01c,09feb01,scm add support for cache & TLB locking...
|
||||
01b,19dec00,scm correct cache sizes...
|
||||
01a,31aug00,scm created
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheArmXSCALELibh
|
||||
#define __INCcacheArmXSCALELibh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define D_CACHE_SIZE (32*1024) /* 32 kbytes DCache */
|
||||
#define I_CACHE_SIZE (32*1024) /* 32 kbytes ICache */
|
||||
|
||||
#define MINI_CACHE_SIZE (2*1024) /* 2 kbytes minicache */
|
||||
#define MINI_CACHE_LINE_SIZE 32 /* 32 bytes per line*/
|
||||
|
||||
/*
|
||||
* Some cache designs (e.g. Harvard) have D-cache either fully or
|
||||
* partially not coherent with I-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NOT_COHERENT TRUE
|
||||
|
||||
/*
|
||||
* This is a writethrough cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_WRITETHROUGH TRUE
|
||||
|
||||
/*
|
||||
* Has a mini-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_MINICACHE TRUE
|
||||
|
||||
/*
|
||||
* Does not need an Instruction Memory Barrier
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NEEDS_IMB FALSE
|
||||
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void cacheArmXSCALELibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
|
||||
|
||||
/* definitions to allow for non-cacheAim direct calls */
|
||||
|
||||
#define cacheArmXSCALEDClearDisable cacheAimXSCALEDClearDisable
|
||||
#define cacheArmXSCALEIClearDisable cacheAimXSCALEIClearDisable
|
||||
|
||||
IMPORT void cacheAimXSCALEDClearDisable (void);
|
||||
IMPORT void cacheAimXSCALEIClearDisable (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheArmXSCALELibh */
|
||||
@@ -0,0 +1,110 @@
|
||||
/* cacheCortexA15Lib.h - Cortex-A15 cache library header file */
|
||||
|
||||
/*
|
||||
* Copyright 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,31aug12,ggm Added SMP support.
|
||||
01a,14jul12,j_b Created from cacheCortexA8Lib.h, rev 01c
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheCortexA15Libh
|
||||
#define __INCcacheCortexA15Libh
|
||||
|
||||
/*
|
||||
* Include ARCH7 common defines.
|
||||
*/
|
||||
|
||||
#include "arch/arm/cacheArmArch7.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some cache designs (e.g. Harvard) have D-cache either fully or
|
||||
* partially not coherent with I-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NOT_COHERENT TRUE
|
||||
|
||||
/*
|
||||
* This is a writethrough cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_WRITETHROUGH TRUE
|
||||
|
||||
/*
|
||||
* Does not have a mini-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_MINICACHE FALSE
|
||||
|
||||
/*
|
||||
* Does need an Instruction Memory Barrier
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NEEDS_IMB TRUE
|
||||
|
||||
/*
|
||||
* Most of the cache designs are virtually addressed, but some newer
|
||||
* ones have physically addressed caches. Note that this is the method of
|
||||
* addressing, not whether the cache has physical address tags within
|
||||
* it.
|
||||
*/
|
||||
|
||||
#define ARMCACHE_IS_PHYSICALLY_ADDRESSED TRUE
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void cacheCortexA15LibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
|
||||
IMPORT void cacheCortexA15DClearDisable (void); /* includes L2 cache */
|
||||
|
||||
/* L2 Cache support functions */
|
||||
|
||||
IMPORT UINT32 cacheCortexA15L2CacrGet (void);
|
||||
IMPORT void cacheCortexA15L2CacrSet (UINT32 cacr);
|
||||
IMPORT UINT32 cacheCortexA15L2EcrGet (void);
|
||||
IMPORT void cacheCortexA15L2EcrSet (UINT32 ecr);
|
||||
|
||||
IMPORT void cacheCortexA8L2ClearAll (void);
|
||||
|
||||
/* CPU ID access function and definitions */
|
||||
|
||||
IMPORT UINT32 mmuReadId (void);
|
||||
|
||||
/* SMP support functions */
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
IMPORT void cacheCortexA15MPCoreSMPInit(void);
|
||||
#endif
|
||||
|
||||
#define MAIN_ID_PART_MASK 0xFFF0
|
||||
#define MAIN_ID_PART_SHIFT 0x4
|
||||
#define MAIN_ID_PART_CORTEXA15 0xC0F
|
||||
|
||||
/* Auxiliary Control Register access functions and definitions */
|
||||
|
||||
IMPORT UINT32 mmuCortexA8AcrGet (void);
|
||||
IMPORT void mmuCortexA8AcrSet (UINT32 acrVal);
|
||||
|
||||
/* enable invalidation of branch tgt buffer with I-cache invalidate */
|
||||
|
||||
#define ACTLR_BTB_INVAL_EN 0x1
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheCortexA15Libh */
|
||||
@@ -0,0 +1,87 @@
|
||||
/* cacheCortexA8Lib.h - Cortex-A8 cache library header file */
|
||||
|
||||
/*
|
||||
* Copyright 2008, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,23sep10,j_b add cacheCortexL2ClearAll() prototype
|
||||
01b,29apr10,pad Moved extern C statement after include statements.
|
||||
01a,03jun08,j_b Created from cacheArm1136jfLib.h, rev 01b
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheCortexA8Libh
|
||||
#define __INCcacheCortexA8Libh
|
||||
|
||||
/*
|
||||
* Include ARCH7 common defines.
|
||||
*/
|
||||
|
||||
#include "arch/arm/cacheArmArch7.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some cache designs (e.g. Harvard) have D-cache either fully or
|
||||
* partially not coherent with I-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NOT_COHERENT TRUE
|
||||
|
||||
/*
|
||||
* This is a writethrough cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_WRITETHROUGH TRUE
|
||||
|
||||
/*
|
||||
* Does not have a mini-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_HAS_MINICACHE FALSE
|
||||
|
||||
/*
|
||||
* Do not need an Instruction Memory Barrier
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NEEDS_IMB TRUE
|
||||
|
||||
/*
|
||||
* Most of the cache designs are virtually addressed, but some newer
|
||||
* ones have physically addressed caches. Note that this is the method of
|
||||
* addressing, not whether the cache has physical address tags within
|
||||
* it.
|
||||
*/
|
||||
|
||||
#define ARMCACHE_IS_PHYSICALLY_ADDRESSED TRUE
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void cacheCortexA8LibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
|
||||
IMPORT void cacheCortexA8DClearDisable (void); /* includes L2 cache */
|
||||
|
||||
/* L2 Cache support functions */
|
||||
|
||||
IMPORT UINT32 cacheCortexA8L2CacrGet (void);
|
||||
IMPORT void cacheCortexA8L2CacrSet (UINT32 cacr);
|
||||
IMPORT void cacheCortexA8L2Enable (void);
|
||||
IMPORT void cacheCortexA8L2Disable (void);
|
||||
IMPORT void cacheCortexA8L2ClearAll (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheCortexA8Libh */
|
||||
@@ -0,0 +1,75 @@
|
||||
/* cacheCortexA9Lib.h - Cortex-A9 cache library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,29apr10,pad Moved extern C statement after include statements.
|
||||
01b,20oct09,z_l Created from cacheCortexA8Lib.h, rev 01a
|
||||
*/
|
||||
|
||||
#ifndef __INCcacheCortexA9Libh
|
||||
#define __INCcacheCortexA9Libh
|
||||
|
||||
/* Include ARCH7 common defines. */
|
||||
|
||||
#include "arch/arm/cacheArmArch7.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some cache designs (e.g. Harvard) have D-cache either fully or
|
||||
* partially not coherent with I-cache
|
||||
*/
|
||||
|
||||
#define ARMCACHE_NOT_COHERENT TRUE
|
||||
|
||||
/* This is a writethrough cache */
|
||||
|
||||
#define ARMCACHE_HAS_WRITETHROUGH TRUE
|
||||
|
||||
/* Does not have a mini-cache */
|
||||
|
||||
#define ARMCACHE_HAS_MINICACHE FALSE
|
||||
|
||||
/* Do not need an Instruction Memory Barrier */
|
||||
|
||||
#define ARMCACHE_NEEDS_IMB TRUE
|
||||
|
||||
/*
|
||||
* Most of the cache designs are virtually addressed, but some newer
|
||||
* ones have physically addressed caches. Note that this is the method of
|
||||
* addressing, not whether the cache has physical address tags within
|
||||
* it.
|
||||
*/
|
||||
|
||||
#define ARMCACHE_IS_PHYSICALLY_ADDRESSED TRUE
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void cacheCortexA9LibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
IMPORT void cacheCortexA9DClearDisable (void);
|
||||
|
||||
/* SMP support functions */
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
IMPORT void cacheCortexA9MPCoreSMPInit(void);
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcacheCortexA9Libh */
|
||||
@@ -0,0 +1,45 @@
|
||||
/* coprocArm.h - coprocessor management library header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2004-2007, 2010, 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01f,15may12,jmp CQID: Fix WIND00309977 : Added VX_COPROCS_ALL_TASK
|
||||
definition.
|
||||
01e,28apr10,pad Moved extern C statement after include statements.
|
||||
01d,02oct07,jb Move VFP to FP equivilent, part of fix for WIND00093069
|
||||
01c,30jun05,scm add support for ARM VFP...
|
||||
01b,04aug04,scm fix permissions...
|
||||
01a,03aug04,scm written based on coprocI86.h 01a.
|
||||
*/
|
||||
|
||||
#ifndef __INCcoprocArmh
|
||||
#define __INCcoprocArmh
|
||||
|
||||
/* includes */
|
||||
|
||||
#include <taskLib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* defines */
|
||||
|
||||
#define VX_FP_TASK VX_COPROC1_TASK
|
||||
#define VX_VFP_TASK VX_FP_TASK
|
||||
|
||||
#define VX_COPROCS_ALL_TASK VX_FP_TASK
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcoprocArmh */
|
||||
@@ -0,0 +1,110 @@
|
||||
/* dbgArmLib.h - header file for ARM-dependent part of debugger */
|
||||
|
||||
/*
|
||||
* Copyright 1996-2004, 2005, 2010, 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use of this
|
||||
* software may be licensed only pursuant to the terms of an applicable Wind
|
||||
* River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01j,26may13,pma Update for ARMARCH7M
|
||||
01i,26jul10,jdw Update with support for THUMB2
|
||||
01h,29apr10,pad Moved extern C statement after include statements.
|
||||
01g,24feb05,jb Correct definition of SYSCALL_INST
|
||||
01f,09dec04,scm resolve DBG_SYSCALL_SIZE warning, define DBG_SYSCALL_INST
|
||||
01e,11feb04,elg Add syscall instruction size macro.
|
||||
01d,12nov98,cdp added support for ARM generic Thumb library.
|
||||
01c,20apr98,dbt modified for new breakpoint scheme
|
||||
01b,24apr97,cdp added Thumb (ARM7TDMI_T) support;
|
||||
changed DBG_BREAK_INST for non-Thumb processors.
|
||||
01a,09may96,cdp created
|
||||
*/
|
||||
|
||||
#ifndef __INCdbgArmLibh
|
||||
#define __INCdbgArmLibh
|
||||
|
||||
|
||||
#include "esf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define BREAK_ESF ESF
|
||||
#define TRACE_ESF ESF
|
||||
|
||||
#define DBG_SYSCALL_SIZE (sizeof (INSTR) / sizeof (INSTR))
|
||||
|
||||
#if (ARM_THUMB2)
|
||||
#define DBG_SYSCALL_INST 0xDF00 /* SVC */
|
||||
#define DBG_SYSCALL_MASK 0xFF00
|
||||
#else /* (ARM_THUMB2) */
|
||||
#define DBG_SYSCALL_INST 0xEF0000FA /* SVC (formerly SWI) */
|
||||
#endif /* (ARM_THUMB2) */
|
||||
|
||||
#if (ARM_THUMB2)
|
||||
/*
|
||||
* For Thumb2 we can not support cret() without a valid frame pointer so
|
||||
* support is disabled here.
|
||||
*/
|
||||
#define DBG_CRET FALSE
|
||||
#endif /* (ARM_THUMB2) */
|
||||
|
||||
#if (ARM_THUMB) || (ARM_THUMB2)
|
||||
|
||||
/*
|
||||
* TODO -- The WDB code which inserts breakpoints needs to be smarter
|
||||
* than it is. We need to use a 16- or 32-bit value depending on the
|
||||
* instruction we are going to break on.
|
||||
*/
|
||||
|
||||
#define DBG_BREAK_INST 0xDEFE /* The undefined instruction used as a
|
||||
* breakpoint for Thumb-state */
|
||||
#define DBG_INST_ALIGN 2
|
||||
#else /* (ARM_THUMB) || (ARM_THUMB2) */
|
||||
|
||||
#define DBG_BREAK_INST 0xE7FDDEFE /* The undefined instruction used as a
|
||||
* breakpoint for ARM-state */
|
||||
#define DBG_INST_ALIGN 4
|
||||
#endif /* (ARM_THUMB) || (ARM_THUMB2) */
|
||||
|
||||
#define DBG_NO_SINGLE_STEP 1 /* no hardware trace support */
|
||||
|
||||
#if (CPU == ARMARCH7M)
|
||||
|
||||
#define BRK_INST 0x0 /* hardware instruction breakpoint */
|
||||
#define DEFAULT_HW_BP (BRK_INST) /* default hardware breakpoint */
|
||||
#define BRK_HARDWARE (0x10) /* hardware breakpoint bit */
|
||||
#define BRK_HARDMASK (0x0f) /* hardware breakpoint mask */
|
||||
|
||||
#define DBG_HARDWARE_BP 1
|
||||
|
||||
#ifdef DBG_NO_SINGLE_STEP
|
||||
#undef DBG_NO_SINGLE_STEP
|
||||
#endif
|
||||
#define DBG_NO_SINGLE_STEP 0 /* no trace support */
|
||||
#define MAX_HW_BP_NUM 6
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* hardware breakpoint registers */
|
||||
|
||||
typedef struct /* DBG_REGS */
|
||||
{
|
||||
unsigned int fp_compx[MAX_HW_BP_NUM]; /* debug register: flash patch */
|
||||
} DBG_REGS;
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* ARMARCH7M */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCdbgArmLibh */
|
||||
@@ -0,0 +1,127 @@
|
||||
/* dsmArmLib.h - ARM disassembler header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996-2005, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,19oct10,jmp Updated INSTR_IS() macro to use VXDBG_INSTR_CMP()
|
||||
(CQ:WIND00185617).
|
||||
01b,29apr10,pad Moved extern C statement after include statements.
|
||||
01a,14jan05,rec add print function to dsmInst
|
||||
01c,09oct97.jpd added more Thumb instructions.
|
||||
01b,09sep97,cdp added more instructions.
|
||||
01a,09may96,cdp created.
|
||||
*/
|
||||
|
||||
#ifndef __INCdsmArmLibh
|
||||
#define __INCdsmArmLibh
|
||||
|
||||
|
||||
|
||||
#include <vwModNum.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* dsmLib status codes */
|
||||
|
||||
#define S_dsmLib_UNKNOWN_INSTRUCTION (M_dsmLib | 1)
|
||||
|
||||
/*
|
||||
* Macro and definitions for simple decoding of instuctions.
|
||||
* To check an instruction, it is ANDed with the IMASK_ and
|
||||
* the result is compared with the IOP_. The macro INSTR_IS
|
||||
* does this and returns !0 to indicate a match.
|
||||
*/
|
||||
|
||||
#define INSTR_IS(pInstr,o) VXDBG_INSTR_CMP(pInstr,(IOP_##o),(IMASK_##o))
|
||||
|
||||
#define IMASK_BL 0x0F000000 /* BL xxx */
|
||||
#define IOP_BL 0x0B000000
|
||||
|
||||
#define IMASK_STMDB_SPP_FP_IP_LR_PC 0xFFFFF800 /* STMDB sp!,{..fp,ip,lr,pc} */
|
||||
#define IOP_STMDB_SPP_FP_IP_LR_PC 0xE92DD800
|
||||
|
||||
#define IMASK_SUB_FP_IP_4 0xFFFFFFFF /* SUB fp,ip,#4 */
|
||||
#define IOP_SUB_FP_IP_4 0xE24CB004
|
||||
|
||||
#define IMASK_SUB_FP_IP_4PLUS 0xFFFFF000 /* SUB fp,ip,#4+ */
|
||||
#define IOP_SUB_FP_IP_4PLUS 0xE24CB000
|
||||
|
||||
#define IMASK_MOV_IP_SP 0xFFFFFFFF /* MOV ip,sp */
|
||||
#define IOP_MOV_IP_SP 0xE1A0C00D
|
||||
|
||||
#define IMASK_MOVXX_LR_PC 0x0FFFFFFF /* MOVxx lr,pc */
|
||||
#define IOP_MOVXX_LR_PC 0x01A0E00F
|
||||
|
||||
#define IMASK_STMDB_SPP_AREGS 0xFFFFFFF0 /* STMDB sp!,{a1-a4} */
|
||||
#define IOP_STMDB_SPP_AREGS 0xE92D0000
|
||||
|
||||
#define IMASK_SUB_SP_SP 0xFFFFF000 /* SUB sp,sp,#n */
|
||||
#define IOP_SUB_SP_SP 0xE24DD000
|
||||
|
||||
#define IMASK_MOVS_PC_LR 0xFFFFFFFF /* MOVS pc,lr */
|
||||
#define IOP_MOVS_PC_LR 0xE1B0F00E
|
||||
|
||||
/* Thumb instructions */
|
||||
|
||||
#define IMASK_T_BL0 0xF800 /* BL prefix */
|
||||
#define IOP_T_BL0 0xF000
|
||||
|
||||
#define IMASK_T_BL1 0xF800 /* BL */
|
||||
#define IOP_T_BL1 0xF800
|
||||
|
||||
#define IMASK_T_MOV_LR_PC 0xFFFF /* MOV lr,pc */
|
||||
#define IOP_T_MOV_LR_PC 0x46FE
|
||||
|
||||
#define IMASK_T_SUB_SP_16 0xFFFF /* SUB sp,#16 */
|
||||
#define IOP_T_SUB_SP_16 0xB084
|
||||
|
||||
#define IMASK_T_MOV_FP_LO 0xFFC7 /* MOV fp,loreg */
|
||||
#define IOP_T_MOV_FP_LO 0x4683
|
||||
|
||||
#define IMASK_T_MOV_SP_LO 0xFFC7 /* MOV sp,loreg */
|
||||
#define IOP_T_MOV_SP_LO 0x4685
|
||||
|
||||
#define IMASK_T_ADD_LO_SP 0xF800 /* ADD loreg, sp, #Imm */
|
||||
#define IOP_T_ADD_LO_SP 0xA800
|
||||
|
||||
#define IMASK_T_POP_LO 0xFF00 /* POP {reglist} (not PC) */
|
||||
#define IOP_T_POP_LO 0xBC00
|
||||
|
||||
#define IMASK_T_PUSH_LO 0xFF00 /* PUSH {reglist} (not LR) */
|
||||
#define IOP_T_PUSH_LO 0xB400
|
||||
|
||||
#define IMASK_T_PUSH 0xFF00 /* PUSH {reglist} (inc LR) */
|
||||
#define IOP_T_PUSH 0xB500
|
||||
|
||||
#define IMASK_T_BX_LO 0xFFC0 /* BX loreg */
|
||||
#define IOP_T_BX_LO 0x4700
|
||||
|
||||
#define IMASK_T_MOV_LO_PC 0xFFF8 /* MOV loreg,pc */
|
||||
#define IOP_T_MOV_LO_PC 0x4678
|
||||
|
||||
#define IMASK_T_MOV_LO_FP 0xFFF8 /* MOV loreg,fp */
|
||||
#define IOP_T_MOV_LO_FP 0x4658
|
||||
|
||||
IMPORT int dsmNbytes(FAST INSTR *binInst);
|
||||
IMPORT int dsmInst(FAST INSTR *binInst, int address, VOIDFUNCPTR prtAddress,
|
||||
FUNCPTR oFn, int oArg);
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCdsmArmLibh */
|
||||
@@ -0,0 +1,100 @@
|
||||
/* elfArm.h - ARM-specific elf loader header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001,2004-2005,2009-2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software may be
|
||||
* licensed only pursuant to the terms of an applicable Wind River license
|
||||
* agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01g,11oct10,v_r Added support for the R_ARM_CALL and R_ARM_THM_JUMP24
|
||||
relocation types (CQ:WIND00234720).
|
||||
Removed unused types (by both the kernel loader and the
|
||||
userspace shared lib loader).
|
||||
01f,14dec09,pgh Add EM_ARCH_MACHINE_x macro definition.
|
||||
01e,25jul05,v_r Updated copyright.
|
||||
01d,18feb05,dbt Cleanup.
|
||||
01c,18sep04,jn Move towards shared code for host and target loaders
|
||||
01b,17feb04,jn Merged version from AE.
|
||||
01b,30nov01,pad Moved definitions of CHECK_FITS and SIGN_EXTEND into
|
||||
loadElfLibP.h
|
||||
01a,24aug01,jn created, based on vxWorksAE 1.1
|
||||
share/src/loader/elfArm.h@@/main/tor3_x/5
|
||||
*/
|
||||
|
||||
#ifndef __INCelfArmh
|
||||
#define __INCelfArmh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* macro to check that a signed <val> fits in <nBits> without overflow
|
||||
* i.e. that the "sign-bit" is correctly propagated into the excess high bits
|
||||
*/
|
||||
|
||||
#define CHECK_FITS(val,nBits) \
|
||||
((((val) & ~((1 << ((nBits)-1))-1)) == 0) || \
|
||||
(((val) & ~((1 << ((nBits)-1))-1)) == ~(UINT32)((1 << ((nBits)-1))-1)))
|
||||
|
||||
/* macros to insert the low n bits of a value into a buffer. */
|
||||
|
||||
#define LOW24_INSERT(buf,value) INSERT ((buf), (value), 0x00ffffff)
|
||||
|
||||
#define LOW16_INSERT(buf,value) INSERT ((buf), (value), 0x0000ffff)
|
||||
|
||||
#define LOW12_INSERT(buf,value) INSERT ((buf), (value), 0x00000fff)
|
||||
|
||||
#define LOW11_INSERT(buf,value) INSERT ((buf), (value), 0x000007ff)
|
||||
|
||||
#define LOW8_INSERT(buf,value) INSERT ((buf), (value), 0x000000ff)
|
||||
|
||||
#define BITS6_10_INSERT(buf,value) INSERT ((buf), (value) << 6, 0x000007c0)
|
||||
|
||||
#define UBIT_INSERT(buf,value) INSERT ((buf), (value) << 23 , 0x0080000)
|
||||
|
||||
/*
|
||||
* The following macro defines the ELF machine type value that can be loaded
|
||||
* into an ARM CPU.
|
||||
*/
|
||||
|
||||
#define EM_ARCH_MACHINE_1 EM_ARM
|
||||
|
||||
#define EM_ARCH_MACHINE EM_ARM
|
||||
#define EM_ARCH_MACH_ALT EM_ARM /* not used */
|
||||
|
||||
/* Relocation Type Definitions */
|
||||
|
||||
#define R_ARM_NONE 0 /* No reloc */
|
||||
#define R_ARM_PC24 1
|
||||
#define R_ARM_ABS32 2
|
||||
#define R_ARM_REL32 3
|
||||
#define R_ARM_PC13 4
|
||||
#define R_ARM_ABS16 5
|
||||
#define R_ARM_ABS12 6
|
||||
#define R_ARM_THM_ABS5 7
|
||||
#define R_ARM_ABS8 8
|
||||
#define R_ARM_THM_PC22 10
|
||||
#define R_ARM_THM_PC8 11
|
||||
#define R_ARM_COPY 20 /* copy symbol at runtime */
|
||||
#define R_ARM_GLOB_DAT 21 /* create GOT entry */
|
||||
#define R_ARM_JUMP_SLOT 22 /* create PLT entry */
|
||||
#define R_ARM_RELATIVE 23 /* adjust by program base */
|
||||
#define R_ARM_CALL 28
|
||||
#define R_ARM_THM_JUMP24 30
|
||||
|
||||
#define R_ARM_THM_PC11 102 /* cygnus extension to abi: */
|
||||
/* thumb unconditional branch */
|
||||
#define R_ARM_THM_PC9 103 /* cygnus extension to abi: */
|
||||
/* thumb conditional branch */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCelfArmh */
|
||||
@@ -0,0 +1,64 @@
|
||||
/* esfArm.h - ARM exception stack frames */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996, 2004, 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,09may12,j_b enable ARMARCH7M-specific header usage
|
||||
01d,03may12,j_b revert to remove ARMARCH7M-specific header usage
|
||||
01c,01may12,j_b Update for ARMv7M
|
||||
01b,09sep04,scm add ttbase to ESF, so structs REG_SET & ESF overlap correctly
|
||||
01a,09may96,cdp created
|
||||
*/
|
||||
|
||||
#ifndef __INCesfArmh
|
||||
#define __INCesfArmh
|
||||
|
||||
#if (CPU == ARMARCH7M)
|
||||
|
||||
#include "arch/arm/arm-m/esfArm-m.h"
|
||||
|
||||
#else /* (CPU == ARMARCH7M) */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* The Exception Stack Frame
|
||||
* On the ARM, this is faked by a stub and the pointer
|
||||
* passed back points to the PC and CPSR at the end of the
|
||||
* register structure. If that changes, so must this.
|
||||
*
|
||||
* I.E. REG_SET struct & ESf struct 'overlap' on last 3
|
||||
* elements of REG_SET (pc,cpsr,ttbase)...
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
INSTR *pc; /* program counter */
|
||||
ULONG cpsr; /* current PSR */
|
||||
ULONG ttbase; /* Trans Table Base */
|
||||
UINT32 vecAddr; /* address of exception vector => type */
|
||||
} ESF;
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* (CPU == ARMARCH7M) */
|
||||
|
||||
#endif /* __INCesfArmh */
|
||||
@@ -0,0 +1,119 @@
|
||||
/* excArmLib.h - ARM exception library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996-2003,2006,2009,2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01g,14may12,m_h enable ARMARCH7M-specific header usage
|
||||
01f,23mar09,m_h Support for non-zero exception vector base
|
||||
01e,01feb06,jb Adding VFP Support
|
||||
01d,26nov03,pes Correct _WRS_IS_SUPV_EXC macro.
|
||||
01c,18nov03,pes Add _WRS_IS_SUPV_EXC macro.
|
||||
01b,23jul01,scm change XScale name to conform to coding standards...
|
||||
01a,11dec00,scm replace references to ARMSA2 with XScale
|
||||
01c,16oct00,scm reverse back I & F bits for SA2
|
||||
01b,15sep00,scm update for SA2 support...
|
||||
01a,09may96,cdp created
|
||||
*/
|
||||
|
||||
#ifndef __INCexcArmLibh
|
||||
#define __INCexcArmLibh
|
||||
|
||||
#if (CPU == ARMARCH7M)
|
||||
|
||||
#include "arch/arm/arm-m/excArmLib-m.h"
|
||||
|
||||
#else /* (CPU == ARMARCH7M) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* NOTE: if this structure changes, the TCB offsets in h/private/taskLibP.h
|
||||
* must be updated. See also taskLib.h.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT32 valid; /* indicators that following fields are valid */
|
||||
UINT32 vecAddr; /* exception vector address */
|
||||
INSTR * pc; /* PC */
|
||||
UINT32 cpsr; /* CPSR */
|
||||
} EXC_INFO;
|
||||
|
||||
#define _WRS_IS_SUPV_EXC() (((excInfo.cpsr & MASK_MODE) == MODE_USER32) ? FALSE : TRUE)
|
||||
|
||||
extern FUNCPTR excExcepHook; /* add'l rtn to call when exceptions occur */
|
||||
extern VOIDFUNCPTR _func_excBreakpoint; /* called to handle breakpoints */
|
||||
|
||||
extern void excVecBaseSet (UINT32 base); /* non-zero exception base address */
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
|
||||
extern STATUS excIntConnect (VOIDFUNCPTR *, VOIDFUNCPTR);
|
||||
extern void excVecSet (FUNCPTR *, FUNCPTR);
|
||||
extern FUNCPTR excVecGet (FUNCPTR *);
|
||||
|
||||
|
||||
#else /* __STDC__ */
|
||||
|
||||
extern STATUS excIntConnect ();
|
||||
extern void excVecSet ();
|
||||
extern FUNCPTR excVecGet ();
|
||||
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#endif /* ASMLANGUAGE */
|
||||
|
||||
|
||||
/* exception information valid bits */
|
||||
|
||||
#define EXC_INFO_VECADDR 0x01 /* vector is valid */
|
||||
#define EXC_INFO_PC 0x02 /* PC is valid */
|
||||
#define EXC_INFO_CPSR 0x04 /* CPSR is valid */
|
||||
#define EXC_INFO_VFPCSR 0x08 /* VFP CSR is valid */
|
||||
|
||||
|
||||
/* exception vector addresses */
|
||||
|
||||
#define EXC_OFF_RESET 0x00 /* reset */
|
||||
#define EXC_OFF_UNDEF 0x04 /* undefined instruction */
|
||||
#define EXC_OFF_SWI 0x08 /* software interrupt */
|
||||
#define EXC_OFF_PREFETCH 0x0c /* prefetch abort */
|
||||
#define EXC_OFF_DATA 0x10 /* data abort */
|
||||
#define EXC_OFF_IRQ 0x18 /* interrupt */
|
||||
#define EXC_OFF_FIQ 0x1C /* fast interrupt */
|
||||
|
||||
/* Exception Vector Base */
|
||||
#define ARM_EXC_VEC_BASE 0x00
|
||||
|
||||
/*
|
||||
* In coyanosa I80310 the default vector base is 0x00,
|
||||
* can be relocated into 0xFFFF0000
|
||||
*
|
||||
*/
|
||||
|
||||
#if ((CPU==XSCALE) || (CPU==ARMSA110))
|
||||
#define ARM_EXC_VEC_BASE_RELOCATED 0xffff0000
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* (CPU == ARMARCH7M) */
|
||||
|
||||
#endif /* __INCexcArmLibh */
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
/* fppArmLib.h - ARM floating-point coprocessor support header file */
|
||||
|
||||
/*
|
||||
* Copyright 1996, 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,11jan12,jdw Update to call the VFP routines, WIND00327855
|
||||
01a,09may96,cdp created
|
||||
*/
|
||||
|
||||
#ifndef __INCfppArmLibh
|
||||
#define __INCfppArmLibh
|
||||
|
||||
#include <arch/arm/vfpArmLib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define FP_CONTEXT VFP_CONTEXT
|
||||
|
||||
#define FPREG_SET FP_CONTEXT
|
||||
|
||||
|
||||
/* variable declarations */
|
||||
|
||||
extern REG_INDEX fpRegName[]; /* f-point data register table */
|
||||
extern REG_INDEX fpCtlRegName[]; /* f-point control register table */
|
||||
extern WIND_TCB *pFppTaskIdPrevious; /* task id for deferred exceptions */
|
||||
extern FUNCPTR fppCreateHookRtn; /* arch dependent create hook routine */
|
||||
extern FUNCPTR fppDisplayHookRtn; /* arch dependent display routine */
|
||||
|
||||
|
||||
/* function declarations */
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
|
||||
IMPORT void fppArchInit (void);
|
||||
IMPORT void fppArchTaskCreateInit (FP_CONTEXT *pFpContext);
|
||||
|
||||
#else /* __STDC__ */
|
||||
|
||||
IMPORT void fppArchInit ();
|
||||
IMPORT void fppArchTaskCreateInit ();
|
||||
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCfppArmLibh */
|
||||
@@ -0,0 +1,179 @@
|
||||
/* in_cksum.h - x86 version in_cksum header file */
|
||||
|
||||
/* Copyright 2001-2002 Wind River Systems, Inc. */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1990 The Regents of the University of California.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
|
||||
* 4. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* from tahoe: in_cksum.c 1.2 86/01/05
|
||||
* from: @(#)in_cksum.c 1.3 (Berkeley) 1/19/91
|
||||
* from: Id: in_cksum.c,v 1.8 1995/12/03 18:35:19 bde Exp
|
||||
* $FreeBSD: src/sys/i386/include/in_cksum.h,v 1.7.2.1 2000/05/05 13:37:00 jlemon Exp $
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01g,25aug05,dlk Add section tags.
|
||||
01f,24mar04,m_h Internet Checksum
|
||||
01e,18mar04,m_h move to arch/arm
|
||||
01d,20nov03,niq Remove copyright_wrs.h file inclusion
|
||||
01c,05nov03,rlm Ran batch header update for header re-org.
|
||||
01b,25jul02,rvr removed DCC specific code
|
||||
01a,13sep01,hsh Created from BSD 4.3
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACHINE_IN_CKSUM_H_
|
||||
#define _MACHINE_IN_CKSUM_H_ 1
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
/*
|
||||
* in_cksum_hdr - checksum on header only
|
||||
*
|
||||
* It is useful to have an Internet checksum routine which is inlineable
|
||||
* and optimized specifically for the task of computing IP header checksums
|
||||
* in the normal case (where there are no options and the header length is
|
||||
* therefore always exactly five 32-bit words.
|
||||
*/
|
||||
|
||||
static __inline
|
||||
u_int in_cksum_hdr
|
||||
(
|
||||
const struct ip *ip
|
||||
)
|
||||
{
|
||||
register u_int sum = 0;
|
||||
int hlen = sizeof (struct ip);
|
||||
register u_short *w = (u_short *) ip;
|
||||
u_short remaining = 0;
|
||||
|
||||
while (hlen > 1)
|
||||
{
|
||||
sum += *w++;
|
||||
hlen -= 2;
|
||||
}
|
||||
|
||||
if (hlen == 1)
|
||||
{
|
||||
*(u_char *) (&remaining) = *(u_char *) w;
|
||||
sum += remaining;
|
||||
}
|
||||
|
||||
sum = (sum & 0xffff) + (sum >> 16);
|
||||
if (sum > 0xffff)
|
||||
sum -= 0xffff;
|
||||
|
||||
return ~sum & 0xffff;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* in_cksum_update
|
||||
*/
|
||||
|
||||
static __inline
|
||||
void in_cksum_update
|
||||
(
|
||||
struct ip *ip
|
||||
)
|
||||
{
|
||||
int __tmpsum;
|
||||
__tmpsum = (int)ntohs(ip->ip_sum) + 256;
|
||||
ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16));
|
||||
}
|
||||
|
||||
/*
|
||||
* in_pseudo - pre-checksum parts of pseudo-header
|
||||
*
|
||||
* Compute significant parts of the IPv4 checksum pseudo-header * for use in a
|
||||
* delayed TCP/UDP checksum calculation.
|
||||
*
|
||||
* Args:
|
||||
*
|
||||
* src Source IP address
|
||||
* dst Destination IP address
|
||||
* lenproto htons(proto-hdr-len + proto-number)
|
||||
*/
|
||||
|
||||
static __inline
|
||||
u_int16_t in_pseudo
|
||||
(
|
||||
u_int32_t src,
|
||||
u_int32_t dst,
|
||||
u_int32_t lenproto
|
||||
)
|
||||
{
|
||||
u_int32_t sum;
|
||||
|
||||
sum = lenproto +
|
||||
(u_int16_t)(src >> 16) +
|
||||
(u_int16_t)(src /*& 0xffff*/) +
|
||||
(u_int16_t)(dst >> 16) +
|
||||
(u_int16_t)(dst /*& 0xffff*/);
|
||||
|
||||
sum = (u_int16_t)(sum >> 16) + (u_int16_t)(sum /*& 0xffff*/);
|
||||
|
||||
if (sum > 0xffff)
|
||||
sum -= 0xffff;
|
||||
|
||||
return (sum);
|
||||
}
|
||||
|
||||
/*
|
||||
* in_addword - Add two 16-bit workd
|
||||
*
|
||||
* Add the two 16-bit network-order values, carry, and return.
|
||||
*/
|
||||
|
||||
static __inline
|
||||
u_int16_t in_addword
|
||||
(
|
||||
u_int16_t a,
|
||||
u_int16_t b
|
||||
)
|
||||
{
|
||||
u_int32_t sum = a + b;
|
||||
|
||||
if (sum > 0xffff)
|
||||
sum -= 0xffff;
|
||||
|
||||
return (sum);
|
||||
}
|
||||
|
||||
|
||||
_WRS_FASTTEXT
|
||||
u_short in_cksum_skip(struct mbuf *m, int len, int skip);
|
||||
|
||||
#endif /* _MACHINE_IN_CKSUM_H_ */
|
||||
|
||||
@@ -0,0 +1,236 @@
|
||||
/* intArmLib.h - ARM-specific interrupt library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997-1998, 2003, 2007-2010, 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01l,07may12,jdw Add ARMARCH7M header include
|
||||
01j,03dec10,j_b add unified FIQ/IRQ handling support
|
||||
01i,23oct09,j_b fix _inline_intCpuMicroUnlock for gnu
|
||||
01h,18may09,j_b add _inline_intCpuMicroLock/Unlock support
|
||||
01h,25feb09,j_b merge ARM SMP support:
|
||||
21jun07,jb3 Convert to vxBus
|
||||
01g,16jun08,zl added memory clobber for GNUC version of inline routines.
|
||||
01f,20may08,j_b fix memory accesses outside lock in
|
||||
_inline_intCpuLock/Unlock for gnu (WIND00121559)
|
||||
01e,07aug07,jb3 Defect00095620 wrong gnu assembler instruction.
|
||||
01d,21jun07,zl updated inline build configuration.
|
||||
01c,22aug03,to added inline intLock()/intUnlock().
|
||||
01b,20aug98,cdp added intIFLock(), intIFUnlock().
|
||||
01a,25nov97,cdp created.
|
||||
*/
|
||||
|
||||
#ifndef __INCintArmLibh
|
||||
#define __INCintArmLibh
|
||||
|
||||
#if (CPU == ARMARCH7M)
|
||||
|
||||
#include <arch/arm/arm-m/intArmLib.h>
|
||||
|
||||
#else /* (CPU == ARMARCH7M) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* interrupt model feature selection bits (OR'd together) */
|
||||
|
||||
#define INT_NON_PREEMPT_MODEL 0
|
||||
#define INT_PREEMPT_MODEL 1
|
||||
#define INT_HDWE_LOCK_LVL 2
|
||||
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* inline intCpuLock()/intCpuUnlock() and intCpuMicroLock/Unlock() */
|
||||
|
||||
#if !(ARM_THUMB)
|
||||
#if defined (__DCC__)
|
||||
|
||||
__asm volatile int _inline_intCpuLock ()
|
||||
{
|
||||
! "r1" /* r1 clobbered */
|
||||
mrs r1, cpsr /* get current status */
|
||||
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
|
||||
and r0, r1, #0xC0 /* return current I & F in r0 */
|
||||
orr r1, r1, #0xC0 /* set I & F (1<<7 | 1<<6) */
|
||||
#else
|
||||
and r0, r1, #0x80 /* return current I_BIT in r0 */
|
||||
orr r1, r1, #0x80 /* set I_BIT (1<<7) */
|
||||
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
|
||||
msr cpsr, r1 /* set new status */
|
||||
}
|
||||
|
||||
__asm volatile void _inline_intCpuUnlock (int key)
|
||||
{
|
||||
% reg key; /* input: key in r0 */
|
||||
! "r0", "r1" /* r0, r1 clobbered */
|
||||
mrs r1, cpsr /* get current status */
|
||||
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
|
||||
bic r1, r1, #0xC0 /* clear I & F (1<<7 | 1<<6) */
|
||||
and r0, key, #0xC0 /* get passed I & F values */
|
||||
#else
|
||||
bic r1, r1, #0x80 /* clear I_BIT (1<<7) */
|
||||
and r0, key, #0x80 /* get passed I_BIT value */
|
||||
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
|
||||
orr r1, r1, r0 /* or in passed value */
|
||||
msr cpsr,r1 /* set new status */
|
||||
}
|
||||
|
||||
__asm volatile int _inline_intCpuMicroLock ()
|
||||
{
|
||||
! "r1" /* r1 clobbered */
|
||||
mrs r0, cpsr /* get, return current status */
|
||||
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
|
||||
orr r1, r0, #0xC0 /* set I & F (1<<7 | 1<<6) */
|
||||
#else
|
||||
orr r1, r0, #0x80 /* set I_BIT (1<<7) */
|
||||
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
|
||||
msr cpsr_c, r1 /* set new status */
|
||||
}
|
||||
|
||||
__asm volatile void _inline_intCpuMicroUnlock (int key)
|
||||
{
|
||||
% reg key; /* input: key in r0 */
|
||||
msr cpsr_c, key /* restore previous status */
|
||||
}
|
||||
|
||||
#elif defined (__GNUC__)
|
||||
|
||||
static __inline__ int _inline_intCpuLock (void)
|
||||
{
|
||||
int key;
|
||||
__asm__ volatile
|
||||
(
|
||||
"mrs r1, cpsr; " /* get current status */
|
||||
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
|
||||
"and %0, r1, #0xC0; " /* return current I & F */
|
||||
"orr r1, r1, #0xC0; " /* set I & F (1<<7 | 1<<6) */
|
||||
#else
|
||||
"and %0, r1, #0x80; " /* return current I_BIT */
|
||||
"orr r1, r1, #0x80; " /* set I_BIT (1<<7) */
|
||||
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
|
||||
"msr cpsr, r1 " /* set new status */
|
||||
: "=&r" (key) /* output: key is %0 */
|
||||
: /* no input */
|
||||
: "r1", "memory" /* r1 clobbered; memory */
|
||||
/* clobber for code barrier */
|
||||
);
|
||||
return key;
|
||||
}
|
||||
|
||||
static __inline__ void _inline_intCpuUnlock (int key)
|
||||
{
|
||||
__asm__ volatile
|
||||
(
|
||||
"mrs r1, cpsr; " /* get current status */
|
||||
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
|
||||
"bic r1, r1, #0xC0; " /* clear I & F (1<<7 | 1<<6) */
|
||||
"and r0, %0, #0xC0; " /* get passed I & F values */
|
||||
#else
|
||||
"bic r1, r1, #0x80; " /* clear I_BIT (1<<7) */
|
||||
"and r0, %0, #0x80; " /* get passed I_BIT value */
|
||||
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
|
||||
"orr r1, r1, r0; " /* or in passed I_BIT value */
|
||||
"msr cpsr, r1" /* set new status */
|
||||
: /* no output */
|
||||
: "r" (key) /* input: key is %0 */
|
||||
: "r0", "r1", "memory" /* r0, r1 clobbered; memory */
|
||||
/* clobber for code barrier */
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ int _inline_intCpuMicroLock (void)
|
||||
{
|
||||
int key;
|
||||
__asm__ volatile
|
||||
(
|
||||
"mrs %0, cpsr; " /* get, return current status */
|
||||
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
|
||||
"orr r1, %0, #0xC0; " /* set I & F (1<<7 | 1<<6) */
|
||||
#else
|
||||
"orr r1, %0, #0x80; " /* set I_BIT (1<<7) */
|
||||
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
|
||||
"msr cpsr_c, r1 " /* set new status */
|
||||
: "=&r" (key) /* output: key is %0 */
|
||||
: /* no input */
|
||||
: "r1", "memory" /* r1 clobbered; memory */
|
||||
/* clobber for code barrier */
|
||||
);
|
||||
return key;
|
||||
}
|
||||
|
||||
static __inline__ void _inline_intCpuMicroUnlock (int key)
|
||||
{
|
||||
__asm__ volatile
|
||||
(
|
||||
"msr cpsr_c, %0" /* restore previous status */
|
||||
: /* no output */
|
||||
: "r" (key) /* input: key is %0 */
|
||||
/* no regs, memory clobbered */
|
||||
);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define _inline_intCpuLock() intCpuLock()
|
||||
#define _inline_intCpuUnlock(key) intCpuUnlock(key)
|
||||
|
||||
#define _inline_intCpuMicroLock() intCpuMicroLock()
|
||||
#define _inline_intCpuMicroUnlock(key) intCpuMicroUnlock(key)
|
||||
|
||||
#endif /* __DCC__ */
|
||||
#endif /* !ARM_THUMB */
|
||||
|
||||
|
||||
/* functions in intArchLib.c and intALib.s */
|
||||
|
||||
extern STATUS intDisable (int);
|
||||
extern STATUS intEnable (int);
|
||||
extern STATUS intLibInit (int, int, int);
|
||||
extern int intIFLock (void);
|
||||
extern void intIFUnlock (int);
|
||||
|
||||
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
|
||||
extern int intILock (void);
|
||||
extern void intIUnlock (int);
|
||||
extern int intFLock (void);
|
||||
extern void intFUnlock (int);
|
||||
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
|
||||
|
||||
|
||||
/*
|
||||
* Function pointers used in intArchLib.c and interrupt driver
|
||||
*/
|
||||
IMPORT FUNCPTR sysIntLvlVecChkRtn;
|
||||
IMPORT FUNCPTR sysIntLvlVecAckRtn;
|
||||
IMPORT FUNCPTR sysIntLvlChgRtn;
|
||||
IMPORT FUNCPTR sysIntLvlEnableRtn;
|
||||
IMPORT FUNCPTR sysIntLvlDisableRtn;
|
||||
|
||||
/*
|
||||
* vxBus function pointers used in intArchLib.c and interrupt driver
|
||||
*/
|
||||
IMPORT FUNCPTR _func_IntLvlVecChkRtn;
|
||||
IMPORT FUNCPTR _func_IntLvlVecAckRtn;
|
||||
IMPORT FUNCPTR _func_IntLvlChgRtn;
|
||||
IMPORT FUNCPTR _func_IntLvlEnableRtn;
|
||||
IMPORT void * intCtlrDevID;
|
||||
IMPORT FUNCPTR _func_IntLvlDisableRtn;
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* (CPU == ARMARCH7M) */
|
||||
|
||||
#endif /* __INCintArmLibh */
|
||||
@@ -0,0 +1,32 @@
|
||||
/* ivArm.h - ARM interrupt vectors */
|
||||
|
||||
/* Copyright 1996-1997 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,09may96,cdp created
|
||||
*/
|
||||
|
||||
#ifndef __INCivArmh
|
||||
#define __INCivArmh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* macros to convert interrupt vectors <-> interrupt numbers */
|
||||
|
||||
#define IVEC_TO_INUM(intVec) ((int) (intVec))
|
||||
#define INUM_TO_IVEC(intNum) ((VOIDFUNCPTR *) (intNum))
|
||||
|
||||
|
||||
/* interrupt vector definitions are in the BSP header files */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCivArmh */
|
||||
@@ -0,0 +1,117 @@
|
||||
/* mmuArm1136jfLib.h - ARM 1136JF MMU library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2004, 2010-2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,20dec11,jdw Add missing APIs to clear up warnings related to ttbr APIs
|
||||
01c,29apr10,pad Moved extern C statement after include statements.
|
||||
01b,09feb10,j_b update mmuArm1136jfTtbrSet for ASID support
|
||||
01a,07dec04,jb created
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuArm1136jfLibh
|
||||
#define __INCmmuArm1136jfLibh
|
||||
|
||||
#include "memLib.h"
|
||||
|
||||
#define MMU_ID_ARM1136JF 0x07B360
|
||||
|
||||
#include "mmuArmArch6PalLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* 1136JF Specific definitions follow */
|
||||
|
||||
/*
|
||||
* Values to be used when mmuEnable() is called. This will be after the MMU has
|
||||
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
|
||||
* cache enable settings have been chosen.
|
||||
*
|
||||
* M 1 Enable MMU
|
||||
* A 0 Disable address alignment fault
|
||||
* C X ((D-)Cache Enable) Controlled by cacheLib
|
||||
* W X (Write Buffer) Controlled by cacheLib
|
||||
* P 1 (PROG32) should be set before this
|
||||
* D 1 (DATA32) should be set before this
|
||||
* L 1 (Late abort on earlier CPUs) ignore
|
||||
* B X (Big/Little-endian) should be set before this
|
||||
* S 1 (System)
|
||||
* R 0 (ROM)
|
||||
* F 0 Should be Zero
|
||||
* Z X (Branch prediction enable on 810) Controlled by cacheLib
|
||||
* I X (I-cache enable) Controlled by cacheLib
|
||||
*
|
||||
* For time being, do not enable the address alignment fault, as GCC
|
||||
* currently generates unaligned accesses in its code, and switching this
|
||||
* on will cause immediate faults. So, do not put it into the enable
|
||||
* mask.
|
||||
*
|
||||
* We used to clear all the Reserved/Should Be Zero bits when the
|
||||
* MMU/MPU was enabled, by including one bits for them in the definition
|
||||
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
|
||||
* the definitions of the bits within the MMU Control Register. The MMU
|
||||
* Control register is initialised within romInit()/sysInit(), as the BSP
|
||||
* is the only place where the particular details of the CPU/MMU are
|
||||
* actually known. In general, it will be appropriate for the BSP to
|
||||
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
|
||||
* MMU is enabled, we will only change the bits we are particularly
|
||||
* concerned about, by using a Read-Modify-Write strategy.
|
||||
*/
|
||||
|
||||
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
|
||||
|
||||
#define MMUCR_MODE 0 /* This is specific to ARMARCH6 */
|
||||
|
||||
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_EXTENDED_PAGE)
|
||||
|
||||
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE | MMUCR_EXTENDED_PAGE)
|
||||
|
||||
#define MMU_MUST_SET_VALUE ( MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_W_ENABLE )
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
#define MMU_INIT_VALUE ( MMU_MUST_SET_VALUE | MMUCR_MODE)
|
||||
#else
|
||||
#define MMU_INIT_VALUE ( MMU_MUST_SET_VALUE | MMUCR_BIGEND | MMUCR_MODE)
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void mmuArm1136jfLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
IMPORT void mmuArm1136jfTtbrSet (MMU_LEVEL_1_DESC *pTable, UINT32 asid);
|
||||
IMPORT MMU_LEVEL_1_DESC * mmuArm1136jfTtbrGet (void);
|
||||
IMPORT void mmuArm1136jfTtbrSetAll (UINT32 ttbr, UINT32 asid);
|
||||
IMPORT UINT32 mmuArm1136jfTtbrGetAll (void);
|
||||
IMPORT void mmuArm1136jfDacrSet (UINT32 dacrVal);
|
||||
IMPORT void mmuArm1136jfTLBIDFlushEntry (VIRT_ADDR *addr);
|
||||
IMPORT void mmuArm1136jfTLBIDFlushAll (void);
|
||||
IMPORT void mmuArm1136jfAEnable (UINT32 cacheState);
|
||||
IMPORT void mmuArm1136jfADisable (void);
|
||||
IMPORT STATUS mmuArm1136jfPBitSet (VIRT_ADDR virtAddr, UINT32 size);
|
||||
IMPORT STATUS mmuArm1136jfPBitClear (VIRT_ADDR virtAddr, UINT32 size);
|
||||
IMPORT STATUS mmuArm1136jfPBitGet (VIRT_ADDR virtAddr );
|
||||
IMPORT STATUS mmuArm1136jfAcrGet (void );
|
||||
IMPORT void mmuArm1136jfAcrSet (UINT32 acrVal);
|
||||
IMPORT STATUS mmuArm1136jfITcmrGet (void );
|
||||
IMPORT void mmuArm1136jfITcmrSet (UINT32 acrVal);
|
||||
IMPORT STATUS mmuArm1136jfDTcmrGet (void );
|
||||
IMPORT void mmuArm1136jfDTcmrSet (UINT32 acrVal);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmmuArm1136jfLibh */
|
||||
@@ -0,0 +1,139 @@
|
||||
/* mmuArm11MPCoreLib.h - ARM 11MPCORE MMU library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007, 2010-2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,20dec11,jdw Add missing APIs to clear up warnings related to ttbr APIs
|
||||
01c,29apr10,pad Moved extern C statement after include statements.
|
||||
01b,09feb10,j_b update mmuArm11MPCoreTtbrSet for ASID support
|
||||
01a,09jul07,j_b Written
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuArm11MPCoreLibh
|
||||
#define __INCmmuArm11MPCoreLibh
|
||||
|
||||
#include "memLib.h"
|
||||
|
||||
#define MMU_ID_ARM11MPCORE 0x0FB024 /* from CP15 ID Code Register c0 */
|
||||
|
||||
#include "mmuArmArch6PalLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* 11MPCORE Specific definitions follow */
|
||||
|
||||
/*
|
||||
* Values to be used when mmuEnable() is called. This will be after the MMU has
|
||||
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
|
||||
* cache enable settings have been chosen.
|
||||
*
|
||||
* M 1 Enable MMU
|
||||
* A 0 Disable address alignment fault
|
||||
* C X ((D-)Cache Enable) Controlled by cacheLib
|
||||
* W 1 (Write Buffer - obsolete) Should be One
|
||||
* P 1 (PROG32 - obsolete) Should be One
|
||||
* D 1 (DATA32 - obsolete) Should be One
|
||||
* L 1 (Late abort - obsolete) Should be One
|
||||
* B 0 (Big/Little-endian - unsupported) Should be Zero
|
||||
* S 0 (System protection - deprecated)
|
||||
* R 0 (ROM protection - deprecated)
|
||||
* F 0 Should be Zero
|
||||
* Z X (Branch prediction) Controlled by cacheLib
|
||||
* I X (I-cache enable) Controlled by cacheLib
|
||||
* V 0 (Vector table location: Normal/High Address)
|
||||
* RR 1 (Random/Round-Robin cache replacement - unsupported) Should be One
|
||||
* L4 0 Load instructions to PC set T bit
|
||||
* DT 1 (Data TCM enable - obsolete) Write has no effect; Read as One
|
||||
* - 0 Should be Zero
|
||||
* IT 1 (Instruction TCM enable - unsupported) Write has no effect; Read as One
|
||||
* - 0 Should be Zero
|
||||
* - 0 Should be Zero
|
||||
* FI 0 (Fast Interrupt enable - obsolete) Should be Zero
|
||||
* U 0 Disable Unaligned data access enable
|
||||
* XP 1 Enable eXtended Page table configuration (disable subpage AP bits)
|
||||
* VE 0 (VEctored Interrupt- unsupported) Should be Zero
|
||||
* EE 0 E bit of CPSR upon Exception
|
||||
* - 0 Should be Zero
|
||||
* NM 0 Disable NMFI behavior for FIQs
|
||||
* TR 0 Disable TEX Remapping
|
||||
* FA 0 Disable Force AP[0] as access bit
|
||||
* - 0 Should be Zero
|
||||
* - 0 Should be Zero
|
||||
*
|
||||
* NOTE: All defined control register bits are set to 0 on Reset, except
|
||||
* V, U and EE which are dependent on system configuration pin signal levels.
|
||||
*
|
||||
* For time being, do not enable the address alignment fault, as GCC
|
||||
* currently generates unaligned accesses in its code, and switching this
|
||||
* on will cause immediate faults. So, do not put it into the enable
|
||||
* mask.
|
||||
*
|
||||
* We used to clear all the Reserved/Should Be Zero bits when the
|
||||
* MMU/MPU was enabled, by including one bits for them in the definition
|
||||
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
|
||||
* the definitions of the bits within the MMU Control Register. The MMU
|
||||
* Control register is initialised within romInit()/sysInit(), as the BSP
|
||||
* is the only place where the particular details of the CPU/MMU are
|
||||
* actually known. In general, it will be appropriate for the BSP to
|
||||
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
|
||||
* MMU is enabled, we will only change the bits we are particularly
|
||||
* concerned about, by using a Read-Modify-Write strategy.
|
||||
*/
|
||||
|
||||
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
|
||||
|
||||
#define MMUCR_MODE 0 /* This is specific to ARMARCH6 */
|
||||
|
||||
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_EXTENDED_PAGE)
|
||||
|
||||
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE | MMUCR_EXTENDED_PAGE)
|
||||
|
||||
#define MMU_MUST_SET_VALUE ( MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_W_ENABLE )
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
#define MMU_INIT_VALUE ( MMU_MUST_SET_VALUE | MMUCR_MODE)
|
||||
#else
|
||||
#define MMU_INIT_VALUE ( MMU_MUST_SET_VALUE | MMUCR_BIGEND | MMUCR_MODE)
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void mmuArm11MPCoreLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
IMPORT void mmuArm11MPCoreTtbrSet (MMU_LEVEL_1_DESC *pTable, UINT32 asid);
|
||||
IMPORT MMU_LEVEL_1_DESC * mmuArm11MPCoreTtbrGet (void);
|
||||
IMPORT void mmuArm11MPCoreTtbrSetAll (UINT32 ttbr, UINT32 asid);
|
||||
IMPORT UINT32 mmuArm11MPCoreTtbrGetAll (void);
|
||||
IMPORT void mmuArm11MPCoreDacrSet (UINT32 dacrVal);
|
||||
IMPORT void mmuArm11MPCoreTLBIDFlushEntry (VIRT_ADDR *addr);
|
||||
IMPORT void mmuArm11MPCoreTLBIDFlushAll (void);
|
||||
IMPORT void mmuArm11MPCoreAEnable (UINT32 cacheState);
|
||||
IMPORT void mmuArm11MPCoreADisable (void);
|
||||
IMPORT STATUS mmuArm11MPCorePBitSet (VIRT_ADDR virtAddr, UINT32 size);
|
||||
IMPORT STATUS mmuArm11MPCorePBitClear (VIRT_ADDR virtAddr, UINT32 size);
|
||||
IMPORT STATUS mmuArm11MPCorePBitGet (VIRT_ADDR virtAddr);
|
||||
IMPORT STATUS mmuArm11MPCoreAcrGet (void);
|
||||
IMPORT void mmuArm11MPCoreAcrSet (UINT32 acrVal);
|
||||
IMPORT STATUS mmuArm11MPCoreITcmrGet (void);
|
||||
IMPORT void mmuArm11MPCoreITcmrSet (UINT32 acrVal);
|
||||
IMPORT STATUS mmuArm11MPCoreDTcmrGet (void);
|
||||
IMPORT void mmuArm11MPCoreDTcmrSet (UINT32 acrVal);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmmuArm11MPCoreLibh */
|
||||
@@ -0,0 +1,38 @@
|
||||
/* mmuArm710aLib.h - ARM 710a MMU library header file */
|
||||
|
||||
/* Copyright 1998-2005 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01b,20jan99,cdp removed support for old ARM libraries.
|
||||
01a,24nov98,cdp created.
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuArm710aLibh
|
||||
#define __INCmmuArm710aLibh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void mmuArm710aLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
IMPORT void mmuArm710aTtbrSet (LEVEL_1_DESC *);
|
||||
IMPORT void mmuArm710aDacrSet (UINT32 dacrVal);
|
||||
IMPORT void mmuArm710aTLBIDFlushEntry (void *addr);
|
||||
IMPORT void mmuArm710aTLBIDFlushAll (void);
|
||||
IMPORT void mmuArm710aAEnable (UINT32 cacheState);
|
||||
IMPORT void mmuArm710aADisable (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmmuArm710aLibh */
|
||||
@@ -0,0 +1,130 @@
|
||||
/* mmuArm920tLib.h - ARM 920T MMU library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1999, 2004, 2005, 2007, 2010-2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01g,21dec11,jdw Update APIs to clear up warnings related to ttbr APIs
|
||||
01f,29apr10,pad Moved extern C statement after include statements.
|
||||
01e,25jan07,j_b add mmuArm920tTtbrGet prototype
|
||||
01d,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01c,10feb05,jb Reverting to ROM mode for shared data/libraries
|
||||
01b,09dec04,jb Palify Arm MMU
|
||||
01a,04feb99,jpd created.
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuArm920tLibh
|
||||
#define __INCmmuArm920tLibh
|
||||
|
||||
#define MMU_ID_ARM920T 0x029200
|
||||
|
||||
#include "mmuArmPalLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Values to be used when mmuEnable() is called. This will be after the MMU has
|
||||
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
|
||||
* cache enable settings have been chosen.
|
||||
*
|
||||
* M 1 Enable MMU
|
||||
* A 0 Disable address alignment fault
|
||||
* C X ((D-)Cache Enable) Controlled by cacheLib
|
||||
* W X (Write Buffer) Controlled by cacheLib
|
||||
* P 1 (PROG32) should be set before this
|
||||
* D 1 (DATA32) should be set before this
|
||||
* L 1 (Late abort on earlier CPUs) ignore
|
||||
* B X (Big/Little-endian) should be set before this
|
||||
* S 1 (System)
|
||||
* R 0 (ROM)
|
||||
* F 0 Should be Zero
|
||||
* Z X (Branch prediction enable on 810) Controlled by cacheLib
|
||||
* I X (I-cache enable) Controlled by cacheLib
|
||||
*
|
||||
* For time being, do not enable the address alignment fault, as GCC
|
||||
* currently generates unaligned accesses in its code, and switching this
|
||||
* on will cause immediate faults. So, do not put it into the enable
|
||||
* mask.
|
||||
*
|
||||
* We used to clear all the Reserved/Should Be Zero bits when the
|
||||
* MMU/MPU was enabled, by including one bits for them in the definition
|
||||
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
|
||||
* the definitions of the bits within the MMU Control Register. The MMU
|
||||
* Control register is initialised within romInit()/sysInit(), as the BSP
|
||||
* is the only place where the particular details of the CPU/MMU are
|
||||
* actually known. In general, it will be appropriate for the BSP to
|
||||
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
|
||||
* MMU is enabled, we will only change the bits we are particularly
|
||||
* concerned about, by using a Read-Modify-Write strategy.
|
||||
*/
|
||||
|
||||
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
|
||||
|
||||
#define MMUCR_MODE MMUCR_ROM /* This MUST remain ROM for shared libraries */
|
||||
|
||||
#define MMUCR_FB_DISABLE (1<<30) /* nFastBus bit */
|
||||
#define MMUCR_ASYNC_BIT (1<<31) /* Async bit*/
|
||||
#define MMUCR_SYNC (1<<30) /* Synchronous mode */
|
||||
#define MMUCR_ASYNC (3<<30) /* Asynchronous mode */
|
||||
|
||||
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
|
||||
|
||||
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE)
|
||||
|
||||
/*
|
||||
* Values to be used when the MMU Control Register is initialised from
|
||||
* within romInit.s or sysALib.s (before the MMU is enabled). Note that
|
||||
* on 710A, this is also used to initialise the soft-copy of the MMU CR
|
||||
* that we need to keep (in order to emulate Read-Modify-Write
|
||||
* operations). So, the BSP *MUST* initialise the MMU CR with the value
|
||||
* contained here, or else trouble will ensue. This restriction does
|
||||
* not apply to non-710A BSPs, but caution must be exercised in choosing a
|
||||
* value different to that defined here.
|
||||
*/
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
|
||||
/* W bit is Should Be One */
|
||||
|
||||
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_MODE | MMUCR_W_ENABLE)
|
||||
|
||||
#else /* _BYTE_ORDER == _LITTLE_ENDIAN now _BIG_ENDIAN */
|
||||
|
||||
/* big endian */
|
||||
|
||||
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_W_ENABLE | MMUCR_BIGEND | MMUCR_MODE)
|
||||
|
||||
#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void mmuArm920tLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
IMPORT MMU_LEVEL_1_DESC * mmuArm920tTtbrGet (void);
|
||||
IMPORT void mmuArm920tTtbrSet (MMU_LEVEL_1_DESC *);
|
||||
IMPORT UINT32 mmuArm920tTtbrGetAll (void);
|
||||
IMPORT void mmuArm920tTtbrSetAll (UINT32);
|
||||
IMPORT void mmuArm920tDacrSet (UINT32 dacrVal);
|
||||
IMPORT void mmuArm920tTLBIDFlushEntry (void *addr);
|
||||
IMPORT void mmuArm920tTLBIDFlushAll (void);
|
||||
IMPORT void mmuArm920tAEnable (UINT32 cacheState);
|
||||
IMPORT void mmuArm920tADisable (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmmuArm920tLibh */
|
||||
@@ -0,0 +1,129 @@
|
||||
/* mmuArm926eLib.h - ARM 926E MMU library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002, 2004, 2005, 2007, 2010-2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01h,21dec11,jdw Update APIs to clear up warnings related to ttbr APIs
|
||||
01g,29apr10,pad Moved extern C statement after include statements.
|
||||
01f,15oct07,j_b fix MMU_INIT_VALUE (WIND00060071)
|
||||
01e,18apr05,jb Fix for SPR 108034
|
||||
01d,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01c,10feb05,jb Reverting to ROM mode for shared data/libraries
|
||||
01b,09dec04,jb Palify Arm MMU
|
||||
01a,09dec02,jpd created, based on mmuArm920tLib.h, version 01a.
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuArm926eLibh
|
||||
#define __INCmmuArm926eLibh
|
||||
|
||||
#define MMU_ID_ARM926E 0x069260
|
||||
|
||||
#include "mmuArmPalLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Values to be used when mmuEnable() is called. This will be after the MMU has
|
||||
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
|
||||
* cache enable settings have been chosen.
|
||||
*
|
||||
* M 1 Enable MMU
|
||||
* A 0 Disable address alignment fault
|
||||
* C X ((D-)Cache Enable) Controlled by cacheLib
|
||||
* W X (Write Buffer) Controlled by cacheLib
|
||||
* P 1 (PROG32) should be set before this
|
||||
* D 1 (DATA32) should be set before this
|
||||
* L 1 (Late abort on earlier CPUs) ignore
|
||||
* B X (Big/Little-endian) should be set before this
|
||||
* S 1 (System)
|
||||
* R 0 (ROM)
|
||||
* F 0 Should be Zero
|
||||
* Z X (Branch prediction enable on 810) Controlled by cacheLib
|
||||
* I X (I-cache enable) Controlled by cacheLib
|
||||
*
|
||||
* For time being, do not enable the address alignment fault, as GCC
|
||||
* currently generates unaligned accesses in its code, and switching this
|
||||
* on will cause immediate faults. So, do not put it into the enable
|
||||
* mask.
|
||||
*
|
||||
* We used to clear all the Reserved/Should Be Zero bits when the
|
||||
* MMU/MPU was enabled, by including one bits for them in the definition
|
||||
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
|
||||
* the definitions of the bits within the MMU Control Register. The MMU
|
||||
* Control register is initialised within romInit()/sysInit(), as the BSP
|
||||
* is the only place where the particular details of the CPU/MMU are
|
||||
* actually known. In general, it will be appropriate for the BSP to
|
||||
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
|
||||
* MMU is enabled, we will only change the bits we are particularly
|
||||
* concerned about, by using a Read-Modify-Write strategy.
|
||||
*/
|
||||
|
||||
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
|
||||
|
||||
#define MMUCR_MODE MMUCR_ROM /* This MUST remain ROM for shared libraries */
|
||||
|
||||
#define MMUCR_L4_ENABLE (1<<15) /* L4 enable, ARMv4 behavior */
|
||||
|
||||
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
|
||||
|
||||
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE)
|
||||
|
||||
#define MMUCR_926E_SBO ((1<<18) | (1<<16)) /* Should Be One bits */
|
||||
|
||||
/*
|
||||
* Values to be used when the MMU Control Register is initialised from
|
||||
* within romInit.s or sysALib.s (before the MMU is enabled). Note that
|
||||
* on 710A, this is also used to initialise the soft-copy of the MMU CR
|
||||
* that we need to keep (in order to emulate Read-Modify-Write
|
||||
* operations). So, the BSP *MUST* initialise the MMU CR with the value
|
||||
* contained here, or else trouble will ensue. This restriction does
|
||||
* not apply to non-710A BSPs, but caution must be exercised in choosing a
|
||||
* value different to that defined here.
|
||||
*/
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
|
||||
/* W bit is Should Be One */
|
||||
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_MODE | MMUCR_926E_SBO)
|
||||
|
||||
#else /* _BYTE_ORDER == _LITTLE_ENDIAN now _BIG_ENDIAN */
|
||||
|
||||
/* big endian */
|
||||
|
||||
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_BIGEND | MMUCR_MODE | MMUCR_926E_SBO)
|
||||
|
||||
#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void mmuArm926eLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
IMPORT MMU_LEVEL_1_DESC * mmuArm926eTtbrGet ( void);
|
||||
IMPORT void mmuArm926eTtbrSet (MMU_LEVEL_1_DESC *);
|
||||
IMPORT UINT32 mmuArm926eTtbrGetAll (void);
|
||||
IMPORT void mmuArm926eTtbrSetAll (UINT32);
|
||||
IMPORT void mmuArm926eDacrSet (UINT32 dacrVal);
|
||||
IMPORT void mmuArm926eTLBIDFlushEntry (void *addr);
|
||||
IMPORT void mmuArm926eTLBIDFlushAll (void);
|
||||
IMPORT void mmuArm926eAEnable (UINT32 cacheState);
|
||||
IMPORT void mmuArm926eADisable (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmmuArm926eLibh */
|
||||
@@ -0,0 +1,900 @@
|
||||
/* mmuArmArch6PalLib.h - ARM MMU library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2005-2014, 2016 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
20jan16,jnl Clean warning.
|
||||
17apr14,c_l Fix TTBR & PTE attribute macros for enabled
|
||||
ENABLE_CACHED_PAGE_TBL. (VXW6-73478)
|
||||
02p,18sep13,zgl Add TTBR & PTE attribute macros for ARM A15 (WIND00434990)
|
||||
02o,11jun12,jdw Fix TTBR & PTE attribute macros for ARM A9,
|
||||
WIND00342202, WIND00342756
|
||||
02n,02mar12,rec WIND00318272 - POSIX signals conformance
|
||||
02m,09jan12,rec WIND00196578 - remove unused reference _func_armPageSource
|
||||
02l,28sep11,jdw Add shared attribute to cached page tables (WIND00298486)
|
||||
02k,13may11,jdw Clear TTBR0 bits during MMU init (WIND00258897)
|
||||
02j,20apr11,jdw Add support for cached page tables
|
||||
02i,25aug10,my_ add MMUCR_EE bit definition (WIND00229795)
|
||||
02h,17jun10,m_h Thumb-2 Support
|
||||
02g,29apr10,pad Moved extern C statement after include statements.
|
||||
02f,02feb10,j_b add not-global PTE bit (nG), ASID support
|
||||
02e,03nov09,j_b add INCLUDE_MMU_TEX_SUPPORT, undef INCLUDE_MMU_SUBPAGE_SUPPORT
|
||||
02d,02nov09,j_b fix translation bug due to XN bit support (WIND00189001)
|
||||
02c,07feb08,j_b Change MMU_DEF_L1_PAGE so bit 4 is 0 per VMSAv6
|
||||
02b,23oct07,to added lockCnt and lockOwner to MMU_TRANS_TBL
|
||||
02a,21sep07,to define MMU_PAGE_SIZE_SHIFT
|
||||
01z,21sep07,j_b add _func_mmuFaultAddrGet prototype
|
||||
01y,08aug07,j_b modify MMU_STATE_MASK_CACHEABLE for ARMv6 extended types;
|
||||
add INCLUDE_MMU_EXTD_TYPE_SUPPORT
|
||||
01x,30jul07,j_b fix special purpose attributes' masks
|
||||
01w,03jul07,j_b add special purpose attributes for added ARMv6 extended types
|
||||
(w/ TEX)
|
||||
01v,20sep06,j_b add page optimization support
|
||||
01u,11sep06,m_h fix vert-to-phys translation problem in upper bits
|
||||
WIND00059266
|
||||
01t,01mar06,m_h Manzano supersection support
|
||||
01s,30mar05,jb Extracted from mmuArmArch6PalLib.h, 01u
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuArmArch6PalLibh
|
||||
#define __INCmmuArmArch6PalLibh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <memLib.h>
|
||||
#include <semLib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/*
|
||||
* The page size we will use. Ignore the sub-page, Large Page and Tiny
|
||||
* Page features.
|
||||
*/
|
||||
|
||||
#define MMU_PAGE_SIZE 4096
|
||||
#define MMU_PAGE_SIZE_SHIFT 12
|
||||
|
||||
/*
|
||||
* See the Virtual Memory System Architecture for ARMv6 (VMSAv6) section
|
||||
* in the ARM Architecture Reference Manual (ARM DDI 0100) for MMU details.
|
||||
*/
|
||||
|
||||
#define PAGE_SIZE MMU_PAGE_SIZE
|
||||
|
||||
#undef INCLUDE_MMU_APXBIT_SUPPORT
|
||||
#define INCLUDE_MMU_APXBIT_SUPPORT
|
||||
|
||||
#undef INCLUDE_MMU_XNBIT_SUPPORT
|
||||
#define INCLUDE_MMU_XNBIT_SUPPORT
|
||||
|
||||
#undef INCLUDE_MMU_EXTD_TYPE_SUPPORT
|
||||
#define INCLUDE_MMU_EXTD_TYPE_SUPPORT
|
||||
|
||||
#undef INCLUDE_MMU_SBIT_SUPPORT
|
||||
#define INCLUDE_MMU_SBIT_SUPPORT
|
||||
|
||||
#undef INCLUDE_MMU_TEX_SUPPORT
|
||||
#define INCLUDE_MMU_TEX_SUPPORT
|
||||
|
||||
#undef INCLUDE_MMU_SUBPAGE_SUPPORT
|
||||
|
||||
/*
|
||||
* The amount described by a Level 1 Descriptor, which equals the smallest
|
||||
* amount of VM allocatable in VxWorks.
|
||||
*/
|
||||
|
||||
#define MMU_PAGE_BLOCK_SIZE 0x100000 /* 1 MByte */
|
||||
|
||||
#define MMU_ADRS_TO_L1D_INDEX_SHIFT 20
|
||||
|
||||
#define MMU_PTE_INDEX_MASK 0x000FF000 /* extract PTE index from Virt Addr */
|
||||
#define MMU_PTE_INDEX_SHIFT 12 /* shift to make that into PTE index */
|
||||
|
||||
#define MMU_L1D_TO_BASE_SHIFT 10 /* to turn L1D to PT base addr */
|
||||
#define MMU_L1DSECTION_TO_BASE_SHIFT 20 /* L1D section to PT base addr */
|
||||
#define MMU_L1DSECTION_BA_MASK 0xFFF00000 /* phys bits 20-31 */
|
||||
|
||||
#define MMU_L1DSSECTIONLO_TO_BASE_SHIFT 24 /* bits 24-31 of supersection */
|
||||
#define MMU_L1DSSECTIONHI_TO_BASE_SHIFT 32 /* bits 32-35 of supersection */
|
||||
#define MMU_L1DSSECTIONHI2_TO_BASE_SHIFT 5 /* bits 36-39 of supersection */
|
||||
#define MMU_L1DSSECTIONLO_BA_MASK 0xFF000000 /* phys bits 24-31 */
|
||||
#define MMU_L1DSSECTIONHI_BA_MASK 0x00F00000 /* phys bits 32-35 */
|
||||
#define MMU_L1DSSECTIONHI2_BA_MASK 0x000001E0 /* phys bits 36-39 */
|
||||
|
||||
/* optional extended physical address bit fields */
|
||||
|
||||
#define MMU_L1DSSECTION_EXTD_BA_MASK \
|
||||
(MMU_L1DSSECTIONHI_BA_MASK | MMU_L1DSSECTIONHI2_BA_MASK)
|
||||
|
||||
/* supersection base address packing */
|
||||
|
||||
#define MMU_L1DSSECTION_BA_SET(physAddr, L1desc) \
|
||||
(L1desc = (unsigned int)((L1desc & ~MMU_L1DSSECTION_EXTD_BA_MASK) | \
|
||||
( (((unsigned long long)(physAddr)) & MMU_L1DSSECTIONLO_BA_MASK) | \
|
||||
((((unsigned long long)(physAddr)) >> 12) & \
|
||||
MMU_L1DSSECTIONHI_BA_MASK) | \
|
||||
((((unsigned long long)(physAddr)) >> 31) & \
|
||||
MMU_L1DSSECTIONHI2_BA_MASK) )))
|
||||
|
||||
/* supersection base address unpacking */
|
||||
|
||||
#define MMU_L1DSSECTION_BA_GET(ssectDesc) \
|
||||
((unsigned long long) \
|
||||
( (unsigned long long)(ssectDesc & MMU_L1DSSECTIONLO_BA_MASK) | \
|
||||
((unsigned long long)(ssectDesc & MMU_L1DSSECTIONHI_BA_MASK) \
|
||||
<< 12) | \
|
||||
((unsigned long long)(ssectDesc & MMU_L1DSSECTIONHI2_BA_MASK) \
|
||||
<< 31) ))
|
||||
|
||||
/* Address translation masks */
|
||||
|
||||
#define MMU_ADDR_PI_MASK 0x00000FFF /* extract page index from Virt Addr */
|
||||
#define MMU_PTE_BA_MASK 0xFFFFF000 /* extract phys base address from PTE */
|
||||
#define MMU_ADDR_SI_MASK 0x000FFFFF /* extr section index from Virt Addr */
|
||||
#define MMU_PTE_SECA_MASK 0xFFF00000 /* extract section base from L1 desc */
|
||||
|
||||
#define MMU_ADDR_SSI_MASK 0x00FFFFFF /* supersection index from virt */
|
||||
#define MMU_PTE_SSECA_MASK 0xFF000000 /* supersection base from L1 desc */
|
||||
#define MMU_PTE_SSECAX_MASK 0x00F00000 /* supersection extended bits L1 */
|
||||
#define MMU_PTE_SSECAX_SHIFT 12 /* supersection extended bits shift */
|
||||
|
||||
/* Level 1 descriptor bit fields */
|
||||
|
||||
#define MMU_L1PD_TYPE_MASK 0x00000003 /* type bits [0:1] */
|
||||
#define MMU_L1PD_CB_MASK 0x0000000C /* CB bits [3:2] */
|
||||
#define MMU_L1PD_XN_MASK 0x00000010 /* eXecute Never bit [4] */
|
||||
#define MMU_L1PD_DOMAIN_MASK 0x000001E0 /* domain bits [8:5] */
|
||||
#define MMU_L1PD_P_MASK 0x00000200 /* P bit [9] */
|
||||
#define MMU_L1PD_AP_MASK 0x00000C00 /* AP bits [10:11] */
|
||||
#define MMU_L1PD_TEX_MASK 0x00007000 /* TEX bits [14:12] */
|
||||
#define MMU_L1PD_APX_MASK 0x00008000 /* APX bit [15] */
|
||||
#define MMU_L1PD_S_MASK 0x00010000 /* Shared bit [16] */
|
||||
#define MMU_L1PD_NG_MASK 0x00020000 /* not-Global bit [17] */
|
||||
#define MMU_L1PD_PTE_MASK 0xFFFFFC00 /* extract phys L2 PTE addr from L1PD */
|
||||
|
||||
/* # of shifts (right) to get fields in Level 1 descriptor */
|
||||
|
||||
#define MMU_L1PD_CB_SHIFT 2
|
||||
#define MMU_L1PD_XN_SHIFT 4
|
||||
#define MMU_L1PD_DOMAIN_SHIFT 5
|
||||
#define MMU_L1PD_P_SHIFT 9
|
||||
#define MMU_L1PD_AP_SHIFT 10
|
||||
#define MMU_L1PD_TEX_SHIFT 12
|
||||
#define MMU_L1PD_APX_SHIFT 15
|
||||
#define MMU_L1PD_S_SHIFT 16
|
||||
#define MMU_L1PD_NG_SHIFT 17
|
||||
|
||||
/* Level 2 descriptor bit fields */
|
||||
|
||||
#define MMU_PTE_TYPE_MASK 0x00000003 /* PTE type bits [0:1] */
|
||||
#define MMU_PTE_SECT_XN_MASK 0x00000001 /* eXecute Never bit [0] */
|
||||
#define MMU_PTE_SECT_CB_MASK 0x0000000C /* CB bits [3:2] */
|
||||
#define MMU_PTE_SECT_AP_MASK 0x00000030 /* AP bits [5:4] */
|
||||
#define MMU_PTE_SECT_TEX_MASK 0x000001C0 /* TEX bits [8:6] */
|
||||
#define MMU_PTE_SECT_APX_MASK 0x00000200 /* APX bit [9] */
|
||||
#define MMU_PTE_SECT_S_MASK 0x00000400 /* Shared bit [10] */
|
||||
#define MMU_PTE_SECT_NG_MASK 0x00000800 /* not-Global bit [11] */
|
||||
|
||||
/* adjustment to translate fields: Level 1 <-> Level 2 descriptors */
|
||||
|
||||
#define MMU_L1L2_SECT_NG_SHIFT 6 /* nG-bit shift convert L1 to L2 */
|
||||
#define MMU_L1L2_SECT_S_SHIFT 6 /* S-bit shift convert L1 to L2 */
|
||||
#define MMU_L1L2_SECT_TEX_SHIFT 6 /* TEX shift convert L1 to L2 */
|
||||
#define MMU_L1L2_SECT_AP_SHIFT 6 /* AP, APX shift convert L1 to L2 */
|
||||
#define MMU_L1L2_SECT_XN_SHIFT 4 /* XN-bit shift convert L1 to L2 */
|
||||
#define MMU_L1L2_SECT_CB_SHIFT 0 /* CB shift convert L1 to L2 */
|
||||
|
||||
/* Section and Supersection type and size macros */
|
||||
|
||||
#define MMU_PTE_SSECT_TYPE 0x00040000 /* supersection bit [18] */
|
||||
#define MMU_PTE_SECT_TYPE_MASK 0x00040000 /* which type of section? */
|
||||
|
||||
#define MMU_SECT_SIZE 0x100000 /* section = 1MB */
|
||||
#define MMU_SSECT_SIZE 0x1000000 /* supersection = 16MB */
|
||||
|
||||
#define MMU_NUM_VM_PAGES_IN_A_SECT 0x100 /* 1MB = 256 * 4KB pages */
|
||||
#define MMU_NUM_VM_PAGES_IN_A_SSECT 0x1000 /* 16MB = 4096 * 4KB pages */
|
||||
#define MMU_NUM_SECTS_IN_A_SSECT 0x10 /* 16 sections/supersection */
|
||||
|
||||
/*
|
||||
* The Domain Access Control Register specifies the way in which access
|
||||
* rights are treated for each of sixteen domains. For each domain the
|
||||
* current state can be:
|
||||
*
|
||||
* 00 no access: all accesses generate aborts
|
||||
* 01 client: access rights specified in page tables are checked.
|
||||
* 10 reserved
|
||||
* 11 manager: accesses not checked against page tables: all access allowed.
|
||||
*/
|
||||
|
||||
#define MMU_DACR_VAL_NORMAL 1 /* client of 0 */
|
||||
#define MMU_DACR_VAL_UNPROTECT 0x03 /* manager of 0 */
|
||||
|
||||
/* Level 1 Descriptor types */
|
||||
|
||||
#define MMU_DESC_TYPE_FAULT 0 /* any access will cause a fault */
|
||||
#define MMU_DESC_TYPE_PAGE 1
|
||||
#define MMU_DESC_TYPE_SECTION 2
|
||||
|
||||
#define MMU_DEF_L1_PAGE 0x00000001 /* domain zero, Page descriptor */
|
||||
|
||||
/*
|
||||
* Section descriptors, such as might be used to set up an intermediate
|
||||
* set of page tables on processors such as SA-1100/SA-1500 where this
|
||||
* needs to be done from BSP initialization, before vm(Base)Lib sets up
|
||||
* a proper set of page tables.
|
||||
*/
|
||||
|
||||
#define MMU_RAM_SECT_DESC 0xC1E /* R/W cacheable bufferable domain 0 */
|
||||
#define MMU_MINICACHE_SECT_DESC 0xC1A /* R/W C+ B- domain 0 */
|
||||
#define MMU_OTHER_SECT_DESC 0xC12 /* R/W C- B- domain 0 */
|
||||
|
||||
/* Level 2 Descriptor or Page Table Entry (PTE) types */
|
||||
|
||||
#define MMU_PTE_TYPE_FAULT 0 /* any access will cause a fault */
|
||||
#define MMU_PTE_TYPE_LG_PAGE 1 /* Large page descriptor */
|
||||
#define MMU_PTE_TYPE_SM_PAGE 2 /* Small page descriptor */
|
||||
#define MMU_PTE_TYPE_EX_PAGE 3 /* Extended page descriptor */
|
||||
|
||||
/*
|
||||
* The Translation Table Base register (TTBR) points to a table of Level 1
|
||||
* Descriptors. these are either Invalid Section descriptors, Section
|
||||
* Descriptors, or Page Table Descriptors. If Page Table Descriptors, they
|
||||
* each point to a table of Level 2 Page Descriptors, or Page Table Entries
|
||||
* (PTEs).
|
||||
* The 32-bit (virtual) address space allows for 4096 M. Each Level 1
|
||||
* Descriptor describes a 1 M area of memory. There are therefore 4096 Level
|
||||
* 1 Descriptors, and each table of 256 Level 2 Page Descriptors (PTEs)
|
||||
* describes 256 4 kbyte pages.
|
||||
*/
|
||||
|
||||
#define MMU_NUM_L1_DESCS 4096
|
||||
#define MMU_NUM_L2_DESCS 256
|
||||
#define MMU_L1_TABLE_SIZE (MMU_NUM_L1_DESCS * sizeof(MMU_LEVEL_1_DESC))
|
||||
|
||||
/* No. of pages a Level 1 Descriptor table takes up */
|
||||
|
||||
#define MMU_L1_DESC_PAGES (MMU_L1_TABLE_SIZE / MMU_PAGE_SIZE)
|
||||
|
||||
/* Size of a Page Table */
|
||||
|
||||
#define MMU_PAGE_TABLE_SIZE (MMU_NUM_L2_DESCS * sizeof(PTE))
|
||||
|
||||
/* Number of possible ASIDs */
|
||||
|
||||
#define MMU_NUM_ASIDS 256
|
||||
#define VXWORKS_KERNEL_ASID 0 /* reserved ASID for VxWorks kernel */
|
||||
|
||||
/* Section and supersection L1 definitions follow */
|
||||
|
||||
#undef INCLUDE_MMU_SUPERSECTION_SUPPORT /* support supersection descriptors */
|
||||
#define INCLUDE_MMU_SUPERSECTION_SUPPORT
|
||||
|
||||
#undef MMU_DEF_L1_SECTION_PAGE
|
||||
#define MMU_DEF_L1_SECTION_PAGE 0x00000002 /* Section page descriptor */
|
||||
|
||||
#undef MMU_DEF_L1_SUPERSECTION_PAGE
|
||||
#define MMU_DEF_L1_SUPERSECTION_PAGE 0x00040002 /* supersection */
|
||||
|
||||
#undef MMU_DEF_L1_SECTION_PAGE_MASK
|
||||
#define MMU_DEF_L1_SECTION_PAGE_MASK 0x00040003 /* mask */
|
||||
|
||||
#undef MMU_STATE_SECTION_MASK_WRITABLE
|
||||
#define MMU_STATE_SECTION_MASK_WRITABLE 0x00000030 /* All APn bits */
|
||||
|
||||
/*
|
||||
* Architecture-dependent MMU states. These are states settable for pages and
|
||||
* here they correspond to settings in the Page Table Entries (PTEs).
|
||||
*
|
||||
* We set Valid/Invalid by setting a Fault second-level descriptor rather
|
||||
* than by using the Access Permissions within a small page second-level
|
||||
* descriptor. This is because we will want to use the Access Permissions to
|
||||
* control supervisor mode access and we cannot then use the AP bits
|
||||
* to disallow access as the SR bits in the MMU Control register must be set
|
||||
* to 10 in order to control read/write access from Supervisor mode.
|
||||
*/
|
||||
|
||||
#define MMU_STATE_INVALID_STATE 0xFFFFFFFF
|
||||
|
||||
#define MMU_STATE_MASK_VALID 0x00000002 /* 2nd lvl desc bit 1 only */
|
||||
|
||||
#define MMU_STATE_MASK_WRITABLE 0x00000230 /* All APn bits */
|
||||
|
||||
#define MMU_STATE_MASK_CACHEABLE 0x000005CC /* S, TEX[0:2] + CB bits */
|
||||
|
||||
#define MMU_STATE_VALID MMU_PTE_TYPE_SM_PAGE /* set to page type */
|
||||
#define MMU_STATE_VALID_NOT MMU_PTE_TYPE_FAULT /* set to type fault */
|
||||
|
||||
#define MMU_STATE_MASK_PROTECTION 0x00000231 /* APX + APn + XN bits */
|
||||
|
||||
#define MMU_STATE_SUP_RO 0x00000210 /* APX: 1 AP: 01 */
|
||||
#define MMU_STATE_SUP_RW 0x00000010 /* APX: 0 AP: 01 */
|
||||
#define MMU_STATE_SUP_RO_USR_RO 0x00000220 /* APX: 1 AP: 10 */
|
||||
#define MMU_STATE_SUP_RW_USR_RO 0x00000020 /* APX: 0 AP: 10 */
|
||||
#define MMU_STATE_SUP_RW_USR_RW 0x00000030 /* APX: 0 AP: 11 */
|
||||
|
||||
#define MMU_STATE_WRITABLE MMU_STATE_SUP_RW
|
||||
|
||||
#define MMU_STATE_WRITABLE_NOT MMU_STATE_SUP_RO
|
||||
|
||||
#define MMU_STATE_AP_SUP_RO 0x1 /* AP field: 01 */
|
||||
#define MMU_STATE_AP_SUP_RW 0x1 /* AP field: 01 */
|
||||
#define MMU_STATE_AP_SUP_RO_USR_RO 0x2 /* AP field: 10 */
|
||||
#define MMU_STATE_AP_SUP_RW_USR_RO 0x2 /* AP field: 10 */
|
||||
#define MMU_STATE_AP_SUP_RW_USR_RW 0x3 /* AP field: 11 */
|
||||
|
||||
#define MMU_STATE_AP_USR_RO_SUP_RO MMU_STATE_AP_SUP_RO_USR_RO
|
||||
#define MMU_STATE_AP_USR_RO_SUP_RW MMU_STATE_AP_SUP_RW_USR_RO
|
||||
#define MMU_STATE_AP_USR_RW_SUP_RW MMU_STATE_AP_SUP_RW_USR_RW
|
||||
|
||||
/* The Execute-Never bit is an extra permission check on readable addresses */
|
||||
|
||||
#define MMU_STATE_EXE_NOT 0x00000001 /* Execute-Never, XN bit */
|
||||
|
||||
#define MMU_STATE_SUP_RO_XN (MMU_STATE_SUP_RO | MMU_STATE_EXE_NOT)
|
||||
#define MMU_STATE_SUP_RW_XN (MMU_STATE_SUP_RW | MMU_STATE_EXE_NOT)
|
||||
#define MMU_STATE_SUP_RO_USR_RO_XN (MMU_STATE_SUP_RO_USR_RO | MMU_STATE_EXE_NOT)
|
||||
#define MMU_STATE_SUP_RW_USR_RO_XN (MMU_STATE_SUP_RW_USR_RO | MMU_STATE_EXE_NOT)
|
||||
#define MMU_STATE_SUP_RW_USR_RW_XN (MMU_STATE_SUP_RW_USR_RW | MMU_STATE_EXE_NOT)
|
||||
|
||||
/*
|
||||
* Memory Region Attributes -
|
||||
* cache access, write buffer access, coherency control
|
||||
*/
|
||||
|
||||
#define MMU_STATE_STRONGLY_ORDERED 0x0 /* strongly ordered, shared */
|
||||
#define MMU_STATE_CACHEABLE_NOT 0x0 /* backward compatible */
|
||||
|
||||
#define MMU_STATE_DEVICE_SHARED 0x00000004 /* device type, shared */
|
||||
/* (bufferable, not cacheable) */
|
||||
|
||||
/* outer & inner write-thru cachable, no write alloc */
|
||||
|
||||
#define MMU_STATE_NORMAL_WRITETHROUGH 0x00000008
|
||||
#define MMU_STATE_CACHEABLE_WRITETHROUGH 0x00000008 /* backward compatible */
|
||||
|
||||
#define MMU_STATE_NORMAL_WRITEBACK 0x0000000C /* write-back, no alloc */
|
||||
#define MMU_STATE_CACHEABLE_COPYBACK 0x0000000C /* backward compatible */
|
||||
|
||||
#define MMU_STATE_NORMAL_NONCACHEABLE 0x00000040 /* non-cached, sharable */
|
||||
|
||||
#define MMU_STATE_DEVICE_NONSHARED 0x00000080 /* device, non-shared */
|
||||
|
||||
#define MMU_STATE_COPYBACK_ALLOC 0x0000004C /* write-back, sharable */
|
||||
|
||||
/* Define the flags used by Cached Page Tables for the PTEs */
|
||||
|
||||
/*
|
||||
* - For MPCore(Cortex-A9 and ARM11), inner and outer write-back
|
||||
* write-allocate cacheable.
|
||||
* - For UPCore(Cortex-A9 and ARM11), inner and outer write-back
|
||||
* no write-allocate cacheable.
|
||||
*/
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
|
||||
/* s=1,tex=001,c,b=11 */
|
||||
|
||||
#define MMU_STATE_CACHE_PTE_A9_FLAGS (MMU_STATE_COPYBACK_ALLOC | \
|
||||
MMU_STATE_SHARED)
|
||||
#else
|
||||
|
||||
/* s=0,tex=000,c,b=11 */
|
||||
|
||||
#define MMU_STATE_CACHE_PTE_A9_FLAGS (MMU_STATE_NORMAL_WRITEBACK)
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
/* - For Cortex-A15 MPCore, inner and outer write-back, no write-allocate. */
|
||||
|
||||
#define MMU_STATE_WRITEBACK_PTE_A15_MPCORE (MMU_STATE_NORMAL_WRITEBACK)
|
||||
|
||||
/* - For others use the standard settings. */
|
||||
|
||||
#define MMU_STATE_WRITETHROUGH_PTE_GENERIC (MMU_STATE_NORMAL_WRITETHROUGH)
|
||||
|
||||
/*
|
||||
* The following outer/inner noncacheable policy is also used as
|
||||
* the basis for the rest of the outer/inner cache policies.
|
||||
* (See the MMU_ATTR_OUT_x_IN_x macros for SPL_4 below.)
|
||||
*/
|
||||
|
||||
#define MMU_STATE_OUT_OFF_IN_OFF 0x00000100 /* out/inner non-cached */
|
||||
|
||||
/* outer cache policy (TEX[1:0]) >> shift, relative to MMU_ATTR_OUT_x_IN_x */
|
||||
|
||||
#define MMU_STATE_OUTER_CACHE_POLICY_SHIFT 24
|
||||
|
||||
/* inner cache policy (CB) >> shift, relative to MMU_ATTR_OUT_x_IN_x */
|
||||
|
||||
#define MMU_STATE_INNER_CACHE_POLICY_SHIFT 26
|
||||
|
||||
/*
|
||||
* Set the default state to be copyback. CACHEABLE_WRITETHROUGH can also be
|
||||
* selected on those cache designs that permit it.
|
||||
*/
|
||||
|
||||
#define MMU_STATE_CACHEABLE MMU_STATE_CACHEABLE_COPYBACK
|
||||
|
||||
/*
|
||||
* Shared memory attribute -
|
||||
* accessible by multiple processors or bus masters and must be kept coherent
|
||||
*/
|
||||
|
||||
#define MMU_STATE_SHARED 0x00000400 /* Shared bit */
|
||||
|
||||
#define MMU_STATE_WRITETHROUGH_SHARED \
|
||||
(MMU_STATE_CACHEABLE_WRITETHROUGH | MMU_STATE_SHARED)
|
||||
#define MMU_STATE_COPYBACK_SHARED \
|
||||
(MMU_STATE_CACHEABLE_COPYBACK | MMU_STATE_SHARED)
|
||||
#define MMU_STATE_NONCACHEABLE_SHARED \
|
||||
(MMU_STATE_NORMAL_NONCACHEABLE | MMU_STATE_SHARED)
|
||||
|
||||
/*
|
||||
* Global memory attribute -
|
||||
* not-Global causes ASID to be associated with address translation
|
||||
*/
|
||||
|
||||
#define MMU_STATE_NOT_GLOBAL 0x00000800 /* not-Global bit */
|
||||
|
||||
/*
|
||||
* Architecture-specific attributes
|
||||
*
|
||||
* The following ARMv6-specific aliases are provided for ease of use.
|
||||
*
|
||||
* NOTE: MMU_ATTR_CACHE_GUARDED is used as MMU_ATTR_CACHE_IO (its former name).
|
||||
*/
|
||||
|
||||
/* Strongly Ordered - same as MMU_ATTR_CACHE_OFF for backward compatibility */
|
||||
|
||||
#define MMU_ATTR_STRONGLY_ORDERED (MMU_ATTR_CACHE_OFF)
|
||||
|
||||
/* Shared Device */
|
||||
|
||||
#define MMU_ATTR_DEVICE_SHARED_MSK (MMU_ATTR_CACHE_MSK)
|
||||
#define MMU_ATTR_DEVICE_SHARED (MMU_ATTR_CACHE_GUARDED | MMU_ATTR_CACHE_OFF | \
|
||||
MMU_ATTR_CACHE_COHERENCY)
|
||||
#define MMU_ATTR_BUFFERABLE MMU_ATTR_DEVICE_SHARED /* backward compatible */
|
||||
|
||||
/* Non-Shared Device */
|
||||
|
||||
#define MMU_ATTR_DEVICE_NONSHARED_MSK MMU_ATTR_DEVICE_SHARED_MSK
|
||||
#define MMU_ATTR_DEVICE_NONSHARED (MMU_ATTR_CACHE_GUARDED | \
|
||||
MMU_ATTR_CACHE_OFF)
|
||||
|
||||
/*
|
||||
* Special Purpose Attributes:
|
||||
* When setting any of these attributes, it is necessary to:
|
||||
*
|
||||
* 1. specify MMU_ATTR_SPL_MSK ORred with MMU_ATTR_CACHE_MSK in the mask
|
||||
* argument to the routine, and:
|
||||
* 2. specify the appropriate cache state ORed in to the state argument
|
||||
* to the routine, unless the cache state is implied.
|
||||
*
|
||||
* So, to set a page as normal, noncacheable memory, it is necessary to
|
||||
* specify both MMU_ATTR_SPL_0 and specify MMU_ATTR_CACHE_OFF in the
|
||||
* state argument.
|
||||
*
|
||||
* To "unset" the special attributes, specify MMU_ATTR_CACHE_MSK in
|
||||
* the mask parameter (without MMU_ATTR_SPL_MSK) and specify the
|
||||
* cacheability required in the state argument.
|
||||
*/
|
||||
|
||||
/* Normal, Noncacheable memory */
|
||||
|
||||
#define MMU_ATTR_NORMAL_NONCACHEABLE_MSK (MMU_ATTR_SPL_MSK | MMU_ATTR_CACHE_MSK)
|
||||
#define MMU_ATTR_NORMAL_NONCACHEABLE (MMU_ATTR_SPL_0 | MMU_ATTR_CACHE_OFF)
|
||||
#define MMU_ATTR_NORMAL_NONCACHEABLE_SHARED (MMU_ATTR_NORMAL_NONCACHEABLE | \
|
||||
MMU_ATTR_CACHE_COHERENCY)
|
||||
|
||||
/*
|
||||
* Outer and Inner Cache Write-Back, Write Allocate (same as XScale)
|
||||
* -- this can also be ORed with MMU_ATTR_CACHE_COHERENCY to set as Shared
|
||||
*/
|
||||
|
||||
#define MMU_ATTR_WRITEALLOCATE_MSK (MMU_ATTR_SPL_MSK | MMU_ATTR_CACHE_MSK)
|
||||
#define MMU_ATTR_WRITEALLOCATE (MMU_ATTR_SPL_3 | MMU_ATTR_CACHE_COPYBACK)
|
||||
#define MMU_ATTR_WRITEALLOCATE_SHARED (MMU_ATTR_WRITEALLOCATE | \
|
||||
MMU_ATTR_CACHE_COHERENCY)
|
||||
|
||||
/*
|
||||
* Individually Specified Outer and Inner Cache Policies
|
||||
* -- ORed with TEX[1:0] and CB encodings for each, shifted to prevent
|
||||
* conflicts with common MMU_ATTR_ protection, cache, valid and SPL bits:
|
||||
* OFF - Noncacheable, Unbuffered
|
||||
* WBWA - Write-Back cached, Write Allocate, Buffered
|
||||
* WTNA - Write-Through cached, No Allocate on Write, Buffered
|
||||
* WBNA - Write-Back cached, No Allocate on Write, Buffered
|
||||
*
|
||||
* -- these can also be ORed with MMU_ATTR_CACHE_COHERENCY to set as Shared,
|
||||
* but since MMU_ATTR_CACHE_COHERENCY is invalid by itself
|
||||
* MMU_ATTR_CACHE_OFF is added to all of them (and will be disregarded)
|
||||
*/
|
||||
|
||||
#define MMU_ATTR_CACHE_POLICY_SHIFT 28 /* cache policy encoding << shift */
|
||||
#define MMU_ATTR_CACHE_OUTER_POLICY_MSK 0xC0000000 /* outer policy code bits */
|
||||
#define MMU_ATTR_CACHE_INNER_POLICY_MSK 0x30000000 /* inner policy code bits */
|
||||
|
||||
#define MMU_ATTR_OUT_X_IN_Y_MSK (MMU_ATTR_SPL_MSK | MMU_ATTR_CACHE_MSK)
|
||||
#define MMU_ATTR_OUT_OFF_IN_OFF (MMU_ATTR_SPL_4 | MMU_ATTR_CACHE_OFF)
|
||||
#define MMU_ATTR_OUT_OFF_IN_WBWA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0x1 << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
#define MMU_ATTR_OUT_OFF_IN_WTNA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0x2 << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
#define MMU_ATTR_OUT_OFF_IN_WBNA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0x3 << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
|
||||
#define MMU_ATTR_OUT_WBWA_IN_OFF (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0x4 << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
#define MMU_ATTR_OUT_WBWA_IN_WBWA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0x5 << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
#define MMU_ATTR_OUT_WBWA_IN_WTNA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0x6 << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
#define MMU_ATTR_OUT_WBWA_IN_WBNA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0x7 << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
|
||||
#define MMU_ATTR_OUT_WTNA_IN_OFF (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0x8 << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
#define MMU_ATTR_OUT_WTNA_IN_WBWA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0x9 << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
#define MMU_ATTR_OUT_WTNA_IN_WTNA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0xA << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
#define MMU_ATTR_OUT_WTNA_IN_WBNA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0xB << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
|
||||
#define MMU_ATTR_OUT_WBNA_IN_OFF (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0xC << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
#define MMU_ATTR_OUT_WBNA_IN_WBWA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0xD << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
#define MMU_ATTR_OUT_WBNA_IN_WTNA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0xE << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
#define MMU_ATTR_OUT_WBNA_IN_WBNA (MMU_ATTR_OUT_OFF_IN_OFF | \
|
||||
(0xF << MMU_ATTR_CACHE_POLICY_SHIFT))
|
||||
|
||||
/* MMU Control Register bit allocations */
|
||||
|
||||
#define MMUCR_M_ENABLE (1<<0) /* MMU enable */
|
||||
#define MMUCR_A_ENABLE (1<<1) /* Address alignment fault enable */
|
||||
#define MMUCR_C_ENABLE (1<<2) /* (data) cache enable */
|
||||
#define MMUCR_W_ENABLE (1<<3) /* write buffer enable */
|
||||
#define MMUCR_PROG32 (1<<4) /* PROG32 */
|
||||
#define MMUCR_DATA32 (1<<5) /* DATA32 */
|
||||
#define MMUCR_L_ENABLE (1<<6) /* Late abort on earlier CPUs */
|
||||
#define MMUCR_BIGEND (1<<7) /* Big-endian (=1), little-endian (=0) */
|
||||
#define MMUCR_SYSTEM (1<<8) /* System bit, modifies MMU protections */
|
||||
#define MMUCR_ROM (1<<9) /* ROM bit, modifies MMU protections */
|
||||
#define MMUCR_F (1<<10) /* Should Be Zero */
|
||||
#define MMUCR_Z_ENABLE (1<<11) /* Branch prediction enable on 810 */
|
||||
#define MMUCR_I_ENABLE (1<<12) /* Instruction cache enable */
|
||||
#define MMUCR_V_ENABLE (1<<13) /* Exception vectors remap to 0xFFFF0000 */
|
||||
#define MMUCR_ALTVECT MMUCR_V_ENABLE /* alternate vector select */
|
||||
#define MMUCR_RR_ENABLE (1<<14) /* Round robin cache replacement enable */
|
||||
#define MMUCR_ROUND_ROBIN MMUCR_RR_ENABLE /* round-robin placement */
|
||||
#define MMUCR_DISABLE_TBIT (1<<15) /* disable TBIT */
|
||||
#define MMUCR_ENABLE_DTCM (1<<16) /* Enable Data TCM */
|
||||
#define MMUCR_ENABLE_ITCM (1<<18) /* Enable Instruction TCM */
|
||||
#define MMUCR_UNALIGNED_ENABLE (1<<22) /* Enable unaligned access */
|
||||
#define MMUCR_EXTENDED_PAGE (1<<23) /* Use extended PTE format */
|
||||
#define MMUCR_VECTORED_INTERRUPT (1<<24) /* Enable VIC Interface */
|
||||
#define MMUCR_EE (1<<25) /* Exception Endianness bit */
|
||||
#define MMUCR_THUMB_EXCEPTIONS (1<<30) /* Exceptions are Thumb */
|
||||
|
||||
#define ADDR_TO_PAGE 12 /* shift phys address to PTE page base address*/
|
||||
|
||||
/* MMU TTBR register fields for v6 and v7a */
|
||||
|
||||
#define MMU_TTBR_BASE_ADDR_MASK 0xFFFFC000
|
||||
#define MMU_TTBR_C_MASK 0x00000001
|
||||
#define MMU_TTBR_RGN_MASK 0x00000018
|
||||
#define MMU_TTBR_IRGN_MASK 0x00000041
|
||||
#define MMU_TTBR_NOS_MASK 0x00000020
|
||||
#define MMU_TTBR_S_MASK 0x00000002
|
||||
#define MMU_TTBR_IMP_MASK 0x00000004
|
||||
|
||||
/* RGN field bits */
|
||||
|
||||
#define MMU_TTBR_RGN_NML_NC 0x00000000 /* Normal, outer not cached */
|
||||
#define MMU_TTBR_RGN_NML_WB_WA 0x00000008 /* Normal, outer write-back,
|
||||
write-allocate cached */
|
||||
#define MMU_TTBR_RGN_NML_WT 0x00000010 /* Normal, outer write-thru cached */
|
||||
#define MMU_TTBR_RGN_NML_WB 0x00000018 /* Normal, outer write-back, */
|
||||
/* no write-allocate cached */
|
||||
|
||||
/* IRGN field bits */
|
||||
|
||||
#define MMU_TTBR_IRGN_NML_NC 0x00000000 /* Normal, inner not cached */
|
||||
#define MMU_TTBR_IRGN_NML_WT 0x00000001 /* Normal, inner write-thru cached */
|
||||
#define MMU_TTBR_IRGN_NML_WB_WA 0x00000040 /* Normal, inner write-back,
|
||||
write-allocate cached */
|
||||
#define MMU_TTBR_IRGN_NML_WB 0x00000041 /* Normal, inner write-back, */
|
||||
/* no write-allocate cached */
|
||||
|
||||
/* C Bit fields */
|
||||
|
||||
#define MMU_TTBR_C_NML_NC 0x00000000 /* Normal, not cached */
|
||||
#define MMU_TTBR_C_NML_C 0x00000001 /* Normal, cached */
|
||||
|
||||
/* S & NOS fields */
|
||||
|
||||
#define MMU_TTBR_S 0x00000002 /* Inner Shared */
|
||||
#define MMU_TTBR_NOS 0x00000020 /* Not Outer Shared */
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
|
||||
/*
|
||||
* ARM Cortex-A9 MPCore and ARM11 MPCore do not support inner write-through
|
||||
* cached page tables. Cortex-A9 MPCore L2 can support write-through cached page
|
||||
* tables. Setup TTBR for normal memory, inner and outer write-back
|
||||
* write-allocate cacheable.
|
||||
*/
|
||||
|
||||
/* IRGN[0]=1,NOS=1,RGN=0b01,S=1 */
|
||||
|
||||
#define MMU_TTBR_CACHE_PTE_A9_FLAGS (MMU_TTBR_RGN_NML_WB_WA | \
|
||||
MMU_TTBR_IRGN_NML_WB_WA | \
|
||||
MMU_TTBR_S | \
|
||||
MMU_TTBR_NOS)
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* ARM Cortex-A9 UPCore and ARM11 UPCore.
|
||||
* Setup TTBR for normal memory, inner and outer write-back
|
||||
* no write-allocate cacheable.
|
||||
*/
|
||||
|
||||
/* IRGN[0]=1,NOS=0,RGN=0b11,S=0,C=1 */
|
||||
|
||||
#define MMU_TTBR_CACHE_PTE_A9_FLAGS (MMU_TTBR_RGN_NML_WB | \
|
||||
MMU_TTBR_IRGN_NML_WB)
|
||||
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
/*
|
||||
* ARM Cortex-A15 MPCore does not support write-through for L1 and L2 cache.
|
||||
* Here, setup TTBR for inner and outer write-back, no write-allocate cached.
|
||||
*/
|
||||
|
||||
#define MMU_TTBR_CACHE_PTE_A15_MPCORE ( MMU_TTBR_IRGN_NML_WB | \
|
||||
MMU_TTBR_RGN_NML_WB )
|
||||
|
||||
/*
|
||||
* For ARM Cortex-A8, or generic ARMv7 & ARMv6 cores:
|
||||
*
|
||||
* Select the mask for the single core or MPCore format for the TTBR. By
|
||||
* default we support the MPCore format because it is compatible with the UP
|
||||
* format and it is safer to zero out all the bits which are unused. Select
|
||||
* inner and outer write-through cached page tables.
|
||||
*/
|
||||
|
||||
#ifdef _WRS_CONFIG_USE_MC_TTBR_FMT
|
||||
#define MMU_TTBR_CACHE_PTE_GENERIC \
|
||||
( MMU_TTBR_IRGN_NML_WT | MMU_TTBR_RGN_NML_WT )
|
||||
#else /* _WRS_CONFIG_USE_MC_TTBR_FMT */
|
||||
#define MMU_TTBR_CACHE_PTE_GENERIC \
|
||||
( MMU_TTBR_C_NML_C | MMU_TTBR_RGN_NML_WT )
|
||||
#endif /* _WRS_CONFIG_USE_MC_TTBR_FMT */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
|
||||
/* little-endian */
|
||||
|
||||
/* First level page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* descriptor type, 1 => page */
|
||||
UINT pad1 : 2; /* SBZ */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT pbit : 1; /* 'P' bit */
|
||||
UINT addr : 22; /* base address of page table */
|
||||
} PAGE_DESC_FIELD;
|
||||
|
||||
/* First level "section" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
UINT bbit : 1; /* bufferable-bit */
|
||||
UINT cbit : 1; /* cacheable-bit */
|
||||
UINT xnbit : 1; /* XN-bit */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT tex : 3; /* TEX */
|
||||
UINT apx : 1; /* APX */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT nG : 1; /* nG-bit */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT pad1 : 1; /* SBZ */
|
||||
UINT addr : 12; /* base address of page table */
|
||||
} SECTION_DESC_FIELD;
|
||||
|
||||
/* First level "supersection" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
UINT bbit : 1; /* bufferable-bit */
|
||||
UINT cbit : 1; /* cacheable-bit */
|
||||
UINT xnbit : 1; /* XN-bit */
|
||||
UINT addrHi2: 4; /* phys address 39:36 */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT tex : 3; /* TEX */
|
||||
UINT apx : 1; /* APX */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT nG : 1; /* nG-bit */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT pad1 : 1; /* SBZ */
|
||||
UINT addrHi : 4; /* phys address 35:32 */
|
||||
UINT addrLo : 8; /* phys address 31:24 */
|
||||
} SUPERSECTION_DESC_FIELD;
|
||||
|
||||
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* page type, 3 => extended small page */
|
||||
UINT cb : 2; /* cacheable/bufferable bits */
|
||||
UINT ap : 2; /* access permission */
|
||||
UINT tex : 3; /* type extension field */
|
||||
UINT apx : 1; /* access permission extension field */
|
||||
UINT sbz : 2; /* should be zero */
|
||||
UINT addr : 20; /* page base address */
|
||||
} PTE_FIELD;
|
||||
|
||||
#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
|
||||
|
||||
/* big-endian */
|
||||
|
||||
/* First level page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT addr : 22; /* base address of page table */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT pad1 : 2; /* SBZ */
|
||||
UINT type : 2; /* descriptor type, 1 => page */
|
||||
} PAGE_DESC_FIELD;
|
||||
|
||||
/* First level "section" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT addr : 12; /* base address of page table */
|
||||
UINT pad1 : 1; /* SBZ */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT nG : 1; /* nG-bit */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT apx : 1; /* APX */
|
||||
UINT tex : 3; /* AP */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT xnbit : 1; /* XN-bit */
|
||||
UINT cbit : 1; /* C-bit */
|
||||
UINT bbit : 1; /* B-bit */
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
} SECTION_DESC_FIELD;
|
||||
|
||||
/* First level "supersection" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT addrLo : 8; /* phys address 31:24 */
|
||||
UINT addrHi : 4; /* phys address 35:32 */
|
||||
UINT pad1 : 1; /* SBZ */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT nG : 1; /* nG-bit */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT apx : 1; /* APX */
|
||||
UINT tex : 3; /* AP */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT addrHi2: 4; /* phys address 39:36 */
|
||||
UINT xnbit : 1; /* XN-bit */
|
||||
UINT cbit : 1; /* C-bit */
|
||||
UINT bbit : 1; /* B-bit */
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
} SUPERSECTION_DESC_FIELD;
|
||||
|
||||
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT addr : 20; /* page base address */
|
||||
UINT sbz : 2; /* should be zero */
|
||||
UINT apx : 1; /* access permission extension field */
|
||||
UINT tex : 3; /* type extension field */
|
||||
UINT ap : 2; /* access permission */
|
||||
UINT cb : 2; /* cacheable/bufferable bits */
|
||||
UINT type : 2; /* page type, 3 => extended small page */
|
||||
} PTE_FIELD;
|
||||
|
||||
#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
|
||||
|
||||
/* First level descriptor access */
|
||||
|
||||
typedef union
|
||||
{
|
||||
PAGE_DESC_FIELD fields;
|
||||
SECTION_DESC_FIELD sectionFields;
|
||||
SUPERSECTION_DESC_FIELD supersectionFields;
|
||||
UINT32 bits;
|
||||
} MMU_LEVEL_1_DESC;
|
||||
|
||||
/* Second level descriptor access */
|
||||
|
||||
typedef union
|
||||
{
|
||||
PTE_FIELD fields;
|
||||
UINT32 bits;
|
||||
} PTE;
|
||||
|
||||
/*
|
||||
* Structure for MMU translation table access - normally used to get a pointer
|
||||
* to the first-level translation table.
|
||||
* To support page table optimization, a second first-level table and a
|
||||
* semaphore are needed.
|
||||
* The initial, unoptimized set of page tables will be set as the active
|
||||
* translation tables (via pLevel1Table) while optimization or deoptimization
|
||||
* is in progress using the inactive second translation table (pAltLevel1Table).
|
||||
* After each page table optimization or deoptimization operation has
|
||||
* completed, the second translation table will be set as the active
|
||||
* translation table. The initial set of page tables retain their
|
||||
* links to level 2 pages, which may otherwise be lost after optimization.
|
||||
* Any non-optimization changes to the active first-level table will also be
|
||||
* made to the inactive first-level table.
|
||||
* The semaphore is used to prevent corruption of the tables.
|
||||
*/
|
||||
|
||||
typedef struct mmuTransTblStruct
|
||||
{
|
||||
MMU_LEVEL_1_DESC *pLevel1Table; /* active MMU table */
|
||||
MMU_LEVEL_1_DESC *pAltLevel1Table; /* inactive MMU table */
|
||||
VX_MUTEX_SEMAPHORE(mmuTransTblSem); /* MMU tables' semaphore */
|
||||
UINT32 lockCnt; /* lock count */
|
||||
atomic_t lockOwner; /* lock owner */
|
||||
UINT8 asid; /* ASID/context id */
|
||||
} MMU_TRANS_TBL;
|
||||
|
||||
/* Externally visible mmuLib, mmuMapLib and mmuALib2 routines */
|
||||
|
||||
IMPORT UINT32 mmuReadId (void);
|
||||
IMPORT PHYS_ADDR mmuVirtToPhys (VIRT_ADDR addr);
|
||||
IMPORT VIRT_ADDR mmuPhysToVirt (PHYS_ADDR addr);
|
||||
|
||||
IMPORT UINT32 (* mmuCrGet) (void);
|
||||
IMPORT void (* mmuModifyCr) (UINT32 value, UINT32 mask);
|
||||
IMPORT UINT32 mmuHardCrGet (void);
|
||||
IMPORT UINT32 mmuSoftCrGet (void);
|
||||
IMPORT void mmuModifyHardCr (UINT32 value, UINT32 mask);
|
||||
IMPORT void mmuModifySoftCr (UINT32 value, UINT32 mask);
|
||||
|
||||
IMPORT UINT32 (* _func_mmuFaultAddrGet) (void);
|
||||
IMPORT UINT32 (* _func_mmuFaultStatusGet) (void);
|
||||
IMPORT UINT32 (* _func_mmuIFaultStatusGet) (void);
|
||||
IMPORT UINT32 mmuIFsrGet (void); /* CP15_IFSR only available with MMUs */
|
||||
IMPORT UINT32 mmuFarGet (void); /* CP15_FAR only available with MMUs */
|
||||
IMPORT UINT32 mmuFsrGet (void); /* CP15_FSR only available with MMUs */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmmuArmArch6PalLibh */
|
||||
@@ -0,0 +1,107 @@
|
||||
/* mmuArmLib.h - ARM MMU library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996-2001, 2003-2008, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
02a,29jul10,pad Moved extern C statement after include statements.
|
||||
01z,04jun10,wqi corrected spelling mistake. (WIND00203804)
|
||||
01y,11jul07,j_b add ARMMMU_11MPCORE support
|
||||
01x,12jun08,j_b add Cortex-A MMU support
|
||||
01w,13jul06,m_h MPU Support
|
||||
01v,25jan06,m_h Manzano Support
|
||||
01u,29mar05,jb Adding ARMARCH6 and 1136 support
|
||||
01t,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01s,09dec04,jb Palifying mmu
|
||||
See mmuArmPalLib.h for previous contents
|
||||
01r,10aug04,scm adjust for removal of MPU support, add 926E...
|
||||
01q,18sep03,scm BASE 6 port...
|
||||
01p,04oct01,scm add extended small page table support for XScale...
|
||||
01o,23jul01,scm change XScale name to conform to coding standards...
|
||||
01n,11jul01,scm add support for XScale...
|
||||
01m,29mar01,jpd removed externs for mmyPhysToVirt & mmuVirtToPhys (SPR #63512).
|
||||
01l,19mar01,jpd redefine MMU_ATTR_BUFFERABLE and MMU_ATTR_CACHE_MINICACHE
|
||||
(SPR #64788).
|
||||
01k,16aug00,jpd no longer clear MMUCR Reserved/Should Be Zero bits (SPR #33608)
|
||||
01j,14jun00,jpd reworked MMU_STATE_WRITETHROUGH definition.
|
||||
01i,17feb00,jpd T3: prefixed defs with MMU_; added new defs; changed SR to 10.
|
||||
01h,07sep99,jpd added ARM740T, ARM920T support.
|
||||
01g,20jan99,cdp removed support for old ARM libraries;
|
||||
add prefix to MMU_IDs.
|
||||
01f,24nov98,jpd added ARM940T support, added other CPU ids; removed
|
||||
mmuIntLock/Unlock as intIFLock/Unlock to be used instead;
|
||||
cdp restructured for multiple cache/MMU libraries; big-endian.
|
||||
01e,09mar98,jpd added MMUCTR_ definitions for ARM810 and extra cache states.
|
||||
01d,20jan98,jpd added _func_armPhysToVirt() etc. function pointers.
|
||||
01c,17sep97,jpd added MMU_INIT_VALUE and mmuIntLock/Unlock definitions.
|
||||
01b,24jan97,jpd modified mmuAEnable definition.
|
||||
01a,09may96,cdp created.
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuArmLibh
|
||||
#define __INCmmuArmLibh
|
||||
|
||||
#if (ARMMMU != ARMMMU_NONE)
|
||||
|
||||
#if (ARMMMU == ARMMMU_710A)
|
||||
#include "mmuArm710aLib.h"
|
||||
#elif (ARMMMU == ARMMMU_720T)
|
||||
#include "mmuArm720tLib.h"
|
||||
#elif (ARMMMU == ARMMMU_810)
|
||||
#include "mmuArm810Lib.h"
|
||||
#elif (ARMMMU == ARMMMU_SA110)
|
||||
#include "mmuArmSA110Lib.h"
|
||||
#elif (ARMMMU == ARMMMU_SA1100)
|
||||
#include "mmuArmSA1100Lib.h"
|
||||
#elif (ARMMMU == ARMMMU_SA1500)
|
||||
#include "mmuArmSA1500Lib.h"
|
||||
#elif (ARMMMU == ARMMMU_920T)
|
||||
#include "mmuArm920tLib.h"
|
||||
#elif (ARMMMU == ARMMMU_926E)
|
||||
#include "mmuArm926eLib.h"
|
||||
#elif (ARMMMU == ARMMMU_XSCALE)
|
||||
#include "mmuArmXSCALELib.h"
|
||||
#elif (ARMMMU == ARMMMU_MANZANO)
|
||||
#include "mmuArmManzanoLib.h"
|
||||
#elif (ARMMMU == ARMMMU_1020E)
|
||||
#include "mmuArm1020eLib.h"
|
||||
#elif (ARMMMU == ARMMMU_1022E)
|
||||
#include "mmuArm1022eLib.h"
|
||||
#elif (ARMMMU == ARMMMU_1136JF)
|
||||
#include "mmuArm1136jfLib.h"
|
||||
#elif (ARMMMU == ARMMMU_CORTEXA8)
|
||||
#include "mmuCortexA8Lib.h"
|
||||
#elif (ARMMMU == ARMMMU_11MPCORE)
|
||||
#include "mmuArm11MPCoreLib.h"
|
||||
|
||||
#elif (ARMMMU == ARMMPU_740T)
|
||||
#include "mpuArm740tLib.h"
|
||||
#elif (ARMMMU == ARMMPU_940T)
|
||||
#include "mpuArm940tLib.h"
|
||||
#elif (ARMMMU == ARMMPU_946E)
|
||||
#include "mpuArm946eLib.h"
|
||||
|
||||
#else
|
||||
#error "Unknown MMU specified"
|
||||
#endif /* ARMMMU == ARMMMU_710A */
|
||||
|
||||
#endif /* (ARMMMU != ARMMMU_NONE) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Any expression using C statements must be defined here */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmmuArmLibh */
|
||||
@@ -0,0 +1,479 @@
|
||||
/* mmuArmLpaeLib.h - ARM LPAE MMU library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013-2014 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
17apr14,c_l add the write protection of L2 page table. (VXW6-73478)
|
||||
01a,01jun13,zgl written
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuArmLpaeLibh
|
||||
#define __INCmmuArmLpaeLibh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* includes */
|
||||
|
||||
#include <memLib.h>
|
||||
#include <semLib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/* defines */
|
||||
|
||||
/* make mask, h = end bit, l = start bit */
|
||||
|
||||
#define MAKE_MASK_64(h,l) (((1ULL << (h + 1)) - 1) & ~((1ULL << l) - 1))
|
||||
#define MAKE_MASK_32(h,l) (((1UL << (h + 1)) - 1) & ~((1UL << l) - 1))
|
||||
|
||||
/*
|
||||
* The page size we will use. Ignore the sub-page, Large Page and Tiny
|
||||
* Page features.
|
||||
*/
|
||||
|
||||
#define MMU_PAGE_SIZE 4096
|
||||
#define PAGE_SIZE MMU_PAGE_SIZE
|
||||
|
||||
#define MMU_ADRS_TO_L1D_INDEX_SHIFT 30
|
||||
#define MMU_ADRS_TO_L2D_INDEX_SHIFT 21
|
||||
#define MMU_PAGE_SIZE_SHIFT 12
|
||||
|
||||
#define MMU_LPAE_NO_BITS_PHYS_ADDR 40
|
||||
|
||||
|
||||
/* get Level 2 index */
|
||||
|
||||
#define MMU_L2PD_INDEX_GET(vaddr) \
|
||||
((vaddr >> MMU_ADRS_TO_L2D_INDEX_SHIFT) & (MMU_NUM_L2_DESCS - 1))
|
||||
|
||||
#define MMU_PTE_INDEX_MASK MAKE_MASK_32(20,12) /* extract PTE index from */
|
||||
/* Virt Addr */
|
||||
#define MMU_PTE_BA_MASK MAKE_MASK_64(39,12) /* extract phys base address */
|
||||
#define MMU_PTE_INDEX_SHIFT 12 /* shift to make that into PTE index */
|
||||
|
||||
#define MMU_ADDR_PI_MASK 0x00000FFF /* extract page offset from Virt Addr */
|
||||
|
||||
/* extract phys L2 page table base addr from L1PD */
|
||||
|
||||
#define MMU_L1PD_L2TBL_MASK MAKE_MASK_64(39,12)
|
||||
|
||||
/* extract phys L3 page table base addr from L2PD */
|
||||
|
||||
#define MMU_L2PD_L3TBL_MASK MMU_L1PD_L2TBL_MASK
|
||||
|
||||
/* Level 1/2 Descriptor types */
|
||||
|
||||
#define MMU_DESC_TYPE_FAULT 0x0 /* any access will cause a fault */
|
||||
#define MMU_DESC_TYPE_BLOCK 0x1 /* block descriptor */
|
||||
#define MMU_DESC_TYPE_TABLE 0x3 /* page table descriptor */
|
||||
|
||||
/* defalt Descriptor types for Level 1/2 */
|
||||
|
||||
#define MMU_DEF_L1_PAGE MMU_DESC_TYPE_TABLE
|
||||
#define MMU_DEF_L2_PAGE MMU_DEF_L1_PAGE
|
||||
|
||||
/* Level 3 Descriptor or Page Table Entry (PTE) types */
|
||||
|
||||
#define MMU_PTE_TYPE_FAULT 0x0 /* any access will cause a fault */
|
||||
#define MMU_PTE_TYPE_PAGE 0x3 /* page descriptor */
|
||||
|
||||
#define MMU_PTE_AF (1 << 10) /* access flag bit */
|
||||
|
||||
/* No. of Descriptor for each page table level */
|
||||
|
||||
#define MMU_NUM_L1_DESCS 4
|
||||
#define MMU_NUM_L2_DESCS 512
|
||||
#define MMU_NUM_L3_DESCS 512
|
||||
|
||||
#define MMU_L1_TABLE_SIZE MMU_PAGE_SIZE
|
||||
|
||||
/* No. of pages a Level 1 Descriptor table takes up */
|
||||
|
||||
#define MMU_L1_DESC_PAGES (MMU_L1_TABLE_SIZE / MMU_PAGE_SIZE)
|
||||
|
||||
/* The amount described by a L1 Descriptor */
|
||||
|
||||
#define MMU_L1_DESC_RANGE (MMU_NUM_L2_DESCS * MMU_NUM_L3_DESCS * MMU_PAGE_SIZE)
|
||||
|
||||
/* Size of a Page Table */
|
||||
|
||||
#define MMU_PAGE_TABLE_SIZE MMU_PAGE_SIZE
|
||||
|
||||
/*
|
||||
* The amount described by a L2 Descriptor, which equals the smallest
|
||||
* amount of VM allocatable in VxWorks.
|
||||
*/
|
||||
|
||||
#define MMU_L2_DESC_RANGE (MMU_NUM_L3_DESCS * MMU_PAGE_SIZE) /* 2 MBytes */
|
||||
|
||||
#define MMU_PAGE_BLOCK_SIZE MMU_L2_DESC_RANGE
|
||||
|
||||
|
||||
/* Number of possible ASIDs */
|
||||
|
||||
#define MMU_NUM_ASIDS 256
|
||||
#define VXWORKS_KERNEL_ASID 0 /* reserved ASID for VxWorks kernel */
|
||||
|
||||
/*
|
||||
* Architecture-dependent MMU states. These are states settable for pages and
|
||||
* here they correspond to settings in the Page Table Entries (PTEs).
|
||||
*/
|
||||
|
||||
#define MMU_STATE_INVALID_STATE 0xFFFFFFFF
|
||||
|
||||
#define MMU_STATE_MASK_VALID 0x00000003 /* bits[1:0] for PTE state */
|
||||
|
||||
#define MMU_STATE_MASK_WRITABLE 0x000000C0 /* AP[2:1], bits[7:6] */
|
||||
|
||||
#define MMU_STATE_MASK_CACHEABLE 0x0000031C /* SH[1:0], AttrIndex[2:0], */
|
||||
/* bits[9:8] and bits[4:2] */
|
||||
|
||||
#define MMU_STATE_VALID 0x3 /* 0b11 means valid */
|
||||
#define MMU_STATE_VALID_NOT 0x0 /* 0b00 means NOT valid */
|
||||
|
||||
#define MMU_STATE_MASK_PROTECTION 0x000000C0 /* AP[2:1], bits[7:6] */
|
||||
|
||||
#define MMU_STATE_SUP_RO 0x00000080 /* AP: 10 */
|
||||
#define MMU_STATE_SUP_RW 0x00000000 /* AP: 00 */
|
||||
#define MMU_STATE_SUP_RO_USR_RO 0x000000C0 /* AP: 11 */
|
||||
#define MMU_STATE_SUP_RW_USR_RO 0x00000040 /* AP: 01, not support, */
|
||||
/* here we set same as RW */
|
||||
#define MMU_STATE_SUP_RW_USR_RW 0x00000040 /* AP: 01 */
|
||||
|
||||
/* XN not support */
|
||||
|
||||
#define MMU_STATE_SUP_RO_XN MMU_STATE_SUP_RO
|
||||
#define MMU_STATE_SUP_RW_XN MMU_STATE_SUP_RW
|
||||
#define MMU_STATE_SUP_RO_USR_RO_XN MMU_STATE_SUP_RO_USR_RO
|
||||
#define MMU_STATE_SUP_RW_USR_RO_XN MMU_STATE_SUP_RW_USR_RO
|
||||
#define MMU_STATE_SUP_RW_USR_RW_XN MMU_STATE_SUP_RW_USR_RW
|
||||
|
||||
#define MMU_STATE_WRITABLE MMU_STATE_SUP_RW
|
||||
|
||||
#define MMU_STATE_WRITABLE_NOT MMU_STATE_SUP_RO
|
||||
|
||||
#define MMU_STATE_AP_SUP_RO 0x2 /* AP field: 10 */
|
||||
#define MMU_STATE_AP_SUP_RW 0x0 /* AP field: 00 */
|
||||
#define MMU_STATE_AP_SUP_RO_USR_RO 0x3 /* AP field: 11 */
|
||||
#define MMU_STATE_AP_SUP_RW_USR_RO 0x1 /* AP field: 01, arm not support */
|
||||
#define MMU_STATE_AP_SUP_RW_USR_RW 0x1 /* AP field: 01 */
|
||||
|
||||
#define MMU_STATE_AP_USR_RO_SUP_RO MMU_STATE_AP_SUP_RO_USR_RO
|
||||
#define MMU_STATE_AP_USR_RO_SUP_RW MMU_STATE_AP_SUP_RW_USR_RO
|
||||
#define MMU_STATE_AP_USR_RW_SUP_RW MMU_STATE_AP_SUP_RW_USR_RW
|
||||
|
||||
/*
|
||||
* Memory Region Attributes -
|
||||
* cache access, write buffer access, coherency control
|
||||
*/
|
||||
|
||||
/*
|
||||
* Memory Region Attributes - for LPAE
|
||||
*
|
||||
* n = AttrIndex[2:0]
|
||||
*
|
||||
* n MAIR
|
||||
* 000 00000000 Strongly-ordered
|
||||
* 001 01000100 Normal memory, Inner & Outer Non-cacheable
|
||||
* 010 10101010 Normal memory, Write-Through, Read-Allocate
|
||||
* 011 11101110 Normal memory, Write-Back, Read-Allocate
|
||||
* 100 00000100 Device memory
|
||||
*/
|
||||
|
||||
#define MMU_MAIR0_VALUE 0xEEAA4400
|
||||
#define MMU_MAIR1_VALUE 0x00000004
|
||||
|
||||
#define MMU_STATE_AI_STRONGLY_ORDERED 0x0 /* n = 0b000, strongly ordered */
|
||||
#define MMU_STATE_STRONGLY_ORDERED ((MMU_STATE_AI_STRONGLY_ORDERED << 2) | \
|
||||
MMU_STATE_SHARED_OUTER)
|
||||
#define MMU_STATE_CACHEABLE_NOT MMU_STATE_STRONGLY_ORDERED
|
||||
|
||||
#define MMU_STATE_AI_DEVICE 0x4 /* n = 0b100 */
|
||||
#define MMU_STATE_DEVICE_SHARED ((MMU_STATE_AI_DEVICE << 2) | \
|
||||
MMU_STATE_SHARED_OUTER)
|
||||
|
||||
/* device always shared in LPAE */
|
||||
|
||||
#define MMU_STATE_DEVICE_NONSHARED MMU_STATE_DEVICE_SHARED
|
||||
|
||||
/* outer & inner write-thru cachable, write alloc */
|
||||
|
||||
#define MMU_STATE_AI_NORMAL_WRITETHROUGH 0x2 /* n = 0b010, Write-Through */
|
||||
#define MMU_STATE_NORMAL_WRITETHROUGH (MMU_STATE_AI_NORMAL_WRITETHROUGH << 2)
|
||||
#define MMU_STATE_CACHEABLE_WRITETHROUGH MMU_STATE_NORMAL_WRITETHROUGH
|
||||
|
||||
/* outer & inner write-back cachable, write alloc */
|
||||
|
||||
#define MMU_STATE_AI_NORMAL_WRITEBACK 0x3 /* n = 0b011, Write-Back */
|
||||
#define MMU_STATE_NORMAL_WRITEBACK (MMU_STATE_AI_NORMAL_WRITEBACK << 2)
|
||||
#define MMU_STATE_CACHEABLE_COPYBACK MMU_STATE_NORMAL_WRITEBACK
|
||||
#define MMU_STATE_COPYBACK_ALLOC MMU_STATE_NORMAL_WRITEBACK
|
||||
|
||||
/* outer & inner Non-cachable */
|
||||
|
||||
#define MMU_STATE_AI_NORMAL_NONCACHEABLE 0x1 /* n = 0b001, Non-cacheable */
|
||||
#define MMU_STATE_NORMAL_NONCACHEABLE (MMU_STATE_AI_NORMAL_NONCACHEABLE << 2)
|
||||
|
||||
/*
|
||||
* Set the default state to be copyback.
|
||||
*/
|
||||
|
||||
#define MMU_STATE_CACHEABLE MMU_STATE_CACHEABLE_COPYBACK
|
||||
|
||||
/*
|
||||
* Shared memory attribute -
|
||||
* accessible by multiple processors or bus masters and must be kept coherent
|
||||
*/
|
||||
|
||||
#define MMU_STATE_SHARED_OUTER (0x2 << 8) /* Outer Shareable */
|
||||
#define MMU_STATE_SHARED_INNER (0x3 << 8) /* Inner Shareable */
|
||||
|
||||
#define MMU_STATE_SHARED MMU_STATE_SHARED_INNER
|
||||
|
||||
#define MMU_STATE_WRITETHROUGH_SHARED \
|
||||
(MMU_STATE_CACHEABLE_WRITETHROUGH | MMU_STATE_SHARED)
|
||||
#define MMU_STATE_COPYBACK_SHARED \
|
||||
(MMU_STATE_CACHEABLE_COPYBACK | MMU_STATE_SHARED)
|
||||
|
||||
/*
|
||||
* A memory region with a resultant memory type attribute of Normal, and a
|
||||
* resultant cacheability attribute of Inner Non-cacheable, Outer Non-cacheable,
|
||||
* must have a resultant shareability attribute of Outer Shareable, otherwise
|
||||
* shareability is UNPREDICTABLE.
|
||||
*/
|
||||
|
||||
#define MMU_STATE_NONCACHEABLE_SHARED \
|
||||
(MMU_STATE_NORMAL_NONCACHEABLE | \
|
||||
MMU_STATE_SHARED_OUTER)
|
||||
|
||||
/*
|
||||
* Global memory attribute -
|
||||
* not-Global causes ASID to be associated with address translation
|
||||
*/
|
||||
|
||||
#define MMU_STATE_NOT_GLOBAL 0x00000800 /* not-Global, bit[11] */
|
||||
|
||||
/*
|
||||
* Architecture-specific attributes
|
||||
*
|
||||
* The following ARMv7-specific aliases are provided for ease of use.
|
||||
*
|
||||
* NOTE: MMU_ATTR_CACHE_GUARDED is used as MMU_ATTR_CACHE_IO (its former name).
|
||||
*/
|
||||
|
||||
/* Strongly Ordered - same as MMU_ATTR_CACHE_OFF for backward compatibility */
|
||||
|
||||
#define MMU_ATTR_STRONGLY_ORDERED (MMU_ATTR_CACHE_OFF)
|
||||
|
||||
/* Shared Device */
|
||||
|
||||
#define MMU_ATTR_DEVICE_SHARED_MSK (MMU_ATTR_CACHE_MSK)
|
||||
#define MMU_ATTR_DEVICE_SHARED (MMU_ATTR_CACHE_GUARDED | MMU_ATTR_CACHE_OFF | \
|
||||
MMU_ATTR_CACHE_COHERENCY)
|
||||
#define MMU_ATTR_BUFFERABLE MMU_ATTR_DEVICE_SHARED /* backward compatible */
|
||||
|
||||
/* Normal, Noncacheable memory */
|
||||
|
||||
#define MMU_ATTR_NORMAL_NONCACHEABLE_MSK (MMU_ATTR_CACHE_MSK)
|
||||
#define MMU_ATTR_NORMAL_NONCACHEABLE (MMU_ATTR_CACHE_OFF)
|
||||
#define MMU_ATTR_NORMAL_NONCACHEABLE_SHARED (MMU_ATTR_NORMAL_NONCACHEABLE | \
|
||||
MMU_ATTR_CACHE_COHERENCY)
|
||||
|
||||
/* Normal, Inner Cache Write-Back, Write Allocate */
|
||||
|
||||
#define MMU_ATTR_WRITEALLOCATE_MSK MMU_ATTR_CACHE_MSK
|
||||
#define MMU_ATTR_WRITEALLOCATE MMU_ATTR_CACHE_COPYBACK
|
||||
#define MMU_ATTR_WRITEALLOCATE_SHARED (MMU_ATTR_WRITEALLOCATE | \
|
||||
MMU_ATTR_CACHE_COHERENCY)
|
||||
|
||||
/* MMU Control Register bit allocations */
|
||||
|
||||
#define MMUCR_M_ENABLE (1<<0) /* MMU enable */
|
||||
#define MMUCR_A_ENABLE (1<<1) /* Address alignment fault enable */
|
||||
#define MMUCR_C_ENABLE (1<<2) /* (data) cache enable */
|
||||
#define MMUCR_W_ENABLE (1<<3) /* write buffer enable */
|
||||
#define MMUCR_PROG32 (1<<4) /* PROG32 */
|
||||
#define MMUCR_DATA32 (1<<5) /* DATA32 */
|
||||
#define MMUCR_L_ENABLE (1<<6) /* Late abort on earlier CPUs */
|
||||
#define MMUCR_BIGEND (1<<7) /* Big-endian (=1), little-endian (=0) */
|
||||
#define MMUCR_SYSTEM (1<<8) /* System bit, modifies MMU protections */
|
||||
#define MMUCR_ROM (1<<9) /* ROM bit, modifies MMU protections */
|
||||
#define MMUCR_F (1<<10) /* Should Be Zero */
|
||||
#define MMUCR_Z_ENABLE (1<<11) /* Branch prediction enable on 810 */
|
||||
#define MMUCR_I_ENABLE (1<<12) /* Instruction cache enable */
|
||||
#define MMUCR_V_ENABLE (1<<13) /* Exception vectors remap to 0xFFFF0000 */
|
||||
#define MMUCR_ALTVECT MMUCR_V_ENABLE /* alternate vector select */
|
||||
#define MMUCR_RR_ENABLE (1<<14) /* Round robin cache replacement enable */
|
||||
#define MMUCR_ROUND_ROBIN MMUCR_RR_ENABLE /* round-robin placement */
|
||||
#define MMUCR_DISABLE_TBIT (1<<15) /* disable TBIT */
|
||||
#define MMUCR_ENABLE_DTCM (1<<16) /* Enable Data TCM */
|
||||
#define MMUCR_HA_ENABLE (1<<17) /* Hardware Access flag enable */
|
||||
#define MMUCR_ENABLE_ITCM (1<<18) /* Enable Instruction TCM */
|
||||
#define MMUCR_UNALIGNED_ENABLE (1<<22) /* Enable unaligned access */
|
||||
#define MMUCR_EXTENDED_PAGE (1<<23) /* Use extended PTE format */
|
||||
#define MMUCR_VECTORED_INTERRUPT (1<<24) /* Enable VIC Interface */
|
||||
#define MMUCR_EE (1<<25) /* Exception Endianness bit */
|
||||
#define MMUCR_THUMB_EXCEPTIONS (1<<30) /* Exceptions are Thumb */
|
||||
|
||||
/* MMU TTBR 64 bit register fields for LPAE */
|
||||
|
||||
#define MMU_TTBR64_BA_MASK MAKE_MASK_64(39, 12)
|
||||
#define MMU_TTBR64_ASID_SHIFT 48
|
||||
|
||||
/* MMU TTBCR register fields for LPAE */
|
||||
|
||||
#define MMU_TTBCR_IRGN_NC (0 << 8)
|
||||
#define MMU_TTBCR_IRGN_WBWA (1 << 8)
|
||||
#define MMU_TTBCR_IRGN_WT (2 << 8)
|
||||
#define MMU_TTBCR_IRGN_WB (3 << 8)
|
||||
#define MMU_TTBCR_ORGN_NC (0 << 10)
|
||||
#define MMU_TTBCR_ORGN_OC_WBWA (1 << 10)
|
||||
#define MMU_TTBCR_ORGN_OC_WT (2 << 10)
|
||||
#define MMU_TTBCR_ORGN_OC_WB (3 << 10)
|
||||
#define MMU_TTBCR_S (3 << 12)
|
||||
#define MMU_TTBCR_S_OUTER (2 << 12)
|
||||
#define MMU_TTBCR_EAE (1 << 31)
|
||||
|
||||
#ifdef _WRS_CONFIG_ENABLE_CACHED_PAGE_TBL
|
||||
/* PTWs cacheable, inner WBWA not shareable, outer WBWA not shareable */
|
||||
|
||||
#define MMU_TTBCR_FLAGS_UP (MMU_TTBCR_IRGN_WBWA | MMU_TTBCR_ORGN_OC_WBWA)
|
||||
|
||||
/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
|
||||
|
||||
#define MMU_TTBCR_FLAGS_SMP (MMU_TTBCR_IRGN_WBWA | MMU_TTBCR_S | \
|
||||
MMU_TTBCR_ORGN_OC_WBWA)
|
||||
#else /* !_WRS_CONFIG_ENABLE_CACHED_PAGE_TBL */
|
||||
/* PTWs not cacheable, inner not shareable, outer not shareable */
|
||||
|
||||
#define MMU_TTBCR_FLAGS_UP (MMU_TTBCR_IRGN_NC | MMU_TTBCR_ORGN_NC)
|
||||
|
||||
/* PTWs not cacheable, inner shareable, outer not shareable */
|
||||
|
||||
#define MMU_TTBCR_FLAGS_SMP (MMU_TTBCR_ORGN_NC | MMU_TTBCR_S | \
|
||||
MMU_TTBCR_ORGN_NC)
|
||||
#endif /* _WRS_CONFIG_ENABLE_CACHED_PAGE_TBL */
|
||||
|
||||
/* typedefs */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
|
||||
/* little-endian */
|
||||
|
||||
/* Level 1/2 page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* descriptor type, 0b11 => page table */
|
||||
UINT pad1 : 10; /* Ignored */
|
||||
UINT addr : 20; /* base address of page table */
|
||||
UINT addr40 : 8; /* base address of page table */
|
||||
UINT pad2 : 12; /* UNK/SBZP */
|
||||
UINT pad3 : 7; /* Ignored */
|
||||
UINT pxn : 1; /* PXNTable */
|
||||
UINT xn : 1; /* XNTable */
|
||||
UINT ap : 2; /* APTable */
|
||||
UINT ns : 1; /* NSTable */
|
||||
} PAGE_DESC_FIELD;
|
||||
|
||||
/* Layout of Page Table Entries (PTEs) */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* page type, 0b11 => page */
|
||||
UINT ai : 3; /* AttrIndx[2:0] */
|
||||
UINT ns : 1; /* non-secure bit */
|
||||
UINT ap : 2; /* AP[2:1], access permission */
|
||||
UINT sh : 2; /* SH[1:0], shareability field */
|
||||
UINT af : 1; /* access flag */
|
||||
UINT ng : 1; /* not global bit */
|
||||
UINT addr : 20; /* phys address */
|
||||
UINT addr40 : 8; /* phys address */
|
||||
UINT pad1 : 12; /* UNK/SBZP */
|
||||
UINT ch : 1; /* contiguous hint */
|
||||
UINT pxn : 1; /* privileged execute-never bit */
|
||||
UINT xn : 1; /* execute-never bit */
|
||||
UINT pad2 : 9; /* ignored */
|
||||
} PTE_FIELD;
|
||||
|
||||
#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
|
||||
|
||||
/* big-endian */
|
||||
|
||||
#error "LPAE for big-endian not support yet."
|
||||
|
||||
#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
|
||||
|
||||
/* First/second level descriptor access */
|
||||
|
||||
typedef union
|
||||
{
|
||||
PAGE_DESC_FIELD fields;
|
||||
UINT bits[2];
|
||||
UINT64 bits64;
|
||||
} MMU_LEVEL_1_DESC, MMU_LEVEL_2_DESC;
|
||||
|
||||
/* Third level descriptor access */
|
||||
|
||||
typedef union
|
||||
{
|
||||
PTE_FIELD fields;
|
||||
UINT bits[2];
|
||||
UINT64 bits64;
|
||||
} PTE;
|
||||
|
||||
/*
|
||||
* Structure for MMU translation table access - normally used to get a pointer
|
||||
* to the first-level translation table.
|
||||
*/
|
||||
|
||||
typedef struct mmuTransTblStruct
|
||||
{
|
||||
MMU_LEVEL_1_DESC *pLevel1Table; /* active MMU table */
|
||||
VX_MUTEX_SEMAPHORE(mmuTransTblSem); /* MMU tables' semaphore */
|
||||
UINT32 lockCnt; /* lock count */
|
||||
atomic_t lockOwner; /* lock owner */
|
||||
UINT8 asid; /* ASID/context id */
|
||||
} MMU_TRANS_TBL;
|
||||
|
||||
/* function declarations */
|
||||
|
||||
/* Externally visible mmuLib, mmuMapLib and mmuALib2 routines */
|
||||
|
||||
IMPORT UINT32 mmuReadId (void);
|
||||
IMPORT PHYS_ADDR mmuVirtToPhys (VIRT_ADDR addr);
|
||||
IMPORT VIRT_ADDR mmuPhysToVirt (PHYS_ADDR addr);
|
||||
|
||||
IMPORT UINT32 (* mmuCrGet) (void);
|
||||
IMPORT void (* mmuModifyCr) (UINT32 value, UINT32 mask);
|
||||
IMPORT UINT32 mmuHardCrGet (void);
|
||||
IMPORT void mmuModifyHardCr (UINT32 value, UINT32 mask);
|
||||
|
||||
IMPORT UINT32 (* _func_mmuFaultAddrGet) (void);
|
||||
IMPORT UINT32 (* _func_mmuFaultStatusGet) (void);
|
||||
IMPORT UINT32 (* _func_mmuIFaultStatusGet) (void);
|
||||
IMPORT UINT32 mmuIFsrGet (void);
|
||||
IMPORT UINT32 mmuFarGet (void);
|
||||
IMPORT UINT32 mmuFsrGet (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmmuArmLpaeLibh */
|
||||
@@ -0,0 +1,78 @@
|
||||
/* mmuArmManzano.h - Manzano (XScale varient) MMU library header file */
|
||||
|
||||
/* Copyright (c) 1998-2006 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement. No license to Wind River intellectual property rights
|
||||
* is granted herein. All rights not licensed by Wind River are reserved
|
||||
* by Wind River.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
012,22feb06,m_h Manzano Support
|
||||
011,25jan06,m_h created.
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuArmManzanoLibh
|
||||
#define __INCmmuArmManzanoLibh
|
||||
|
||||
/* Enable support for supersection descriptors */
|
||||
#undef INCLUDE_MMU_SUPERSECTION_SUPPORT
|
||||
#define INCLUDE_MMU_SUPERSECTION_SUPPORT
|
||||
|
||||
#ifdef INCLUDE_MMU_SUPERSECTION_SUPPORT
|
||||
/* Supersections require "section" functionality */
|
||||
#undef INCLUDE_MMU_SECTION_SUPPORT
|
||||
#define INCLUDE_MMU_SECTION_SUPPORT
|
||||
#endif /* INCLUDE_MMU_SUPERSECTION_SUPPORT */
|
||||
|
||||
|
||||
#undef INCLUDE_MMU_SBIT_SUPPORT
|
||||
#define INCLUDE_MMU_SBIT_SUPPORT
|
||||
|
||||
#include "arch/arm/mmuArmXSCALELib.h"
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
|
||||
|
||||
IMPORT void mmuMANZANOLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
IMPORT void mmuMANZANOTtbrSet (MMU_LEVEL_1_DESC *);
|
||||
IMPORT MMU_LEVEL_1_DESC * mmuMANZANOTtbrGet ( void);
|
||||
IMPORT void mmuMANZANODacrSet (UINT32 dacrVal);
|
||||
IMPORT void mmuMANZANOTLBIDFlushEntry (void *addr);
|
||||
IMPORT void mmuMANZANOTLBIDFlushAll (void);
|
||||
IMPORT void mmuMANZANOAEnable (UINT32 cacheState);
|
||||
IMPORT void mmuMANZANOADisable (void);
|
||||
IMPORT STATUS mmuMANZANOPBitSet ( void * virtAddr, UINT32 size);
|
||||
IMPORT STATUS mmuMANZANOPBitClear ( void * virtAddr, UINT32 size);
|
||||
IMPORT STATUS mmuMANZANOPBitGet ( void * virtAddr );
|
||||
IMPORT STATUS mmuMANZANOAcrGet (void );
|
||||
IMPORT void mmuMANZANOAcrSet (UINT32 acrVal);
|
||||
|
||||
#else /* __STDC__ */
|
||||
|
||||
IMPORT void mmuMANZANOLibInstall ();
|
||||
IMPORT void mmuMANZANOTtbrSet ();
|
||||
IMPORT MMU_LEVEL_1_DESC * mmuMANZANOTtbrGet ();
|
||||
IMPORT void mmuMANZANODacrSet ();
|
||||
IMPORT void mmuMANZANOTLBIDFlushEntry ();
|
||||
IMPORT void mmuMANZANOTLBIDFlushAll ();
|
||||
IMPORT void mmuMANZANOAEnable ();
|
||||
IMPORT void mmuMANZANOADisable ();
|
||||
IMPORT STATUS mmuMANZANOPBitSet ();
|
||||
IMPORT STATUS mmuMANZANOPBitClear ();
|
||||
IMPORT STATUS mmuMANZANOPBitGet ();
|
||||
IMPORT STATUS mmuMANZANOAcrGet ();
|
||||
IMPORT void mmuMANZANOAcrSet ();
|
||||
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* __INCmmuArmManzanoLibh */
|
||||
@@ -0,0 +1,611 @@
|
||||
/* mmuArmPalLib.h - ARM MMU library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996-2007, 2009-2010, 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
02i,02mar12,rec WIND00318272 - POSIX signals conformance
|
||||
02h,09jan12,rec WIND00196578 - remove unused reference _func_armPageSource
|
||||
02g,29apr10,pad Moved extern C statement after include statements.
|
||||
02f,03nov09,j_b add INCLUDE_MMU_SUBPAGE_SUPPORT, undef INCLUDE_MMU_TEX_SUPPORT
|
||||
02e,23oct07,to added lockCnt and lockOwner to MMU_TRANS_TBL
|
||||
02d,21sep07,to define MMU_PAGE_SIZE_SHIFT
|
||||
02c,21sep07,j_b add _func_mmuFaultAddrGet prototype
|
||||
02b,09feb07,j_b add mmuFarGet prototype
|
||||
02a,20sep06,j_b add page optimization support
|
||||
01z,12sep06,m_h fix vert-to-phys translation problem in upper bits
|
||||
WIND00059266
|
||||
01y,28mar06,m_h Coherancy Support (s-bit)
|
||||
01x,01mar06,m_h Section Support in non-XScale ARM
|
||||
01w,03jan06,m_h Manzano Support
|
||||
01v,24jun05,scm correct PAGE_DESC_FIELD for missing BE pad3 field, (SPR 110348)
|
||||
01u,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01t,31jan05,jb Adding OTHER_SECT_DESC to resolve bsp reference
|
||||
01s,09dec04,jb Palifying mmu, extracted from mmuArmLib.h, 01r
|
||||
*/
|
||||
|
||||
/*
|
||||
History from mmuArmLib.h
|
||||
01r,10aug04,scm adjust for removal of MPU support, add 926E...
|
||||
01q,18sep03,scm BASE 6 port...
|
||||
01p,04oct01,scm add extended small page table support for XScale...
|
||||
01o,23jul01,scm change XScale name to conform to coding standards...
|
||||
01n,11jul01,scm add support for XScale...
|
||||
01m,29mar01,jpd removed externs for mmyPhysToVirt & mmuVirtToPhys (SPR #63512).
|
||||
01l,19mar01,jpd redefine MMU_ATTR_BUFFERABLE and MMU_ATTR_CACHE_MINICACHE
|
||||
(SPR #64788).
|
||||
01k,16aug00,jpd no longer clear MMUCR Reserved/Should Be Zero bits (SPR #33608)
|
||||
01j,14jun00,jpd reworked MMU_STATE_WRITETHROUGH definition.
|
||||
01i,17feb00,jpd T3: prefixed defs with MMU_; added new defs; changed SR to 10.
|
||||
01h,07sep99,jpd added ARM740T, ARM920T support.
|
||||
01g,20jan99,cdp removed support for old ARM libraries;
|
||||
add prefix to MMU_IDs.
|
||||
01f,24nov98,jpd added ARM940T support, added other CPU ids; removed
|
||||
mmuIntLock/Unlock as intIFLock/Unlock to be used instead;
|
||||
cdp restructured for multiple cache/MMU libraries; big-endian.
|
||||
01e,09mar98,jpd added MMUCTR_ definitions for ARM810 and extra cache states.
|
||||
01d,20jan98,jpd added _func_armPhysToVirt() etc. function pointers.
|
||||
01c,17sep97,jpd added MMU_INIT_VALUE and mmuIntLock/Unlock definitions.
|
||||
01b,24jan97,jpd modified mmuAEnable definition.
|
||||
01a,09may96,cdp created.
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuArmPalLibh
|
||||
#define __INCmmuArmPalLibh
|
||||
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <memLib.h>
|
||||
#include <semLib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/*
|
||||
* MMUs are not fitted to all processors, and so the definitions below
|
||||
* should not need to be included for processors without MMUs.
|
||||
*/
|
||||
|
||||
#if (ARMMMU != ARMMMU_NONE)
|
||||
|
||||
/*
|
||||
* The page size we will use. Ignore the sub-page, Large Page and Tiny
|
||||
* Page features.
|
||||
*/
|
||||
|
||||
#define MMU_PAGE_SIZE 4096
|
||||
#define MMU_PAGE_SIZE_SHIFT 12
|
||||
|
||||
#undef INCLUDE_MMU_SUBPAGE_SUPPORT
|
||||
#define INCLUDE_MMU_SUBPAGE_SUPPORT
|
||||
|
||||
#undef INCLUDE_MMU_TEX_SUPPORT
|
||||
|
||||
/*
|
||||
* The amount described by a Level 1 Descriptor, which equals the smallest
|
||||
* amount of VM allocatable in VxWorks.
|
||||
*/
|
||||
|
||||
#define MMU_PAGE_BLOCK_SIZE 0x100000 /* 1 MByte */
|
||||
|
||||
#define MMU_ADRS_TO_L1D_INDEX_SHIFT 20
|
||||
|
||||
#define MMU_PTE_INDEX_MASK 0x000FF000 /* extract PTE index from Virt Addr */
|
||||
#define MMU_PTE_INDEX_SHIFT 12 /* shift to make that into PTE index */
|
||||
|
||||
#define MMU_L1D_TO_BASE_SHIFT 10 /* to turn L1D to PT base addr */
|
||||
#define MMU_L1DSECTION_TO_BASE_SHIFT 20 /* L1D section to PT base addr */
|
||||
#define MMU_L1DSECTION_BA_MASK 0xFFF00000 /* phys bits 20-31 */
|
||||
|
||||
#define MMU_L1DSSECTIONLO_TO_BASE_SHIFT 24 /* bits 24-31 of supersection */
|
||||
#define MMU_L1DSSECTIONHI_TO_BASE_SHIFT 32 /* bits 32-35 of supersection */
|
||||
#define MMU_L1DSSECTIONLO_BA_MASK 0xFF000000 /* phys bits 24-31 */
|
||||
#define MMU_L1DSSECTIONHI_BA_MASK 0x00F00000 /* phys bits 32-35 */
|
||||
|
||||
#define MMU_ADDR_PI_MASK 0x00000FFF /* extract page index from Virt Addr */
|
||||
#define MMU_PTE_BA_MASK 0xFFFFF000 /* extract phys base address from PTE */
|
||||
|
||||
#define MMU_ADDR_SI_MASK 0x000FFFFF /* extr section index from Virt Addr */
|
||||
#define MMU_PTE_SECA_MASK 0xFFF00000 /* extract section base from L1 desc */
|
||||
|
||||
#define MMU_ADDR_SSI_MASK 0x00FFFFFF /* supersection index from virt */
|
||||
#define MMU_PTE_SSECA_MASK 0xFF000000 /* supersection base from L1 desc */
|
||||
#define MMU_PTE_SSECAX_MASK 0x00F00000 /* supersection extended bits L1 */
|
||||
#define MMU_PTE_SSECAX_SHIFT 12 /* supersection extended bits L1 */
|
||||
|
||||
#define MMU_PTE_TYPE_MASK 0x00000003 /* bits [0:1] */
|
||||
#define MMU_L1PD_PTE_MASK 0xFFFFFC00 /* extract phys PTE addr from L1PD */
|
||||
#define MMU_L1PD_TYPE_MASK 0x00000003 /* type bits [0:1] */
|
||||
#define MMU_L1PD_CB_MASK 0x0000000C /* CB bits [3:2] */
|
||||
#define MMU_L1PD_AP_MASK 0x00000C00 /* AP bits [10:11] */
|
||||
#define MMU_L1PD_P_MASK 0x00000200 /* P bit [9] */
|
||||
#define MMU_L1PD_TEX_MASK 0x00007000 /* TEX bits [14:12] */
|
||||
#define MMU_L1PD_S_MASK 0x00010000 /* S bit (coherancy) [16] */
|
||||
|
||||
#define MMU_PTE_SECT_CB_MASK 0x0000000C /* CB bits [3:2] */
|
||||
#define MMU_PTE_SECT_AP_MASK 0x00000030 /* AP bits [5:4] */
|
||||
#define MMU_PTE_SECT_TEX_MASK 0x000001C0 /* TEX bits [8:6] */
|
||||
#define MMU_PTE_SECT_S_MASK 0x00000200 /* S-bit (coherancy) [9] */
|
||||
|
||||
#define MMU_L1L2_SECT_CB_SHIFT 0 /* CB shift convert L1 to L2 */
|
||||
#define MMU_L1L2_SECT_AP_SHIFT 6 /* AP shift convert L1 to L2 */
|
||||
#define MMU_L1L2_SECT_TEX_SHIFT 6 /* TEX shift convert L1 to L2 */
|
||||
#define MMU_L1L2_SECT_S_SHIFT 7 /* S-bit shift convert L1 to L2 */
|
||||
|
||||
#define MMU_PTE_SSECT_TYPE 0x00040000 /* supersection bit [18] */
|
||||
#define MMU_PTE_SECT_TYPE_MASK 0x00040000 /* which type of section? */
|
||||
|
||||
#define MMU_NUM_VM_PAGES_IN_A_SECT 0x100
|
||||
#define MMU_NUM_VM_PAGES_IN_A_SSECT 0x1000
|
||||
#define MMU_NUM_SECTS_IN_A_SSECT 0x10 /* 16 sections/supersection */
|
||||
#define MMU_SECT_SIZE 0x100000 /* section = 1MB */
|
||||
#define MMU_SSECT_SIZE 0x1000000 /* supersection = 16MB */
|
||||
|
||||
#define MMU_L1PD_AP_SHIFT 10
|
||||
#define MMU_L1PD_CB_SHIFT 2
|
||||
#define MMU_L1PD_P_SHIFT 9
|
||||
#define MMU_L1PD_S_SHIFT 16
|
||||
|
||||
#define MMU_L1PD_DOMAIN_MASK 0x000001E0 /* domain bits 5-8 */
|
||||
#define MMU_L1PD_DOMAIN_SHIFT 5 /* shift to make domain field in L1PD */
|
||||
|
||||
/*
|
||||
* The Domain Access Control Register specifies the way in which access
|
||||
* rights are treated for each of sixteen domains. For each domain the
|
||||
* current state can be:
|
||||
*
|
||||
* 00 no access: all accesses generate aborts
|
||||
* 01 client: access rights specified in page tables are checked.
|
||||
* 10 reserved
|
||||
* 11 manager: accesses not checked against page tables: all access allowed.
|
||||
*/
|
||||
|
||||
#define MMU_DACR_VAL_NORMAL 1 /* client of 0 */
|
||||
#define MMU_DACR_VAL_UNPROTECT 0x03 /* manager of 0 */
|
||||
|
||||
/* Level 1 Descriptor types */
|
||||
|
||||
#define MMU_DESC_TYPE_FAULT 0 /* any access will cause a fault */
|
||||
#define MMU_DESC_TYPE_PAGE 1
|
||||
#define MMU_DESC_TYPE_SECTION 2
|
||||
|
||||
#define MMU_DEF_L1_PAGE 0x00000011 /* domain zero, Page descriptor */
|
||||
|
||||
/*
|
||||
* Section descriptors, such as might be used to set up an intermediate
|
||||
* set of page tables on processors such as SA-1100/SA-1500 where this
|
||||
* needs to be done from BSP initialization, before vm(Base)Lib sets up
|
||||
* a proper set of page tables.
|
||||
*/
|
||||
|
||||
#define MMU_RAM_SECT_DESC 0xC1E /* R/W cacheable bufferable domain 0 */
|
||||
#define MMU_MINICACHE_SECT_DESC 0xC1A /* R/W C+ B- domain 0 */
|
||||
#define MMU_OTHER_SECT_DESC 0xC12 /* R/W C- B- domain 0 */
|
||||
|
||||
/* Level 2 Descriptor or Page Table Entry (PTE) types */
|
||||
|
||||
#define MMU_PTE_TYPE_FAULT 0 /* any access will cause a fault */
|
||||
#define MMU_PTE_TYPE_LG_PAGE 1 /* Large page descriptor */
|
||||
#define MMU_PTE_TYPE_SM_PAGE 2 /* Small page descriptor */
|
||||
#define MMU_PTE_TYPE_EX_PAGE 3 /* Extended page descriptor */
|
||||
|
||||
/*
|
||||
* The Translation Table Base register (TTBR) points to a table of Level 1
|
||||
* Descriptors. these are either Invalid Section descriptors, Section
|
||||
* Descriptors, or Page Table Descriptors. If Page Table Descriptors, they
|
||||
* each point to a table of Level 2 Page Descriptors, or Page Table Entries
|
||||
* (PTEs).
|
||||
* The 32-bit (virtual) address space allows for 4096 M. Each Level 1
|
||||
* Descriptor describes a 1 M area of memory. There are therefore 4096 Level
|
||||
* 1 Descriptors, and each table of 256 Level 2 Page Descriptors (PTEs)
|
||||
* describes 256 4 kbyte pages.
|
||||
*/
|
||||
|
||||
#define MMU_NUM_L1_DESCS 4096
|
||||
#define MMU_NUM_L2_DESCS 256
|
||||
#define MMU_L1_TABLE_SIZE (MMU_NUM_L1_DESCS * sizeof(MMU_LEVEL_1_DESC))
|
||||
|
||||
/* No. of pages a Level 1 Descriptor table takes up */
|
||||
|
||||
#define MMU_L1_DESC_PAGES (MMU_L1_TABLE_SIZE / MMU_PAGE_SIZE)
|
||||
|
||||
/* Size of a Page Table */
|
||||
|
||||
#define MMU_PAGE_TABLE_SIZE (MMU_NUM_L2_DESCS * sizeof(PTE))
|
||||
|
||||
/* Section and supersection L1 definitions follow */
|
||||
|
||||
#undef MMU_DEF_L1_SECTION_PAGE
|
||||
#define MMU_DEF_L1_SECTION_PAGE 0x00000002 /* Section page descriptor */
|
||||
|
||||
#undef MMU_DEF_L1_SUPERSECTION_PAGE
|
||||
#define MMU_DEF_L1_SUPERSECTION_PAGE 0x00040002 /* supersection */
|
||||
|
||||
#undef MMU_DEF_L1_SECTION_PAGE_MASK
|
||||
#define MMU_DEF_L1_SECTION_PAGE_MASK 0x00040003 /* mask */
|
||||
|
||||
#undef MMU_STATE_SECTION_MASK_WRITABLE
|
||||
#define MMU_STATE_SECTION_MASK_WRITABLE 0x00000030 /* All APn bits */
|
||||
|
||||
/*
|
||||
* Architecture-dependent MMU states. These are states settable for pages and
|
||||
* here they correspond to settings in the Page Table Entries (PTEs).
|
||||
*
|
||||
* We set Valid/Invalid by setting a Fault second-level descriptor rather
|
||||
* than by using the Access Permissions within a small page second-level
|
||||
* descriptor. This is because we will want to use the Access Permissions to
|
||||
* control supervisor mode access and we cannot then use the AP bits
|
||||
* to disallow access as the SR bits in the MMU Control register must be set
|
||||
* to 10 in order to control read/write access from Supervisor mode.
|
||||
*/
|
||||
|
||||
#define MMU_STATE_INVALID_STATE 0xFFFFFFFF
|
||||
|
||||
#define MMU_STATE_MASK_VALID 0x03 /* 2nd level desc type */
|
||||
|
||||
#define MMU_STATE_MASK_WRITABLE 0x00000FF0 /* All APn bits */
|
||||
|
||||
#define MMU_STATE_MASK_CACHEABLE 0x0000000C /* CB bits */
|
||||
#define MMU_STATE_MASK_BUFFERABLE 0x00000004
|
||||
|
||||
#define MMU_STATE_MASK_MEM_COHERENCY 0x00000200 /* Manzano S-bit */
|
||||
#define MMU_STATE_MEM_COHERENCY 0x00000200 /* Manzano S-bit */
|
||||
|
||||
#ifdef INCLUDE_MMU_SBIT_SUPPORT
|
||||
#define MMU_STATE_MASK_CACHEABLE_S 0x0000020C /* CB&S bits */
|
||||
#else /*INCLUDE_MMU_SBIT_SUPPORT*/
|
||||
#define MMU_STATE_MASK_CACHEABLE_S 0x0000000C /* CB bits */
|
||||
#endif /*INCLUDE_MMU_SBIT_SUPPORT*/
|
||||
|
||||
#define MMU_STATE_VALID MMU_PTE_TYPE_SM_PAGE /* set to page type */
|
||||
#define MMU_STATE_VALID_NOT MMU_PTE_TYPE_FAULT /* set to type fault */
|
||||
|
||||
#define MMU_STATE_WRITABLE 0x00000FF0 /* APn bits to 11 */
|
||||
|
||||
#define MMU_STATE_WRITABLE_NOT 0x0 /* APn bits to 00 */
|
||||
|
||||
#define MMU_STATE_MASK_PROTECTION 0x00000FF0 /* APn bits */
|
||||
|
||||
#define MMU_STATE_SUP_RO 0x00000000 /* AP: 00 */
|
||||
#define MMU_STATE_SUP_RW 0x00000550 /* AP: 01 */
|
||||
#define MMU_STATE_USR_RO_SUP_RW 0x00000AA0 /* AP: 10 */
|
||||
#define MMU_STATE_USR_RW_SUP_RW 0x00000FF0 /* AP: 11 */
|
||||
|
||||
#define MMU_STATE_AP_SUP_RO 0x0 /* AP field: 00 */
|
||||
#define MMU_STATE_AP_SUP_RW 0x1 /* AP field: 01 */
|
||||
#define MMU_STATE_AP_USR_RO_SUP_RW 0x2 /* AP field: 10 */
|
||||
#define MMU_STATE_AP_USR_RW_SUP_RW 0x3 /* AP field: 11 */
|
||||
|
||||
/* Write-through mode is only available on some CPUs */
|
||||
|
||||
#define MMU_STATE_CACHEABLE_WRITETHROUGH 0x8
|
||||
|
||||
#define MMU_STATE_CACHEABLE_COPYBACK 0xC /* write back */
|
||||
|
||||
/*
|
||||
* Set the default state to be copyback. CACHEABLE_WRITETHROUGH can also be
|
||||
* selected on those cache designs that permit it.
|
||||
*/
|
||||
|
||||
#define MMU_STATE_CACHEABLE MMU_STATE_CACHEABLE_COPYBACK
|
||||
|
||||
#define MMU_STATE_CACHEABLE_NOT 0x0
|
||||
|
||||
#define MMU_STATE_BUFFERABLE 0x4 /* bufferable, not cacheable */
|
||||
#define MMU_STATE_BUFFERABLE_NOT 0x0 /* will also set not cacheable*/
|
||||
|
||||
/*
|
||||
* Under VxWorks AE 1.1, when setting either of the attributes SPL_0 or SPL_1,
|
||||
* using vmPgAttrSet(), it is necessary to:
|
||||
*
|
||||
* 1. specify MMU_ATTR_SPL_MSK ORred with MMU_ATTR_CACHE_MSK in the mask
|
||||
* argument to the routine, and:
|
||||
* 2. specify the appropriate cache state ORred in to the state argument
|
||||
* to the routine.
|
||||
*
|
||||
* So, to set a page as bufferable not cacheable, it is necessary to
|
||||
* specify both MMU_ATTR_SPL_0 and specify MMU_ATTR_CACHE_OFF in the
|
||||
* state argument. To mark a page as cacheable in the minicache,
|
||||
* MMU_ATTR_SPL_1 and MMU_ATTR_CACHE_COPYBACK must be specified in the
|
||||
* state argument. In both cases, specify MMU_ATTR_SPL_MSK ORred with
|
||||
* MMU_ATTR_CACHE_MSK in the mask argument.
|
||||
*
|
||||
* These restrictions were not present in VxWorks AE 1.0.
|
||||
*
|
||||
* To "unset" the special attibutes SPL_0 or SPL_1, specify
|
||||
* MMU_ATTR_CACHE_MSK in the mask parameter (without MMU_ATTR_SPL_MSK),
|
||||
* and specify the cacheability required in the state argument.
|
||||
*
|
||||
* We provide the following aliases on ARM, to make life easier.
|
||||
*/
|
||||
|
||||
#define MMU_ATTR_BUFFERABLE (MMU_ATTR_SPL_0)
|
||||
|
||||
/* MMU Control Register bit allocations */
|
||||
|
||||
#define MMUCR_M_ENABLE (1<<0) /* MMU enable */
|
||||
#define MMUCR_A_ENABLE (1<<1) /* Address alignment fault enable */
|
||||
#define MMUCR_C_ENABLE (1<<2) /* (data) cache enable */
|
||||
#define MMUCR_W_ENABLE (1<<3) /* write buffer enable */
|
||||
#define MMUCR_PROG32 (1<<4) /* PROG32 */
|
||||
#define MMUCR_DATA32 (1<<5) /* DATA32 */
|
||||
#define MMUCR_L_ENABLE (1<<6) /* Late abort on earlier CPUs */
|
||||
#define MMUCR_BIGEND (1<<7) /* Big-endian (=1), little-endian (=0) */
|
||||
#define MMUCR_SYSTEM (1<<8) /* System bit, modifies MMU protections */
|
||||
#define MMUCR_ROM (1<<9) /* ROM bit, modifies MMU protections */
|
||||
#define MMUCR_F (1<<10) /* Should Be Zero */
|
||||
#define MMUCR_Z_ENABLE (1<<11) /* Branch prediction enable on 810 */
|
||||
#define MMUCR_I_ENABLE (1<<12) /* Instruction cache enable */
|
||||
#define MMUCR_V_ENABLE (1<<13) /* Exception vectors remap to 0xFFFF0000 */
|
||||
#define MMUCR_ALTVECT MMUCR_V_ENABLE /* alternate vector select */
|
||||
#define MMUCR_RR_ENABLE (1<<14) /* Round robin cache replacement enable */
|
||||
#define MMUCR_ROUND_ROBIN MMUCR_RR_ENABLE /* round-robin placement */
|
||||
#define MMUCR_DISABLE_TBIT (1<<15) /* disable TBIT */
|
||||
|
||||
/* The following definitions are now deprecated and may be withdrawn */
|
||||
|
||||
#ifdef MMU_ARM_ALLOW_DEPRECATED
|
||||
|
||||
#define LEVEL_1_DESC MMU_LEVEL_1_DESC
|
||||
#define PAGE_SIZE MMU_PAGE_SIZE
|
||||
#define PAGE_BLOCK_SIZE MMU_PAGE_BLOCK_SIZE
|
||||
#define PTE_INDEX_MASK MMU_PTE_INDEX_MASK
|
||||
#define PTE_INDEX_SHIFT MMU_PTE_INDEX_SHIFT
|
||||
#define L1D_TO_BASE_SHIFT MMU_L1D_TO_BASE_SHIFT
|
||||
#define ADDR_PI_MASK MMU_ADDR_PI_MASK
|
||||
#define NUM_L1_DESCS MMU_NUM_L1_DESCS
|
||||
#define NUM_L2_DESCS MMU_NUM_L2_DESCS
|
||||
#define L1_TABLE_SIZE MMU_L1_TABLE_SIZE
|
||||
#define L1_DESC_PAGES MMU_L1_DESC_PAGES
|
||||
#define PAGE_TABLE_SIZE MMU_PAGE_TABLE_SIZE
|
||||
#define DESC_TYPE_PAGE MMU_DESC_TYPE_PAGE
|
||||
#define DEF_L1_PAGE MMU_DEF_L1_PAGE
|
||||
#define PTE_TYPE_FAULT MMU_PTE_TYPE_FAULT
|
||||
#define PTE_TYPE_SM_PAGE MMU_PTE_TYPE_SM_PAGE
|
||||
#define RAM_SECT_DESC MMU_RAM_SECT_DESC
|
||||
#define MINICACHE_SECT_DESC MMU_MINICACHE_SECT_DESC
|
||||
#define OTHER_SECT_DESC MMU_OTHER_SECT_DESC
|
||||
|
||||
#else /* MMU_ARM_ALLOW_DEPRECATED */
|
||||
|
||||
/* Some BSPs still reference PAGE_SIZE */
|
||||
|
||||
#define PAGE_SIZE MMU_PAGE_SIZE
|
||||
|
||||
/* Some BSPs still reference OTHER_SECT_DESC */
|
||||
|
||||
#define OTHER_SECT_DESC MMU_OTHER_SECT_DESC
|
||||
|
||||
#endif /* MMU_ARM_ALLOW_DEPRECATED */
|
||||
|
||||
#define ADDR_TO_PAGE 12 /* shift phys address to PTE page base address */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* If using standard ARM MMU structures */
|
||||
#ifndef MMU_ARCHITECTURE_DEFINES_STRUCTURES
|
||||
|
||||
/* Default ARMARCH4/5 ARM MMU Structures */
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
|
||||
/* little-endian */
|
||||
|
||||
/* First level page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* descriptor type, 1 => page */
|
||||
UINT pad1 : 2; /* SBZ */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT pad3 : 1; /* SBZ */
|
||||
UINT addr : 22; /* base address of page table */
|
||||
} PAGE_DESC_FIELD;
|
||||
|
||||
/* First level "section" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
UINT bbit : 1; /* bufferable-bit */
|
||||
UINT cbit : 1; /* cacheable-bit */
|
||||
UINT pad1 : 1; /* SBO */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT tex : 3; /* AP */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT pad3 : 1; /* SBO */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT pad4 : 1; /* SBO */
|
||||
UINT addr : 12; /* base address of page table */
|
||||
} SECTION_DESC_FIELD;
|
||||
|
||||
/* First level "supersection" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
UINT bbit : 1; /* bufferable-bit */
|
||||
UINT cbit : 1; /* cacheable-bit */
|
||||
UINT pad1 : 1; /* SBO */
|
||||
UINT addrHi2: 4; /* phys address 39:36 */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT tex : 3; /* TEX */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT pad3 : 1; /* SBO */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT pad4 : 1; /* SBO */
|
||||
UINT addrHi : 4; /* phys address 35:32 */
|
||||
UINT addrLo : 8; /* phys address 31:24 */
|
||||
} SUPERSECTION_DESC_FIELD;
|
||||
|
||||
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* page type, 2 => small page */
|
||||
UINT cb : 2; /* cacheable/bufferable bits */
|
||||
UINT ap0 : 2; /* access permission, sub-page 0 */
|
||||
UINT ap1 : 2; /* access permission, sub-page 1 */
|
||||
UINT ap2 : 2; /* access permission, sub-page 2 */
|
||||
UINT ap3 : 2; /* access permission, sub-page 3 */
|
||||
UINT addr : 20; /* page base address */
|
||||
} PTE_FIELD;
|
||||
|
||||
#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
|
||||
|
||||
/* big-endian */
|
||||
|
||||
/* First level descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT addr : 22; /* descriptor type, 1 => page */
|
||||
UINT pad3 : 1; /* SBZ */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT pad1 : 2; /* SBZ */
|
||||
UINT type : 2; /* base address of page table */
|
||||
} PAGE_DESC_FIELD;
|
||||
|
||||
/* First level "section" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT addr : 12; /* base address of page table */
|
||||
UINT pad4 : 1; /* SBO */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT pad3 : 1; /* SBO */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT tex : 3; /* AP */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT pad1 : 1; /* SBO */
|
||||
UINT c : 1; /* c-bit */
|
||||
UINT b : 1; /* b-bit */
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
} SECTION_DESC_FIELD;
|
||||
|
||||
/* First level "supersection" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT addrLo : 8; /* phys address 31:24 */
|
||||
UINT addrHi : 4; /* phys address 35:32 */
|
||||
UINT pad4 : 1; /* SBO */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT pad3 : 1; /* SBO */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT tex : 3; /* AP */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT addrHi2: 4; /* phys address 39:36 */
|
||||
UINT pad1 : 1; /* SBO */
|
||||
UINT c : 1; /* c-bit */
|
||||
UINT b : 1; /* b-bit */
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
} SUPERSECTION_DESC_FIELD;
|
||||
|
||||
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT addr : 20; /* page base address */
|
||||
UINT ap3 : 2; /* access permission, sub-page 3 */
|
||||
UINT ap2 : 2; /* access permission, sub-page 2 */
|
||||
UINT ap1 : 2; /* access permission, sub-page 1 */
|
||||
UINT ap0 : 2; /* access permission, sub-page 0 */
|
||||
UINT cb : 2; /* cacheable/bufferable bits */
|
||||
UINT type : 2; /* page type, 2 => small page */
|
||||
} PTE_FIELD;
|
||||
|
||||
#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
|
||||
|
||||
/* First level descriptor access */
|
||||
|
||||
typedef union
|
||||
{
|
||||
PAGE_DESC_FIELD fields;
|
||||
SECTION_DESC_FIELD sectionFields;
|
||||
SUPERSECTION_DESC_FIELD supersectionFields;
|
||||
UINT32 bits;
|
||||
} MMU_LEVEL_1_DESC;
|
||||
|
||||
/* Second level descriptor access */
|
||||
|
||||
typedef union
|
||||
{
|
||||
PTE_FIELD fields;
|
||||
UINT32 bits;
|
||||
} PTE;
|
||||
|
||||
/*
|
||||
* Structure for MMU translation table access - normally used to get a pointer
|
||||
* to the first-level translation table.
|
||||
* To support page table optimization, a second first-level table and a
|
||||
* semaphore are needed.
|
||||
* The initial, unoptimized set of page tables will be set as the active
|
||||
* translation tables (via pLevel1Table) while optimization or deoptimization
|
||||
* is in progress using the inactive second translation table (pAltLevel1Table).
|
||||
* After each page table optimization or deoptimization operation has
|
||||
* completed, the second translation table will be set as the active
|
||||
* translation table. The initial set of page tables retain their
|
||||
* links to level 2 pages, which may otherwise be lost after optimization.
|
||||
* Any non-optimization changes to the active first-level table will also be
|
||||
* made to the inactive first-level table.
|
||||
* The semaphore is used to prevent corruption of the tables.
|
||||
*/
|
||||
|
||||
typedef struct mmuTransTblStruct
|
||||
{
|
||||
MMU_LEVEL_1_DESC *pLevel1Table; /* active MMU table */
|
||||
MMU_LEVEL_1_DESC *pAltLevel1Table; /* inactive MMU table */
|
||||
VX_MUTEX_SEMAPHORE(mmuTransTblSem); /* MMU tables' semaphore */
|
||||
UINT32 lockCnt; /* lock count */
|
||||
atomic_t lockOwner; /* lock owner */
|
||||
} MMU_TRANS_TBL;
|
||||
|
||||
#endif /* MMU_ARCHITECTURE_DEFINES_STRUCTURES */
|
||||
|
||||
/* Externally visible mmuLib, mmuMapLib and mmuALib2 routines */
|
||||
|
||||
IMPORT UINT32 mmuReadId (void);
|
||||
IMPORT PHYS_ADDR mmuVirtToPhys (VIRT_ADDR addr);
|
||||
IMPORT VIRT_ADDR mmuPhysToVirt (PHYS_ADDR addr);
|
||||
IMPORT UINT32 (* mmuCrGet) (void);
|
||||
IMPORT void (* mmuModifyCr) (UINT32 value, UINT32 mask);
|
||||
IMPORT UINT32 mmuHardCrGet (void);
|
||||
IMPORT UINT32 mmuSoftCrGet (void);
|
||||
IMPORT void mmuModifyHardCr (UINT32 value, UINT32 mask);
|
||||
IMPORT void mmuModifySoftCr (UINT32 value, UINT32 mask);
|
||||
|
||||
IMPORT UINT32 (* _func_mmuFaultAddrGet) (void);
|
||||
IMPORT UINT32 (* _func_mmuFaultStatusGet) (void);
|
||||
|
||||
IMPORT UINT32 mmuFarGet (void); /* CP15_FAR only available with MMUs */
|
||||
IMPORT UINT32 mmuFsrGet (void); /* CP15_FSR only available with MMUs */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* (ARMMMU != ARMMMU_NONE) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmmuArmPalLibh */
|
||||
@@ -0,0 +1,459 @@
|
||||
/* mmuArmXSCALELib.h - XScale MMU library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000, 2001, 2003-2007, 2009-2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01l,29jul10,pad Moved extern C statement after include statements.
|
||||
01k,03nov09,j_b add INCLUDE_MMU_TEX_SUPPORT, undef INCLUDE_MMU_SUBPAGE_SUPPORT
|
||||
01j,23oct07,to added lockCnt and lockOwner to MMU_TRANS_TBL
|
||||
01i,13sep06,j_b add page optimization support
|
||||
01h,29mar06,m_h Coherancy (S-bit) support
|
||||
01g,03jan06,m_h Manzano Support
|
||||
01f,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01e,10feb05,jb Reverting to ROM mode for shared data/libraries
|
||||
01d,09dec04,jb Palify Arm MMU
|
||||
01c,08sep03,scm add P-bit support...
|
||||
01b,23jul01,scm change XScale name to conform to coding standards...
|
||||
01a,31aug00,scm created.
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuArmXSCALELibh
|
||||
#define __INCmmuArmXSCALELibh
|
||||
|
||||
#include <memLib.h>
|
||||
#include <semLib.h>
|
||||
|
||||
#define MMU_ID_XSCALE 0x052000
|
||||
|
||||
/* Enable support for section descriptors */
|
||||
#undef INCLUDE_MMU_SECTION_SUPPORT
|
||||
#define INCLUDE_MMU_SECTION_SUPPORT
|
||||
|
||||
/* Let the Pal code know Xscale has unique structures */
|
||||
|
||||
#define MMU_ARCHITECTURE_DEFINES_STRUCTURES
|
||||
|
||||
#include "mmuArmPalLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Xscale specific definitions follow */
|
||||
|
||||
#undef INCLUDE_MMU_SUBPAGE_SUPPORT
|
||||
|
||||
#undef INCLUDE_MMU_TEX_SUPPORT
|
||||
#define INCLUDE_MMU_TEX_SUPPORT
|
||||
|
||||
#undef MMU_DEF_L1_PAGE
|
||||
#define MMU_DEF_L1_PAGE 0x00000001 /* domain zero, Page descriptor */
|
||||
|
||||
#undef MMU_STATE_MASK_WRITABLE
|
||||
#define MMU_STATE_MASK_WRITABLE 0x00000030 /* All APn bits */
|
||||
|
||||
#define MMU_STATE_X_BIT 0x00000040
|
||||
#define MMU_STATE_S_BIT 0x00000200 /* S-bit coherancy */
|
||||
|
||||
#define MMU_STATE_MASK_EX_BUFFERABLE (MMU_STATE_X_BIT | MMU_STATE_MASK_BUFFERABLE)
|
||||
#define MMU_STATE_MASK_EX_CACHEABLE (MMU_STATE_X_BIT | MMU_STATE_MASK_CACHEABLE)
|
||||
|
||||
#undef MMU_STATE_VALID
|
||||
#define MMU_STATE_VALID MMU_PTE_TYPE_EX_PAGE /* set to page type */
|
||||
|
||||
#undef MMU_STATE_WRITABLE
|
||||
#define MMU_STATE_WRITABLE 0x00000030 /* APn bits to 11 */
|
||||
|
||||
#undef MMU_STATE_MASK_PROTECTION
|
||||
#define MMU_STATE_MASK_PROTECTION 0x00000030 /* APn bits */
|
||||
|
||||
#undef MMU_STATE_SUP_RO
|
||||
#define MMU_STATE_SUP_RO 0x00000000 /* AP: 00 */
|
||||
|
||||
#undef MMU_STATE_SUP_RW
|
||||
#define MMU_STATE_SUP_RW 0x00000010 /* AP: 01 */
|
||||
|
||||
#undef MMU_STATE_USR_RO_SUP_RW
|
||||
#define MMU_STATE_USR_RO_SUP_RW 0x00000020 /* AP: 10 */
|
||||
|
||||
#undef MMU_STATE_USR_RW_SUP_RW
|
||||
#define MMU_STATE_USR_RW_SUP_RW 0x00000030 /* AP: 11 */
|
||||
|
||||
/* only AP bits valid on extended small page tables are AP0 */
|
||||
|
||||
#ifdef INCLUDE_MMU_SBIT_SUPPORT
|
||||
#define MMU_MSK_UNUSED_AP 0xfffff23f
|
||||
#else /*INCLUDE_MMU_SBIT_SUPPORT*/
|
||||
#define MMU_MSK_UNUSED_AP 0xfffff03f
|
||||
#endif /*INCLUDE_MMU_SBIT_SUPPORT*/
|
||||
|
||||
#define MMU_MSK_CHK_APS 0x00000fc0
|
||||
#define MMU_MSK_X_BIT 0x00000040
|
||||
|
||||
/* Section and supersection L1 definitions follow */
|
||||
|
||||
#undef MMU_DEF_L1_SECTION_PAGE
|
||||
#define MMU_DEF_L1_SECTION_PAGE 0x00000002 /* Section page descriptor */
|
||||
|
||||
#undef MMU_DEF_L1_SUPERSECTION_PAGE
|
||||
#define MMU_DEF_L1_SUPERSECTION_PAGE 0x00040002 /* supersection */
|
||||
|
||||
#undef MMU_DEF_L1_SECTION_PAGE_MASK
|
||||
#define MMU_DEF_L1_SECTION_PAGE_MASK 0x00040003 /* mask */
|
||||
|
||||
#undef MMU_STATE_SECTION_MASK_WRITABLE
|
||||
#define MMU_STATE_SECTION_MASK_WRITABLE 0x00000030 /* All APn bits */
|
||||
|
||||
/* optional extended physical address bit fields */
|
||||
#define MMU_L1DSSECTION_EXTD_BA_MASK MMU_L1DSSECTIONHI_BA_MASK
|
||||
|
||||
/* Supersection base address packing */
|
||||
#define MMU_L1DSSECTION_BA_SET(physAddr, ssectDesc) \
|
||||
(ssectDesc = (ssectDesc & ~MMU_L1DSSECTION_EXTD_BA_MASK) | \
|
||||
( (((unsigned long long)(physAddr)) & MMU_L1DSSECTIONLO_BA_MASK) | \
|
||||
((((unsigned long long)(physAddr)) >> 12) & \
|
||||
MMU_L1DSSECTIONHI_BA_MASK) ))
|
||||
/* Supersection base address unpacking */
|
||||
#define MMU_L1DSSECTION_BA_GET(ssectDesc) \
|
||||
((unsigned long long) \
|
||||
( (unsigned long long)(ssectDesc & MMU_L1DSSECTIONLO_BA_MASK) | \
|
||||
((unsigned long long)(ssectDesc & MMU_L1DSSECTIONHI_BA_MASK) \
|
||||
<< 12) ))
|
||||
|
||||
/* The X-bit is the LSB of TEX: bit-12 of the section or supersection L1 */
|
||||
#define MMU_STATE_SECTION_X_BIT 0x00001000
|
||||
|
||||
#define MMU_STATE_MASK_SECTION_EX_BUFFERABLE \
|
||||
(MMU_STATE_SECTION_X_BIT | MMU_STATE_MASK_BUFFERABLE)
|
||||
#define MMU_STATE_MASK_SECTION_EX_CACHEABLE \
|
||||
(MMU_STATE_SECTION_X_BIT | MMU_STATE_MASK_CACHEABLE)
|
||||
|
||||
#define MMU_SECTION_MSK_X_BIT 0x00001000
|
||||
|
||||
#define MMU_STATE_CACHEABLE_MINICACHE 0x48 /* allocate in minicache, X=1, CB=10 */
|
||||
|
||||
/* the mini data cache attributes to the Auxiliary Control Reg */
|
||||
/* used by mmuSetMDBits... */
|
||||
|
||||
#define MD_COPYBACK 0x00000000
|
||||
#define MD_WRITEALLOCATE 0x00000010
|
||||
#define MD_WRITETHRU 0x00000020
|
||||
|
||||
#define MMU_STATE_CACHEABLE_EX_COPYBACK (MMU_STATE_X_BIT | MMU_STATE_CACHEABLE_COPYBACK)
|
||||
|
||||
#define MMU_STATE_EX_CACHEABLE MMU_STATE_CACHEABLE_EX_COPYBACK
|
||||
|
||||
#define MMU_STATE_EX_CACHEABLE_NOT 0x0
|
||||
|
||||
/* bufferable, not cacheable, no coalesce */
|
||||
|
||||
#define MMU_STATE_EX_BUFFERABLE (MMU_STATE_X_BIT | MMU_STATE_BUFFERABLE)
|
||||
#define MMU_STATE_EX_BUFFERABLE_NOT 0x0 /* will also set not cacheable, no coalesce */
|
||||
|
||||
#define MMU_ATTR_CACHE_MINICACHE (MMU_ATTR_SPL_1 | MMU_ATTR_CACHE_COPYBACK)
|
||||
|
||||
/*
|
||||
* two new states with extended small page tables, bufferable no coalesce, and
|
||||
* write back with read/write allocate...
|
||||
*/
|
||||
|
||||
#define MMU_ATTR_NO_COALESCE (MMU_ATTR_SPL_2 | MMU_ATTR_CACHE_OFF) /* Cache -- no coalesce into buffers */
|
||||
#define MMU_ATTR_WRITEALLOCATE (MMU_ATTR_SPL_3 | MMU_ATTR_CACHE_COPYBACK) /* Cache -- write allocate */
|
||||
|
||||
/* cache states determined by MD-bits of Auxilliary Control Register */
|
||||
|
||||
#define MMU_ATTR_CACHE_MINICACHE_CB (MMU_ATTR_SPL_1 | MMU_ATTR_CACHE_COPYBACK)
|
||||
#define MMU_ATTR_CACHE_MINICACHE_WA (MMU_ATTR_SPL_1 | MMU_ATTR_WRITEALLOCATE)
|
||||
#define MMU_ATTR_CACHE_MINICACHE_WT (MMU_ATTR_SPL_1 | MMU_ATTR_CACHE_WRITETHRU)
|
||||
|
||||
/* Write-through mode is only available on some CPUs */
|
||||
|
||||
#define MMU_STATE_CACHEABLE_WRITETHROUGH 0x8
|
||||
|
||||
/*
|
||||
* Values to be used when mmuEnable() is called. This will be after the MMU has
|
||||
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
|
||||
* cache enable settings have been chosen.
|
||||
*
|
||||
* M 1 Enable MMU
|
||||
* A 0 Disable address alignment fault
|
||||
* C X ((D-)Cache Enable) Controlled by cacheLib
|
||||
* W X (Write Buffer) Controlled by cacheLib
|
||||
* P 1 (PROG32) should be set before this
|
||||
* D 1 (DATA32) should be set before this
|
||||
* L 1 (Late abort on earlier CPUs) ignore
|
||||
* B X (Big/Little-endian) should be set before this
|
||||
* S 1 (System)
|
||||
* R 0 (ROM)
|
||||
* F 0 Should be Zero
|
||||
* Z X (Branch prediction enable on 810) Controlled by cacheLib
|
||||
* I X (I-cache enable) Controlled by cacheLib
|
||||
*
|
||||
* For time being, do not enable the address alignment fault, as GCC
|
||||
* currently generates unaligned accesses in its code, and switching this
|
||||
* on will cause immediate faults. So, do not put it into the enable
|
||||
* mask.
|
||||
*
|
||||
* We used to clear all the Reserved/Should Be Zero bits when the
|
||||
* MMU/MPU was enabled, by including one bits for them in the definition
|
||||
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
|
||||
* the definitions of the bits within the MMU Control Register. The MMU
|
||||
* Control register is initialised within romInit()/sysInit(), as the BSP
|
||||
* is the only place where the particular details of the CPU/MMU are
|
||||
* actually known. In general, it will be appropriate for the BSP to
|
||||
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
|
||||
* MMU is enabled, we will only change the bits we are particularly
|
||||
* concerned about, by using a Read-Modify-Write strategy.
|
||||
*/
|
||||
|
||||
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
|
||||
|
||||
#define MMUCR_MODE MMUCR_ROM /* This MUST remain as ROM for shared libraries */
|
||||
|
||||
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
|
||||
|
||||
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE)
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_MODE)
|
||||
#else
|
||||
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_BIGEND | MMUCR_MODE)
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
|
||||
/* little-endian */
|
||||
|
||||
/* First level page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* descriptor type, 1 => page */
|
||||
UINT pad1 : 2; /* SBZ */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT addr : 22; /* base address of page table */
|
||||
} PAGE_DESC_FIELD;
|
||||
|
||||
/* First level "section" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
UINT bbit : 1; /* bufferable-bit */
|
||||
UINT cbit : 1; /* cacheable-bit */
|
||||
UINT pad1 : 1; /* SBO */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT tex : 3; /* TEX */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT pad3 : 1; /* SBO */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT pad4 : 1; /* SBO */
|
||||
UINT addr : 12; /* base address of page table */
|
||||
} SECTION_DESC_FIELD;
|
||||
|
||||
/* First level "supersection" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
UINT bbit : 1; /* bufferable-bit */
|
||||
UINT cbit : 1; /* cacheable-bit */
|
||||
UINT pad1 : 1; /* SBO */
|
||||
UINT addrHi2: 4; /* SBZ [phys address 39:36] */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT tex : 3; /* TEX */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT pad3 : 1; /* SBO */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT pad4 : 1; /* SBO */
|
||||
UINT addrHi : 4; /* phys address 35:32 */
|
||||
UINT addrLo : 8; /* phys address 31:24 */
|
||||
} SUPERSECTION_DESC_FIELD;
|
||||
|
||||
|
||||
|
||||
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT type : 2; /* page type, 3 => extended small page */
|
||||
UINT cb : 2; /* cacheable/bufferable bits */
|
||||
UINT ap : 2; /* access permission */
|
||||
UINT tex : 4; /* type extension field */
|
||||
UINT sbz : 2; /* should be zero */
|
||||
UINT addr : 20; /* page base address */
|
||||
} PTE_FIELD;
|
||||
|
||||
#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
|
||||
|
||||
/* big-endian */
|
||||
|
||||
/* First level page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT addr : 22; /* base address of page table */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT pad1 : 2; /* SBZ */
|
||||
UINT type : 2; /* descriptor type, 1 => page */
|
||||
} PAGE_DESC_FIELD;
|
||||
|
||||
/* First level "section" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT addr : 12; /* base address of page table */
|
||||
UINT pad4 : 1; /* SBO */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT pad3 : 1; /* SBO */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT tex : 3; /* AP */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT domain : 4; /* domain number */
|
||||
UINT pad1 : 1; /* SBO */
|
||||
UINT c : 1; /* c-bit */
|
||||
UINT b : 1; /* b-bit */
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
} SECTION_DESC_FIELD;
|
||||
|
||||
/* First level "supersection" descriptor */
|
||||
typedef struct
|
||||
{
|
||||
UINT addrLo : 8; /* phys address 31:24 */
|
||||
UINT addrHi : 4; /* phys address 35:32 */
|
||||
UINT pad4 : 1; /* SBO */
|
||||
UINT super : 1; /* 1 => supersection */
|
||||
UINT pad3 : 1; /* SBO */
|
||||
UINT sbit : 1; /* S-bit */
|
||||
UINT pad2 : 1; /* SBO */
|
||||
UINT tex : 3; /* AP */
|
||||
UINT ap : 2; /* AP */
|
||||
UINT pbit : 1; /* XSCALE 'P' bit */
|
||||
UINT addrHi2: 4; /* SBZ [phys address 39:36] */
|
||||
UINT pad1 : 1; /* SBO */
|
||||
UINT c : 1; /* c-bit */
|
||||
UINT b : 1; /* b-bit */
|
||||
UINT type : 2; /* descriptor type, 2 => section */
|
||||
} SUPERSECTION_DESC_FIELD;
|
||||
|
||||
/* Layout of Page Table Entries (PTEs), actually small page descriptors */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT addr : 20; /* page base address */
|
||||
UINT sbz : 2; /* should be zero */
|
||||
UINT tex : 4; /* type extension field */
|
||||
UINT ap : 2; /* access permission */
|
||||
UINT cb : 2; /* cacheable/bufferable bits */
|
||||
UINT type : 2; /* page type, 3 => extended small page */
|
||||
} PTE_FIELD;
|
||||
|
||||
#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
|
||||
|
||||
/* First level descriptor access */
|
||||
|
||||
typedef union
|
||||
{
|
||||
PAGE_DESC_FIELD fields;
|
||||
SECTION_DESC_FIELD sectionFields;
|
||||
SUPERSECTION_DESC_FIELD supersectionFields;
|
||||
UINT32 bits;
|
||||
} MMU_LEVEL_1_DESC;
|
||||
|
||||
/* Second level descriptor access */
|
||||
|
||||
typedef union
|
||||
{
|
||||
PTE_FIELD fields;
|
||||
UINT32 bits;
|
||||
} PTE;
|
||||
|
||||
/*
|
||||
* Structure for MMU translation table access - normally used to get a pointer
|
||||
* to the first-level translation table.
|
||||
* To support page table optimization, a second first-level table and a
|
||||
* semaphore are needed.
|
||||
* The initial, unoptimized set of page tables will be set as the active
|
||||
* translation tables (via pLevel1Table) while optimization or deoptimization
|
||||
* is in progress using the inactive second translation table (pAltLevel1Table).
|
||||
* After each page table optimization or deoptimization operation has
|
||||
* completed, the second translation table will be set as the active
|
||||
* translation table. The initial set of page tables retain their
|
||||
* links to level 2 pages, which may otherwise be lost after optimization.
|
||||
* Any non-optimization changes to the active first-level table will also be
|
||||
* made to the inactive first-level table.
|
||||
* The semaphore is used to prevent corruption of the tables.
|
||||
*/
|
||||
|
||||
typedef struct mmuTransTblStruct
|
||||
{
|
||||
MMU_LEVEL_1_DESC *pLevel1Table; /* active MMU table */
|
||||
MMU_LEVEL_1_DESC *pAltLevel1Table; /* inactive MMU table */
|
||||
VX_MUTEX_SEMAPHORE(mmuTransTblSem); /* MMU tables' semaphore */
|
||||
UINT32 lockCnt; /* lock count */
|
||||
atomic_t lockOwner; /* lock owner */
|
||||
} MMU_TRANS_TBL;
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
|
||||
|
||||
IMPORT void mmuArmXSCALELibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
IMPORT void mmuArmXSCALETtbrSet (MMU_LEVEL_1_DESC *);
|
||||
IMPORT MMU_LEVEL_1_DESC * mmuArmXSCALETtbrGet ( void);
|
||||
IMPORT void mmuArmXSCALEDacrSet (UINT32 dacrVal);
|
||||
IMPORT void mmuArmXSCALETLBIDFlushEntry (void *addr);
|
||||
IMPORT void mmuArmXSCALETLBIDFlushAll (void);
|
||||
IMPORT void mmuArmXSCALEAEnable (UINT32 cacheState);
|
||||
IMPORT void mmuArmXSCALEADisable (void);
|
||||
IMPORT STATUS mmuArmXSCALEPBitSet ( void * virtAddr, UINT32 size);
|
||||
IMPORT STATUS mmuArmXSCALEPBitClear ( void * virtAddr, UINT32 size);
|
||||
IMPORT STATUS mmuArmXSCALEPBitGet ( void * virtAddr );
|
||||
IMPORT STATUS mmuArmXSCALEAcrGet (void );
|
||||
IMPORT void mmuArmXSCALEAcrSet (UINT32 acrVal);
|
||||
|
||||
#else /* __STDC__ */
|
||||
|
||||
IMPORT void mmuArmXSCALELibInstall ();
|
||||
IMPORT void mmuArmXSCALETtbrSet ();
|
||||
IMPORT MMU_LEVEL_1_DESC * mmuArmXSCALETtbrGet ();
|
||||
IMPORT void mmuArmXSCALEDacrSet ();
|
||||
IMPORT void mmuArmXSCALETLBIDFlushEntry ();
|
||||
IMPORT void mmuArmXSCALETLBIDFlushAll ();
|
||||
IMPORT void mmuArmXSCALEAEnable ();
|
||||
IMPORT void mmuArmXSCALEADisable ();
|
||||
IMPORT STATUS mmuArmXSCALEPBitSet ();
|
||||
IMPORT STATUS mmuArmXSCALEPBitClear ();
|
||||
IMPORT STATUS mmuArmXSCALEPBitGet ();
|
||||
IMPORT STATUS mmuArmXSCALEAcrGet ();
|
||||
IMPORT void mmuArmXSCALEAcrSet ();
|
||||
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmmuArmXSCALELibh */
|
||||
@@ -0,0 +1,163 @@
|
||||
/* mmuCortexA8Lib.h - Cortex-A8 MMU library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008, 2010-2012, 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01j,19aug13,zgl LPAE support (WIND00357632)
|
||||
01i,17jul12,j_b fix mmuCortexA8AcrGet API
|
||||
01h,20dec11,jdw Add missing APIs to clear up warnings related to ttbr APIs
|
||||
01g,25aug10,my_ Remove MMUCR_BIGEND in MMU_INIT_VALUE and add
|
||||
MMUCR_EE in MMU_INIT_VALUE (WIND00229795)
|
||||
01f,29apr10,pad Moved extern C statement after include statements.
|
||||
01e,09feb10,j_b update mmuCortexA8TtbrSet for ASID support
|
||||
01d,25aug10,my_ make EE bit default in BE8 mode (WIND00228157)
|
||||
01c,05aug10,j_b enable branch prediction by default (CQID: 222896)
|
||||
01b,05aug10,m_h Thumb-mode exception handling for Thumb-2
|
||||
01a,11jun08,j_b Created from mmuArm1136jfLib.h, rev 01a
|
||||
*/
|
||||
|
||||
#ifndef __INCmmuCortexALibh
|
||||
#define __INCmmuCortexALibh
|
||||
|
||||
#include "memLib.h"
|
||||
|
||||
#ifndef _WRS_CONFIG_ARM_LPAE
|
||||
#include <arch/arm/mmuArmArch6PalLib.h>
|
||||
#else /* _WRS_CONFIG_ARM_LPAE */
|
||||
#include <arch/arm/mmuArmLpaeLib.h>
|
||||
#endif /* !_WRS_CONFIG_ARM_LPAE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Cortex-A Specific definitions follow */
|
||||
|
||||
/*
|
||||
* Values to be used when mmuEnable() is called. This will be after the MMU has
|
||||
* been initialised by sysInit()/romInit() and after cacheLib has set whatever
|
||||
* cache enable settings have been chosen.
|
||||
* See "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition"
|
||||
* (ARM DDI 0406) and "Cortex-A8 Processor Technical Reference Manual"
|
||||
* (ARM DDI 0344) for details.
|
||||
*
|
||||
* M 1 Enable MMU
|
||||
* A 0 Disable address alignment fault
|
||||
* C X ((D-)Cache Enable) Controlled by cacheLib
|
||||
* - 1 (Write Buffer - obsolete) Reserved; SBO
|
||||
* - 1 (PROG32 - obsolete) Reserved; SBO
|
||||
* - 1 (DATA32 - obsolete) Reserved; SBO
|
||||
* - 1 (Late abort - obsolete) Reserved; SBO
|
||||
* B 0 (Big/Little-endian - obsolete) Reserved; SBZ
|
||||
* - 0 (System - obsolete) Reserved; SBZ
|
||||
* - 0 (ROM - obsolete) Reserved; SBZ
|
||||
* SW 0 (SWP/SWPB Enable - unsupported) SBZ; Reserved for Multiprocessing
|
||||
* Z 1 (Branch prediction enable)
|
||||
* I X (I-cache enable) Controlled by cacheLib
|
||||
* V 0 (Vector table location: Normal/High Address)
|
||||
* RR 0 (Random/Round-Robin cache replacement - unsupported) SBZ
|
||||
* - 0 (Load instructions to PC set T bit - obsolete) SBZ
|
||||
* - 1 (Data TCM enable - obsolete) SBO
|
||||
* HA 0 (Hardware Access flag enable - unsupported) SBZ
|
||||
* - 1 (Instruction TCM enable - obsolete) SBO
|
||||
* - 0 Reserved; SBZ
|
||||
* - 0 Reserved; SBZ
|
||||
* FI 0 (Fast Interrupt enable - unsupported) SBZ
|
||||
* U 1 (Unaligned access enable); SBO
|
||||
* - 1 (extended PTE format enable - obsolete) SBO
|
||||
* VE 0 (VEctored Interrupt - unsupported) SBZ
|
||||
* EE 0 Exception Endian set to Little-Endian
|
||||
* - 0 Reserved; SBZ
|
||||
* NMFI 0 Disable NMFI behavior for FIQs
|
||||
* TRE 0 Disable TEX Remap
|
||||
* AFE 0 Disable Access Flag
|
||||
* TE X if Thumb-2 enable Thumb Exceptions
|
||||
* - 0 Reserved; SBZ
|
||||
*
|
||||
* For time being, do not enable the address alignment fault, as GCC
|
||||
* currently generates unaligned accesses in its code, and switching this
|
||||
* on will cause immediate faults. So, do not put it into the enable
|
||||
* mask.
|
||||
*
|
||||
* We used to clear all the Reserved/Should Be Zero bits when the
|
||||
* MMU/MPU was enabled, by including one bits for them in the definition
|
||||
* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
|
||||
* the definitions of the bits within the MMU Control Register. The MMU
|
||||
* Control register is initialised within romInit()/sysInit(), as the BSP
|
||||
* is the only place where the particular details of the CPU/MMU are
|
||||
* actually known. In general, it will be appropriate for the BSP to
|
||||
* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
|
||||
* MMU is enabled, we will only change the bits we are particularly
|
||||
* concerned about, by using a Read-Modify-Write strategy.
|
||||
*/
|
||||
|
||||
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE)
|
||||
|
||||
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE)
|
||||
|
||||
#if (ARM_THUMB2)
|
||||
#define MMU_EXCEPTION_MODE MMUCR_THUMB_EXCEPTIONS
|
||||
#else /* (ARM_THUMB2) */
|
||||
#define MMU_EXCEPTION_MODE 0x0
|
||||
#endif /* (ARM_THUMB2) */
|
||||
|
||||
/* Control Register SBO bits */
|
||||
|
||||
#define MMU_MUST_SET_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_W_ENABLE | MMUCR_ENABLE_DTCM | \
|
||||
MMUCR_ENABLE_ITCM | MMUCR_UNALIGNED_ENABLE | \
|
||||
MMUCR_EXTENDED_PAGE | MMU_EXCEPTION_MODE)
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
#define MMU_INIT_VALUE (MMU_MUST_SET_VALUE | MMUCR_Z_ENABLE)
|
||||
#else
|
||||
#define MMU_INIT_VALUE (MMU_MUST_SET_VALUE | MMUCR_Z_ENABLE | MMUCR_EE)
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void mmuCortexA8LibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
|
||||
PHYS_ADDR(virtToPhys) (VIRT_ADDR));
|
||||
#ifndef _WRS_CONFIG_ARM_LPAE
|
||||
IMPORT void mmuCortexA8TtbrSet (MMU_LEVEL_1_DESC *pTable, UINT32 asid);
|
||||
IMPORT MMU_LEVEL_1_DESC * mmuCortexA8TtbrGet (void);
|
||||
IMPORT void mmuCortexA8TtbrSetAll (UINT32 ttbr, UINT32 asid);
|
||||
IMPORT UINT32 mmuCortexA8TtbrGetAll (void);
|
||||
IMPORT void mmuCortexA8DacrSet (UINT32 dacrVal);
|
||||
#else /* _WRS_CONFIG_ARM_LPAE */
|
||||
IMPORT void mmuCortexA8TtbrSet64 (UINT64 ttbr);
|
||||
IMPORT UINT64 mmuCortexA8TtbrGet64 (void);
|
||||
IMPORT void mmuCortexA8MairSet(UINT32 mair0Val, UINT32 mair1Val);
|
||||
IMPORT void mmuCortexA8TtbcrSet (UINT32 ttbcr);
|
||||
IMPORT UINT32 mmuCortexA8TtbcrGet (void);
|
||||
#endif /* !_WRS_CONFIG_ARM_LPAE */
|
||||
|
||||
IMPORT void mmuCortexA8TLBIDFlushEntry (VIRT_ADDR *addr);
|
||||
IMPORT void mmuCortexA8TLBIDFlushAll (void);
|
||||
IMPORT void mmuCortexA8AEnable (UINT32 cacheState);
|
||||
IMPORT void mmuCortexA8ADisable (void);
|
||||
IMPORT STATUS mmuCortexA8PBitSet (VIRT_ADDR virtAddr, UINT32 size);
|
||||
IMPORT STATUS mmuCortexA8PBitClear (VIRT_ADDR virtAddr, UINT32 size);
|
||||
IMPORT STATUS mmuCortexA8PBitGet (VIRT_ADDR virtAddr);
|
||||
IMPORT UINT32 mmuCortexA8AcrGet (void);
|
||||
IMPORT void mmuCortexA8AcrSet (UINT32 acrVal);
|
||||
IMPORT STATUS mmuCortexA8ITcmrGet (void);
|
||||
IMPORT void mmuCortexA8ITcmrSet (UINT32 acrVal);
|
||||
IMPORT STATUS mmuCortexA8DTcmrGet (void);
|
||||
IMPORT void mmuCortexA8DTcmrSet (UINT32 acrVal);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmmuCortexALibh */
|
||||
@@ -0,0 +1,92 @@
|
||||
/* mpuArm940tLib.h - ARM 940T MPU library header file */
|
||||
|
||||
/* Copyright (c) 1998-2006, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement. No license to Wind River intellectual property rights
|
||||
* is granted herein. All rights not licensed by Wind River are reserved
|
||||
* by Wind River.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,29apr10,pad Moved extern C statement after include statements.
|
||||
01d,27jul06,m_h vxWorks 6.x palification
|
||||
01c,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01b,10aug04,scm adjust for MPU removal...
|
||||
01a,24nov98,cdp created.
|
||||
*/
|
||||
|
||||
#ifndef __INCmpuArm940tLibh
|
||||
#define __INCmpuArm940tLibh
|
||||
|
||||
#define MMU_ID_ARM940T 0x059400
|
||||
|
||||
#include "mpuArmPalLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
|
||||
|
||||
#define MMUCR_MODE MMUCR_ROM /* This MUST remain ROM for shared libraries */
|
||||
|
||||
#define MMUCR_L4_ENABLE (1<<15) /* L4 enable, ARMv4 behavior */
|
||||
|
||||
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
|
||||
|
||||
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE)
|
||||
|
||||
/*
|
||||
* Values to be used when the MPU Control Register is initialised from
|
||||
* within romInit.s or sysALib.s (before the MPU is enabled). Note that
|
||||
* on 710A, this is also used to initialise the soft-copy of the MPU CR
|
||||
* that we need to keep (in order to emulate Read-Modify-Write
|
||||
* operations). So, the BSP *MUST* initialise the MPU CR with the value
|
||||
* contained here, or else trouble will ensue. This restriction does
|
||||
* not apply to non-710A BSPs, but caution must be exercised in choosing a
|
||||
* value different to that defined here.
|
||||
*/
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
|
||||
/* W bit should Be One */
|
||||
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_MODE)
|
||||
|
||||
#else /* _BYTE_ORDER == _LITTLE_ENDIAN now _BIG_ENDIAN */
|
||||
|
||||
/* big endian */
|
||||
|
||||
/* W bit should Be One */
|
||||
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_BIGEND | MMUCR_MODE)
|
||||
#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void mpuArm940tLibInstall (void);
|
||||
IMPORT STATUS mpuArm940tShowInstall (void);
|
||||
|
||||
IMPORT void mpuArm940tPrrSet (const MPU_REGION_REG *pRegs);
|
||||
IMPORT void mpuArm940tPrrGet (MPU_REGION_REG *pRegs);
|
||||
|
||||
IMPORT void mpuArm940tCcrSet (UINT32 val);
|
||||
IMPORT UINT32 mpuArm940tCcrGet (void);
|
||||
IMPORT void mpuArm940tWbcrSet (UINT32 val);
|
||||
IMPORT UINT32 mpuArm940tWbcrGet (void);
|
||||
IMPORT void mpuArm940tPrSet (UINT32 val);
|
||||
IMPORT UINT32 mpuArm940tPrGet (void);
|
||||
IMPORT void mpuArm940tAEnable (UINT32 cacheState);
|
||||
IMPORT void mpuArm940tADisable (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmpuArm940tLibh */
|
||||
@@ -0,0 +1,93 @@
|
||||
/* mpuArm946eLib.h - ARM 946E MPU library header file */
|
||||
|
||||
/* Copyright (c) 1998-2006, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement. No license to Wind River intellectual property rights
|
||||
* is granted herein. All rights not licensed by Wind River are reserved
|
||||
* by Wind River.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01f,29apr10,pad Moved extern C statement after include statements.
|
||||
01e,13jul06,m_h MPU not MMU
|
||||
01d,22may06,m_h Palify
|
||||
01c,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
|
||||
01b,10aug04,scm adjust for MPU removal...
|
||||
01a,19jul00,jpd created, based on mmuArm940tLib.h.
|
||||
*/
|
||||
|
||||
#ifndef __INCmpuArm946eLibh
|
||||
#define __INCmpuArm946eLibh
|
||||
|
||||
#define MMU_ID_ARM946E 0x059460
|
||||
|
||||
#include "mpuArmPalLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
|
||||
|
||||
#define MMUCR_MODE MMUCR_ROM /* This MUST remain ROM for shared libraries */
|
||||
|
||||
#define MMUCR_L4_ENABLE (1<<15) /* L4 enable, ARMv4 behavior */
|
||||
|
||||
#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
|
||||
|
||||
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE)
|
||||
|
||||
/*
|
||||
* Values to be used when the MMU Control Register is initialised from
|
||||
* within romInit.s or sysALib.s (before the MMU is enabled). Note that
|
||||
* on 710A, this is also used to initialise the soft-copy of the MMU CR
|
||||
* that we need to keep (in order to emulate Read-Modify-Write
|
||||
* operations). So, the BSP *MUST* initialise the MMU CR with the value
|
||||
* contained here, or else trouble will ensue. This restriction does
|
||||
* not apply to non-710A BSPs, but caution must be exercised in choosing a
|
||||
* value different to that defined here.
|
||||
*/
|
||||
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
|
||||
/* W bit should Be One */
|
||||
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_MODE)
|
||||
|
||||
#else /* _BYTE_ORDER == _LITTLE_ENDIAN now _BIG_ENDIAN */
|
||||
|
||||
/* big endian */
|
||||
|
||||
/* W bit should Be One */
|
||||
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
|
||||
MMUCR_BIGEND | MMUCR_MODE)
|
||||
#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT void mpuArm946eLibInstall (void);
|
||||
IMPORT STATUS mpuArm946eShowInstall (void);
|
||||
|
||||
IMPORT void mpuArm946ePrrSet (const MPU_REGION_REG *pRegs);
|
||||
IMPORT void mpuArm946ePrrGet (MPU_REGION_REG *pRegs);
|
||||
|
||||
IMPORT void mpuArm946eCcrSet (UINT32 val);
|
||||
IMPORT UINT32 mpuArm946eCcrGet (void);
|
||||
IMPORT void mpuArm946eWbcrSet (UINT32 val);
|
||||
IMPORT UINT32 mpuArm946eWbcrGet (void);
|
||||
IMPORT void mpuArm946ePrSet (UINT32 val);
|
||||
IMPORT UINT32 mpuArm946ePrGet (void);
|
||||
IMPORT void mpuArm946eAEnable (UINT32 cacheState);
|
||||
IMPORT void mpuArm946eADisable (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmpuArm946eLibh */
|
||||
@@ -0,0 +1,229 @@
|
||||
/* mmuArmPalLib.h - ARM MPU library header file */
|
||||
|
||||
/* Copyright (c) 2006, 2007, 2010, 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement. No license to Wind River intellectual property rights
|
||||
* is granted herein. All rights not licensed by Wind River are reserved
|
||||
* by Wind River.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,16mar12,rec WIND00318272 - POSIX signals conformance
|
||||
01d,29apr10,pad Moved extern C statement after include statements.
|
||||
01c,21sep07,j_b add _func_mmuFaultAddrGet prototype
|
||||
01b,13jul06,m_h Generic MPU definitions
|
||||
01a,13jul06,m_h Created from mmuArmPalLib.h and vxWorks 5.5 mmuArmLib.h
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INCmpuArmPalLibh
|
||||
#define __INCmpuArmPalLibh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <memLib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#define MPU_NUM_REGIONS 8
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
|
||||
typedef struct
|
||||
{
|
||||
UINT enable : 1; /* 1 => region enabled */
|
||||
UINT size : 5; /* size */
|
||||
UINT pad : 6; /* padding */
|
||||
UINT base : 20; /* region base address */
|
||||
} MPU_REGION_FIELDS;
|
||||
#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
|
||||
/* Big-Endian */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT base : 20; /* region base address */
|
||||
UINT pad : 6; /* padding */
|
||||
UINT size : 5; /* size */
|
||||
UINT enable : 1; /* 1 => region enabled */
|
||||
} MPU_REGION_FIELDS;
|
||||
#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
|
||||
|
||||
typedef union
|
||||
{
|
||||
MPU_REGION_FIELDS fields;
|
||||
UINT32 bits;
|
||||
} MPU_REGION_REG;
|
||||
|
||||
typedef struct mpuTransTblStruct
|
||||
{
|
||||
MPU_REGION_REG regs[MPU_NUM_REGIONS];
|
||||
} MPU_TRANS_TBL;
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/*
|
||||
* Architecture-dependent MPU states. These are states settable for regions.
|
||||
*/
|
||||
|
||||
/* The size must be larger than 0x0A so zero in these fields
|
||||
* is an invalid MPU state is it is enabled (bit-0 = 1)
|
||||
*/
|
||||
#define MMU_STATE_INVALID_STATE 0xFFFFFFFF
|
||||
|
||||
#define MPU_REGION_BASE_MASK 0xFFFFF000
|
||||
#define MPU_REGION_SIZE_MASK 0x0000003E
|
||||
#define MPU_REGION_SIZE_MAX 0x0000003E
|
||||
|
||||
#define MMU_STATE_MASK_CACHEABLE 0xC0 /* CB bits */
|
||||
#define MMU_STATE_MASK_BUFFERABLE 0x40
|
||||
|
||||
#define MMU_STATE_MASK_VALID 0x100 /* allows 4 AP bits */
|
||||
#define MMU_STATE_VALID 0x100 /* Full Access */
|
||||
#define MMU_STATE_VALID_NOT 0x000 /* No access */
|
||||
|
||||
#ifdef MPU_USE_EXTENDED_PERMISSIONS
|
||||
|
||||
#define MMU_STATE_NUM_AP_BITS 4
|
||||
#define MMU_STATE_MASK_PROTECTION 0xF
|
||||
|
||||
#else /*MPU_USE_EXTENDED_PERMISSIONS*/
|
||||
|
||||
#define MMU_STATE_NUM_AP_BITS 2
|
||||
#define MMU_STATE_MASK_PROTECTION 0x3
|
||||
|
||||
#endif /*MPU_USE_EXTENDED_PERMISSIONS*/
|
||||
|
||||
/* cacheable and bufferable states are not real physical bit definitions */
|
||||
|
||||
#ifdef ARMCACHE_HAS_WRITETHROUGH
|
||||
/* Write-through mode is not available on all CPUs */
|
||||
|
||||
#define MMU_STATE_CACHEABLE_WRITETHROUGH 0x80
|
||||
#endif /*ARMCACHE_HAS_WRITETHROUGH*/
|
||||
|
||||
#define MMU_STATE_CACHE_BIT 0x80
|
||||
|
||||
#define MMU_STATE_CACHEABLE_COPYBACK 0xC0
|
||||
|
||||
/*
|
||||
* Set the default state to be copyback. CACHEABLE_WRITETHROUGH can also be
|
||||
* selected on 740T/946E.
|
||||
*/
|
||||
|
||||
#define MMU_STATE_CACHEABLE MMU_STATE_CACHEABLE_COPYBACK
|
||||
|
||||
#define MMU_STATE_CACHEABLE_NOT 0x0
|
||||
|
||||
#define MMU_STATE_BUFFERABLE 0x40 /* bufferable, not cacheable */
|
||||
#define MMU_STATE_BUFFERABLE_NOT 0x0 /* will also set not cacheable*/
|
||||
|
||||
/*
|
||||
* We need a size for a region that means the entire address
|
||||
* space. It is perfectly reasonable to wish to define such a region
|
||||
* and it is of course, not expressible within a UINT. So, define a
|
||||
* special size.
|
||||
*/
|
||||
|
||||
#define MMU_ENTIRE_SPACE 0
|
||||
|
||||
#define MMU_STATE_SUP_RW 0x01
|
||||
#define MMU_STATE_USR_RO_SUP_RW 0x02
|
||||
#define MMU_STATE_USR_RW_SUP_RW 0x03
|
||||
#define MMU_STATE_SUP_RO 0x05
|
||||
#define MMU_STATE_USR_RO_SUP_RO 0x06
|
||||
|
||||
/*
|
||||
* When setting either of the attributes SPL_0 or SPL_1 it is necessary to:
|
||||
*
|
||||
* 1. specify MMU_ATTR_SPL_MSK ORred with MMU_ATTR_CACHE_MSK in the mask
|
||||
* argument to the routine, and:
|
||||
* 2. specify the appropriate cache state ORred in to the state argument
|
||||
* to the routine.
|
||||
*
|
||||
* So, to set a page as bufferable not cacheable, it is necessary to
|
||||
* specify both MMU_ATTR_SPL_0 and specify MMU_ATTR_CACHE_OFF in the
|
||||
* state argument. To mark a page as cacheable in the minicache,
|
||||
* MMU_ATTR_SPL_1 and MMU_ATTR_CACHE_COPYBACK must be specified in the
|
||||
* state argument. In both cases, specify MMU_ATTR_SPL_MSK ORred with
|
||||
* MMU_ATTR_CACHE_MSK in the mask argument.
|
||||
*
|
||||
* To "unset" the special attibutes SPL_0 or SPL_1, specify
|
||||
* MMU_ATTR_CACHE_MSK in the mask parameter (without MMU_ATTR_SPL_MSK),
|
||||
* and specify the cacheability required in the state argument.
|
||||
*
|
||||
* We provide the following alias on ARM, to make life easier.
|
||||
*/
|
||||
|
||||
#define MMU_ATTR_BUFFERABLE (MMU_ATTR_SPL_0)
|
||||
|
||||
/* MMU Control Register bit allocations */
|
||||
|
||||
#define MMUCR_M_ENABLE (1<<0) /* MMU enable */
|
||||
#define MMUCR_A_ENABLE (1<<1) /* Address alignment fault enable */
|
||||
#define MMUCR_C_ENABLE (1<<2) /* (data) cache enable */
|
||||
#define MMUCR_W_ENABLE (1<<3) /* write buffer enable */
|
||||
#define MMUCR_PROG32 (1<<4) /* PROG32 */
|
||||
#define MMUCR_DATA32 (1<<5) /* DATA32 */
|
||||
#define MMUCR_L_ENABLE (1<<6) /* Late abort on earlier CPUs */
|
||||
#define MMUCR_BIGEND (1<<7) /* Big-endian (=1), little-endian (=0) */
|
||||
#define MMUCR_SYSTEM (1<<8) /* System bit, modifies MMU protections */
|
||||
#define MMUCR_ROM (1<<9) /* ROM bit, modifies MMU protections */
|
||||
#define MMUCR_F (1<<10) /* Should Be Zero */
|
||||
#define MMUCR_Z_ENABLE (1<<11) /* Branch prediction enable on 810 */
|
||||
#define MMUCR_I_ENABLE (1<<12) /* Instruction cache enable */
|
||||
#define MMUCR_V_ENABLE (1<<13) /* Exception vectors remap to 0xFFFF0000 */
|
||||
#define MMUCR_ALTVECT MMUCR_V_ENABLE /* alternate vector select */
|
||||
#define MMUCR_RR_ENABLE (1<<14) /* Round robin cache replacement enable */
|
||||
#define MMUCR_ROUND_ROBIN MMUCR_RR_ENABLE /* round-robin placement */
|
||||
#define MMUCR_DISABLE_TBIT (1<<15) /* disable TBIT */
|
||||
#define MMUCR_DSRAM_EN (1<<16) /* D-SRAM enable */
|
||||
#define MMUCR_DSRAM_LOADMODE (1<<17) /* D-SRAM load mode select */
|
||||
#define MMUCR_ISRAM_EN (1<<18) /* I-SRAM enable */
|
||||
#define MMUCR_ISRAM_LOADMODE (1<<19) /* I-SRAM load mode select */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* Externally visible mpuLib routines */
|
||||
|
||||
IMPORT UINT32 mmuReadId (void);
|
||||
|
||||
IMPORT UINT32 (* mmuCrGet) (void);
|
||||
IMPORT void (* mmuModifyCr) (UINT32 value, UINT32 mask);
|
||||
IMPORT UINT32 mmuHardCrGet (void);
|
||||
IMPORT UINT32 mmuSoftCrGet (void);
|
||||
IMPORT void mmuModifyHardCr (UINT32 value, UINT32 mask);
|
||||
IMPORT void mmuModifySoftCr (UINT32 value, UINT32 mask);
|
||||
|
||||
IMPORT UINT32 (* _func_mmuFaultAddrGet) (void);
|
||||
IMPORT UINT32 (* _func_mmuFaultStatusGet) (void);
|
||||
#if (CPU == ARMARCH6) || (CPU==ARMARCH7) || (CPU==ARMARCH7_T2)
|
||||
IMPORT UINT32 (* _func_mmuIFaultStatusGet) (void);
|
||||
#endif /* ARMARCH6 || ARMARCH7 || ARMARCH7_T2 */
|
||||
|
||||
IMPORT void mpuPrrSet (const MPU_REGION_REG *pRegs);
|
||||
IMPORT void mpuPrrGet (MPU_REGION_REG *pRegs);
|
||||
IMPORT void mpuCcrSet (UINT32 val);
|
||||
IMPORT UINT32 mpuCcrGet (void);
|
||||
IMPORT void mpuWbcrSet (UINT32 val);
|
||||
IMPORT UINT32 mpuWbcrGet (void);
|
||||
IMPORT void mpuPrSet (UINT32 val);
|
||||
IMPORT UINT32 mpuPrGet (void);
|
||||
IMPORT void mpuAEnable (UINT32 cacheState);
|
||||
IMPORT void mpuADisable (void);
|
||||
IMPORT UINT32 mpuGetEnable (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmpuArmPalLibh */
|
||||
@@ -0,0 +1,91 @@
|
||||
/* mpuGlobalMap.h - arch "independent" header MPU functionality */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,13jul06,m_h Arch "independent" MPU definitions normally found in vmLib.h
|
||||
(actually vmLibP.h)
|
||||
01a,13jul06,m_h written.
|
||||
*/
|
||||
|
||||
#ifndef __INCmpuGlobalMaph
|
||||
#define __INCmpuGlobalMaph
|
||||
|
||||
#include <private/vmLibP.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
typedef struct mpuTransTblStruct * MPU_TRANS_TBL_ID;
|
||||
|
||||
typedef STATUS (*MPUGLOBALPAGEMAPFUNCPTR)(VIRT_ADDR, PHYS_ADDR, UINT, BOOL);
|
||||
typedef STATUS (*MPUTRANSLATEFUNCPTR)(struct mpuTransTblStruct *,
|
||||
VIRT_ADDR, PHYS_ADDR *);
|
||||
typedef STATUS (*MPUPHYSTRANSLATEFUNCPTR)(struct mpuTransTblStruct *,
|
||||
PHYS_ADDR, VIRT_ADDR *);
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
FUNCPTR mpuLibInit;
|
||||
MPU_TRANS_TBL_ID (*mpuTransTblCreate) ();
|
||||
FUNCPTR mpuTransTblDelete;
|
||||
FUNCPTR mpuEnable;
|
||||
FUNCPTR mpuStateSetRegion;
|
||||
FUNCPTR mpuStateGet;
|
||||
MPUGLOBALPAGEMAPFUNCPTR mpuGlobalPageMap;
|
||||
MPUTRANSLATEFUNCPTR mpuTranslate;
|
||||
VOIDFUNCPTR mpuCurrentSet;
|
||||
FUNCPTR mpuAttrTranslate;
|
||||
FUNCPTR mpuShow;
|
||||
} MPU_LIB_FUNCS;
|
||||
|
||||
|
||||
#define MPU_ENABLE (*(mpuLibFuncs.mpuEnable))
|
||||
#define MPU_TRANS_TBL_CREATE (*(mpuLibFuncs.mpuTransTblCreate))
|
||||
#define MPU_STATE_SET_REGION (*(mpuLibFuncs.mpuStateSetRegion))
|
||||
#define MPU_CURRENT_SET (*(mpuLibFuncs.mpuCurrentSet))
|
||||
#define MPU_GLOBAL_PAGE_MAP (*(mpuLibFuncs.mpuGlobalPageMap))
|
||||
#define MPU_ATTR_TRANSLATE (*(mpuLibFuncs.mpuAttrTranslate))
|
||||
|
||||
#define MPU_TRANSLATE (*(mpuLibFuncs.mpuTranslate))
|
||||
|
||||
#define MPU_TRANS_TBL_DELETE (*(mpuLibFuncs.mpuTransTblDelete))
|
||||
|
||||
#define MPU_SHOW (*(mpuLibFuncs.mpuShow))
|
||||
|
||||
IMPORT MPU_LIB_FUNCS mpuLibFuncs;
|
||||
|
||||
IMPORT void mpuLibInstall (void);
|
||||
|
||||
IMPORT STATUS
|
||||
mpuGlobalMapInit (PHYS_MEM_DESC * pMemDescArray,
|
||||
int numDescArrayElements,
|
||||
BOOL enable,
|
||||
int cacheDefault);
|
||||
|
||||
IMPORT STATUS
|
||||
mpuStateSet (void *addr, int len, UINT stateMask, UINT state);
|
||||
|
||||
IMPORT STATUS mpuShow (void);
|
||||
|
||||
#endif /*_ASMLANGUAGE*/
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmpuGlobalMaph */
|
||||
@@ -0,0 +1,410 @@
|
||||
/* private/smpArmP.h - ARM/XScale-specific definitions for SMP support */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007-2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
|
||||
* Any compilation using definitions from this file will not *
|
||||
* be binary-compatible between the UP and SMP environments. *
|
||||
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01r,10sep12,ggm updated for tes.
|
||||
01q,02dec11,jdw Add _fpStatus per WIND00129622
|
||||
01p,30nov10,j_b add unified FIQ/IRQ handling support
|
||||
01o,29jul10,pad Moved extern C statement after include statements.
|
||||
01n,07jul10,jdw Add _WRS_ARCH_HAS_OBJ_SAFE
|
||||
01m,21may10,m_h Thumb-2 Support
|
||||
01l,15may09,gls moved VX_INSTR_BARRIER() to vxAtomicArchLibCommon.h
|
||||
01k,25feb09,j_b merge ARM SMP support:
|
||||
03feb09,j_b define _WRS_SNOOP_NEEDS_DMA_MALLOC_SUPPORT so
|
||||
cacheAimArch6DmaMalloc/Free are used with CACHE_SNOOP_ENABLE
|
||||
04oct07,j_b define _WRS_ARCH_REQUIRES_CACHE_TEXT_UPDATE_CPC
|
||||
31aug07,m_h Fix _ARM_PER_CPU_* macros for CPU != 0
|
||||
18jun07,m_h syntax error non-SMP _ARM_CPU_INDEX_GET
|
||||
01j,18sep08,gls added _WRS_KERNEL_LOCK_VAR_ALIGN
|
||||
01i,27aug08,jpb Renamed VSB header file
|
||||
01h,24jun08,jpb Added include path for kernel configurations options set in
|
||||
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
|
||||
01g,20jun08,zl replaced _WRS_ASM() with _WRS_BARRIER()
|
||||
01f,10jan08,gls added VX_INSTR_BARRIER()
|
||||
01e,09may07,lei renamed reschedNeeded to reschedMode.
|
||||
01d,09may07,m_h Fix per-CPU SMP macros, cleanup kernel global offsets
|
||||
01c,03may07,m_h SMP definitions
|
||||
01b,20apr07,m_h SMP Private definitions
|
||||
01a,04apr07,m_h written.
|
||||
*/
|
||||
|
||||
#ifndef __INCsmpArmPh
|
||||
#define __INCsmpArmPh
|
||||
|
||||
#include <vsbConfig.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
|
||||
/*
|
||||
* ARM has been adapted to use the new object safe count feature for SMP.
|
||||
* When all architectures have been adapted this can be removed from
|
||||
* the code.
|
||||
*/
|
||||
|
||||
#define _WRS_ARCH_HAS_OBJ_SAFE
|
||||
|
||||
/*
|
||||
* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
|
||||
* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
|
||||
* XSCALE, etc), representing the maximum cache line size of the variants of
|
||||
* the respective arch.
|
||||
*
|
||||
* For ARM this is 128 bytes.
|
||||
*/
|
||||
|
||||
#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
|
||||
|
||||
/*
|
||||
* ARM11 MPCore does not support cache coherency with DMA agents or
|
||||
* shared memory, so uncached memory must be returned by cacheDmaMalloc()
|
||||
* (via cacheAimArch6DmaMalloc) when CACHE_SNOOP_ENABLE is defined
|
||||
* (ex., in SMP mode).
|
||||
* See usage in target\src\os\mm\cacheLib.c:cacheFuncsSet().
|
||||
*/
|
||||
|
||||
#define _WRS_SNOOP_NEEDS_DMA_MALLOC_SUPPORT
|
||||
|
||||
/* Trigger software cacheTextUpdate CPC */
|
||||
|
||||
#define _WRS_ARCH_REQUIRES_CACHE_TEXT_UPDATE_CPC
|
||||
|
||||
/* ARM specific extension fields to the WIND_VARS struct */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
typedef struct wind_vars_arch
|
||||
{
|
||||
long cpu_intNestingLevel;
|
||||
long cpu_maxIntNestingLevel;
|
||||
UINT32 cpu_cacheArchState;
|
||||
char * cpu_undefSaveArea;
|
||||
char * cpu_abortSaveArea;
|
||||
char * cpu_swiSaveArea;
|
||||
char * cpu_irqStack;
|
||||
UINT32 cpu_fpStatus;
|
||||
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
|
||||
long cpu_fiqNestingLevel;
|
||||
long cpu_maxFiqNestingLevel;
|
||||
char * cpu_fiqStack;
|
||||
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
|
||||
} WIND_VARS_ARCH;
|
||||
|
||||
#define _WRS_WIND_VARS_ARCH WIND_VARS_ARCH cpu_archVars
|
||||
|
||||
/* macro to access the arch-specific fields of the vxKernelVars struct */
|
||||
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
|
||||
_WRS_KERNEL_GLOBAL_ACCESS (archVars.cpu_##glob)
|
||||
|
||||
#define _WRS_WIND_VARS_ARCH_SET(cpuid,glob,var) \
|
||||
_WRS_KERNEL_CPU_GLOBAL_SET(cpuid,archVars.cpu_##glob,var)
|
||||
|
||||
#define _WRS_WIND_VARS_ARCH_GET(cpuid,glob) \
|
||||
_WRS_KERNEL_CPU_GLOBAL_GET(cpuid,archVars.cpu_##glob)
|
||||
|
||||
#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
|
||||
_WRS_KERNEL_LOCKED_GLOBAL_SET(archVars.cpu_##glob,var)
|
||||
|
||||
#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
|
||||
_WRS_KERNEL_LOCKED_GLOBAL_GET(archVars.cpu_##glob,var)
|
||||
|
||||
|
||||
/* TODO optimization work needed in regsArm.h (etc) */
|
||||
#undef _WRS_ARCH_SUPPORTS_VX_CPU_STATE_INIT
|
||||
|
||||
#else /* !_ASMLANGUAGE */
|
||||
|
||||
/* offsets required for assembly macros */
|
||||
|
||||
#define WIND_VARS_ARCH_BASE (_WRS_WIND_VARS_OFFSET_archVars)
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/*
|
||||
* _WRS_WIND_VARS_ALIGN sets the alignment constraint for vxKernelVars. The
|
||||
* value must be: a power of two no smaller than sizeof(vxKernelVars), and a
|
||||
* multiple of the cache line size (which is 32) on every ARM variant that
|
||||
* supports SMP.
|
||||
*/
|
||||
#define _WRS_WIND_VARS_ALIGN 128
|
||||
#define _WRS_WIND_VARS_ALIGN_SHIFT 7
|
||||
|
||||
/*
|
||||
* _ARM_ATOMIC_OPS_SEPARATION defines the minimum desirable separation between
|
||||
* words on which SMP-atomic operations (including spinlock) will be
|
||||
* performed. This is the cache line size on ARM MP.
|
||||
*/
|
||||
|
||||
#define _ARM_ATOMIC_OPS_SEPARATION _CPU_CACHE_ALIGN_SIZE
|
||||
|
||||
# ifdef _CPU_CACHE_ALIGN_SIZE
|
||||
/*
|
||||
* Validate _WRS_WIND_VARS_ALIGN vs current build's _CPU_CACHE_ALIGN_SIZE
|
||||
*
|
||||
* If any SMP-enabled variant fails this test, _WRS_WIND_VARS_ALIGN must be
|
||||
* increased. Since this limit also applies to any subsequent arch-only
|
||||
* release against the same generic binary release, it may be desirable to
|
||||
* allow for growth.
|
||||
*/
|
||||
|
||||
|
||||
# if (_CPU_CACHE_ALIGN_SIZE > _WRS_WIND_VARS_ALIGN)
|
||||
#error Must increase "_WRS_WIND_VARS_ALIGN" to at least _CPU_CACHE_ALIGN_SIZE
|
||||
# endif /* _CPU_CACHE_ALIGN_SIZE > _WRS_WIND_VARS_ALIGN */
|
||||
|
||||
/*
|
||||
* Sanity check on _ARM_ATOMIC_OPS_SEPARATION
|
||||
*
|
||||
* A miss here generates a warning instead of an error, since it is merely
|
||||
* likely (not inevitable) that the lwarx/stwcx. granularity matches the
|
||||
* cache line size; also the performance penalty is less. (Two instances of
|
||||
* vxKernelVars within the same cache line will cause continual interference,
|
||||
* but two atoms within the same reservation granule will only occasionally
|
||||
* cause additional trips around the lwarx/stwcx. loop due to loss of the
|
||||
* reservation to an unrelated store.)
|
||||
*/
|
||||
# if (_CPU_CACHE_ALIGN_SIZE > _ARM_ATOMIC_OPS_SEPARATION)
|
||||
#warning Check "_ARM_ATOMIC_OPS_SEPARATION" setting; it likely should be at least _CPU_CACHE_ALIGN_SIZE
|
||||
# endif /* _CPU_CACHE_ALIGN_SIZE > _ARM_ATOMIC_OPS_SEPARATION */
|
||||
# endif /* _CPU_CACHE_ALIGN_SIZE */
|
||||
|
||||
/*
|
||||
* Just call the (assembly) function for now, but to optimize
|
||||
* performance this should eventually become a C-callable
|
||||
* _WRS_ASM construct (whose syntax varies depending on TOOL).
|
||||
*/
|
||||
#define _WRS_CPU_INDEX_GET() vxCpuIndexGet()
|
||||
#else /* _WRS_CONFIG_SMP */
|
||||
|
||||
/* macro to access the arch-specific fields */
|
||||
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
|
||||
_WRS_KERNEL_GLOBAL_ACCESS (glob)
|
||||
|
||||
#define _WRS_WIND_VARS_ARCH_SET(ignored,glob,var) \
|
||||
_WRS_KERNEL_CPU_GLOBAL_SET(ignored,glob,var)
|
||||
|
||||
#define _WRS_WIND_VARS_ARCH_GET(ignored,glob) \
|
||||
_WRS_KERNEL_CPU_GLOBAL_GET(ignored,archVars.cpu_##glob)
|
||||
|
||||
#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
|
||||
_WRS_KERNEL_LOCKED_GLOBAL_SET(glob,var)
|
||||
|
||||
#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
|
||||
_WRS_KERNEL_LOCKED_GLOBAL_GET(glob,var)
|
||||
|
||||
|
||||
#define _WRS_CPU_INDEX_GET() 0
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
|
||||
#include <private/windLibP.h>
|
||||
|
||||
# ifdef _WRS_CONFIG_SMP
|
||||
|
||||
#include <private/kernelLockLibP.h>
|
||||
|
||||
/*
|
||||
* Sticking a "#" in the middle of a complex #define generates garbage
|
||||
* passed to the assembler which results in a syntax error. ARM_HASH is
|
||||
* used by this file in order to tell the assembler to use an immediate
|
||||
* value.
|
||||
*/
|
||||
|
||||
#define ARM_HASH #
|
||||
|
||||
#define _ARM_WIND_VARS_OFFSET(label) _WRS_WIND_VARS_OFFSET_##label
|
||||
#define _ARM_WIND_VARS_OFFSET_reschedMode \
|
||||
#_WRS_WIND_VARS_OFFSET_reschedMode
|
||||
|
||||
/* ARM specific per-CPU globals */
|
||||
#define _WRS_WIND_VARS_OFFSET_intNestingLevel \
|
||||
(_WRS_WIND_VARS_OFFSET_archVars+0x0)
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET_maxIntNestingLevel \
|
||||
(_WRS_WIND_VARS_OFFSET_archVars+0x4)
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET_cacheArchState \
|
||||
(_WRS_WIND_VARS_OFFSET_archVars+0x8)
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET_undefSaveArea \
|
||||
(_WRS_WIND_VARS_OFFSET_archVars+0xC)
|
||||
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET_abortSaveArea \
|
||||
(_WRS_WIND_VARS_OFFSET_archVars+0x10)
|
||||
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET_swiSaveArea \
|
||||
(_WRS_WIND_VARS_OFFSET_archVars+0x14)
|
||||
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET_irqStack \
|
||||
(_WRS_WIND_VARS_OFFSET_archVars+0x18)
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET_fpStatus \
|
||||
(_WRS_WIND_VARS_OFFSET_archVars+0x1C)
|
||||
|
||||
#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET_fiqNestingLevel \
|
||||
(_WRS_WIND_VARS_OFFSET_archVars+0x20)
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET_maxFiqNestingLevel \
|
||||
(_WRS_WIND_VARS_OFFSET_archVars+0x24)
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET_fiqStack \
|
||||
(_WRS_WIND_VARS_OFFSET_archVars+0x28)
|
||||
|
||||
#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
|
||||
|
||||
|
||||
#define _ARM_CPU_ID_MASK #0xF
|
||||
|
||||
#define ARM_WIND_VARS_ALIGN_SHIFT #(_WRS_WIND_VARS_ALIGN_SHIFT)
|
||||
|
||||
/* Using CPU ID, get the index into the CPU's vxKernelVars */
|
||||
/* Note: reading CPU ID requires CPU privileged mode */
|
||||
#define _ARM_CPU_INDEX_GET(r) \
|
||||
MRC p15, 0, r, c0, c0, 5 ; \
|
||||
AND r, r, _ARM_CPU_ID_MASK
|
||||
|
||||
/* place the address of label into register r */
|
||||
#define _ARM_PER_CPU_ADRS_GET(r, scratch, label) \
|
||||
_ARM_CPU_INDEX_GET(r) ; \
|
||||
LDR scratch, L$_vxKernelVars ; \
|
||||
ADD scratch, scratch, r, LSL ARM_WIND_VARS_ALIGN_SHIFT ; \
|
||||
ADD r, scratch, ARM_HASH _ARM_WIND_VARS_OFFSET(label) ; \
|
||||
|
||||
/*
|
||||
* In some configurations (e.g. Thumb-2) there are special restrictions on
|
||||
* usage of the sp register. Also there appears to be a defect in some
|
||||
* versions of the Wind River assembler related to similar use of the lr
|
||||
* register. So use these macros for setting up sp or lr.
|
||||
*/
|
||||
|
||||
#define _ARM_PER_CPU_ADRS_GET_SPLR(r_sp, scratch, label) \
|
||||
_ARM_PER_CPU_ADRS_GET(r_sp, scratch, label)
|
||||
|
||||
/* place the value at label into register r */
|
||||
#define _ARM_PER_CPU_VALUE_GET_SPLR(r_sp, scratch, label) \
|
||||
_ARM_PER_CPU_VALUE_GET(r_sp, scratch, label)
|
||||
|
||||
/* place the value at label into register r */
|
||||
#define _ARM_PER_CPU_VALUE_GET(r,scratch,label) \
|
||||
_ARM_CPU_INDEX_GET(r) ; \
|
||||
LDR scratch, L$_vxKernelVars ; \
|
||||
ADD scratch, scratch, r, LSL ARM_WIND_VARS_ALIGN_SHIFT ; \
|
||||
ADD scratch, scratch, ARM_HASH _ARM_WIND_VARS_OFFSET(label) ; \
|
||||
LDR r, [scratch]
|
||||
|
||||
/* place value at label in rv, also place address at label in ra */
|
||||
#define _ARM_PER_CPU_VALUE_AND_ADRS_GET(rv,ra,label) \
|
||||
_ARM_CPU_INDEX_GET(rv) ; \
|
||||
LDR ra, L$_vxKernelVars ; \
|
||||
ADD ra, ra, rv, LSL ARM_WIND_VARS_ALIGN_SHIFT ; \
|
||||
ADD ra, ra, ARM_HASH _ARM_WIND_VARS_OFFSET(label) ; \
|
||||
LDR rv, [ra]
|
||||
|
||||
/*
|
||||
* ro = register to store kernel lock owner
|
||||
* ri = register to store cpu index
|
||||
*
|
||||
* typedef struct smpLock
|
||||
* {
|
||||
* volatile int state; /@ state of lock (free/taken) @/
|
||||
* volatile int owner; /@ CPU which owns the lock @/
|
||||
* int count; /@ recursive ownership nesting count @/
|
||||
* int options; /@ options applicable to this lock @/
|
||||
*/
|
||||
|
||||
#define _ARM_KERNEL_LOCK_OWNER_AND_INDEX_GET(ro, ri) \
|
||||
_ARM_CPU_INDEX_GET(ri) ; \
|
||||
LDR ro, L$_kernelStateLock ; \
|
||||
ADD ro, ro, ARM_HASH _WRS_KERNEL_LOCK_OFFSET_cpuIndex ; \
|
||||
LDR ro, [ro] /* kernel spin lock owner */ ; \
|
||||
|
||||
|
||||
# else /* _WRS_CONFIG_SMP */
|
||||
|
||||
#define IMM0 #0
|
||||
/* Macro unconditionally returns 0 when built for UP */
|
||||
#define _ARM_CPU_INDEX_GET(r) MOV r, IMM0
|
||||
|
||||
/*
|
||||
* WARNING: UP build assumes that scratch register is not used.
|
||||
* There is only one scratch register available in
|
||||
* excEnterCommon
|
||||
*/
|
||||
|
||||
/* place the address of label into register r */
|
||||
#define _ARM_PER_CPU_ADRS_GET(r, scratch, label) \
|
||||
LDR r, L$_##label
|
||||
|
||||
/* place the value at label into register r */
|
||||
#define _ARM_PER_CPU_VALUE_GET(r, scratch, label) \
|
||||
LDR r, L$_##label ; \
|
||||
LDR r, [r]
|
||||
|
||||
/* place value at label in ra, also place address at label in rv */
|
||||
#define _ARM_PER_CPU_VALUE_AND_ADRS_GET(rv,ra,label) \
|
||||
LDR ra, L$_##label ; \
|
||||
LDR rv, [ra]
|
||||
|
||||
|
||||
/*
|
||||
* In some configurations (e.g. Thumb-2) there are special restrictions on
|
||||
* usage of the sp register. Also there appears to be a defect in some
|
||||
* versions of the Wind River assembler related to similar use of the lr
|
||||
* register. So use these macros for setting up sp or lr.
|
||||
*/
|
||||
|
||||
# if (ARM_THUMB2)
|
||||
/* place the address of label into register r */
|
||||
#define _ARM_PER_CPU_ADRS_GET_SPLR(r_sp, scratch, label) \
|
||||
LDR scratch, L$_##label ; \
|
||||
MOV r_sp, scratch
|
||||
|
||||
/* place the value at label into register r */
|
||||
#define _ARM_PER_CPU_VALUE_GET_SPLR(r_sp, scratch, label) \
|
||||
LDR scratch, L$_##label ; \
|
||||
LDR r_sp, [scratch]
|
||||
|
||||
# else /* (ARM_THUMB2) */
|
||||
/* place the address of label into register r */
|
||||
#define _ARM_PER_CPU_ADRS_GET_SPLR(r_sp, scratch, label) \
|
||||
_ARM_PER_CPU_ADRS_GET(r_sp, scratch, label)
|
||||
|
||||
/* place the value at label into register r */
|
||||
#define _ARM_PER_CPU_VALUE_GET_SPLR(r_sp, scratch, label) \
|
||||
_ARM_PER_CPU_VALUE_GET(r_sp, scratch, label)
|
||||
# endif /* (ARM_THUMB2) */
|
||||
|
||||
# endif /* _WRS_CONFIG_SMP */
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCsmpArmPh */
|
||||
@@ -0,0 +1,75 @@
|
||||
/* vxPortableArchP.h - ARM portable library configuration */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007, 2009-2010, 2013, 2017 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01g,28jul17,swu undef _WRS_PORTABLE_vxCpuPhysIndexGet for armv7-a (VXW6-86373)
|
||||
01f,24apr13,yjw undef _WRS_PORTABLE_schedLib for armv7-m
|
||||
01e,29oct10,j_b undefine _WRS_PORTABLE_vxCpuIdGet
|
||||
01d,08jun09,j_b undef _WRS_PORTABLE_schedLib for uniprocessor
|
||||
01c,11jul07,to undef _WRS_PORTABLE_vxAtomicLib if ldrex/strex are supported
|
||||
01b,06jul07,to undef _WRS_PORTABLE_vxCpuIndexGet
|
||||
01a,04may07,zl created
|
||||
*/
|
||||
|
||||
#ifndef __INCvxPortableArchPh
|
||||
#define __INCvxPortableArchPh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This file is included from <private/vxPortableP.h>. It may undefine
|
||||
* portable library definitions in order to enable architecture specific
|
||||
* implementation of a library or routine.
|
||||
*/
|
||||
|
||||
/* the following can be overridden with PORTABLE */
|
||||
|
||||
#ifndef PORTABLE
|
||||
|
||||
#undef _WRS_PORTABLE_bLib
|
||||
#undef _WRS_PORTABLE_dllLib
|
||||
#undef _WRS_PORTABLE_ffsLib
|
||||
|
||||
#ifdef _WRS_CPU_HAS_CLZ_INSTR
|
||||
# undef _WRS_PORTABLE_ffsTbl
|
||||
#endif
|
||||
|
||||
#ifndef _WRS_CONFIG_SMP
|
||||
# undef _WRS_PORTABLE_schedLib
|
||||
#endif
|
||||
|
||||
#endif /* !PORTABLE */
|
||||
|
||||
/* the following cannot be overridden with PORTABLE */
|
||||
|
||||
#if (CPU == ARMARCH7M)
|
||||
# undef _WRS_PORTABLE_schedLib
|
||||
#endif
|
||||
|
||||
#if (CPU == ARMARCH7)
|
||||
# undef _WRS_PORTABLE_vxCpuPhysIndexGet
|
||||
#endif
|
||||
|
||||
#if (ARM_HAS_LDREX_STREX == TRUE)
|
||||
#undef _WRS_PORTABLE_vxAtomicLib
|
||||
#endif
|
||||
|
||||
#undef _WRS_PORTABLE_vxCpuIdGet
|
||||
#undef _WRS_PORTABLE_vxCpuIndexGet
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxPortableArchPh */
|
||||
@@ -0,0 +1,98 @@
|
||||
/* vxdbgArmLibP.h - private ARM VxDBG library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007-2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use of this
|
||||
* software may be licensed only pursuant to the terms of an applicable Wind
|
||||
* River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01h,24apr12,jdw Update for ARM-M
|
||||
01g,09feb11,rlp Defined VXDBG_INT_LOCK_LEVEL_COMPUTE macro for both UP and
|
||||
SMP (CQ:WIND00253870).
|
||||
01f,29apr10,pad Moved extern C statement after include statements.
|
||||
01e,25feb09,j_b merge ARM SMP support:
|
||||
12nov07,jmp Added support for VxDBG cpu control library.
|
||||
01d,27aug08,jpb Renamed VSB header file
|
||||
01c,24jun08,jpb Added include path for kernel configurations options set in
|
||||
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
|
||||
01b,26oct07,rlp Added the VXDBG_INT_LOCK_LEVEL_COMPUTE macro (CQ:WIND00109321).
|
||||
01a,11oct07,rlp Written
|
||||
*/
|
||||
|
||||
#ifndef __INCvxdbgArmLibPh
|
||||
#define __INCvxdbgArmLibPh
|
||||
|
||||
|
||||
#include <vsbConfig.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This macro returns the <level> parameter modified with the interrupt lock
|
||||
* level defined into the <value> parameter. The <level> parameter must be
|
||||
* previously get with either intCpuLock() or intRegsLock() API.
|
||||
*/
|
||||
#if (CPU == ARMARCH7M)
|
||||
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
|
||||
((level & ~PRIMASK_PM) | (value & PRIMASK_PM))
|
||||
#else /* CPU == ARMARCH7M */
|
||||
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
|
||||
((level & ~I_BIT) | (value & I_BIT))
|
||||
#endif /* CPU == ARMARCH7M */
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
|
||||
/* return TRUE if interrupts are locked in specified register set. */
|
||||
|
||||
#define VXDBG_INT_REGS_IS_LOCKED(pRegs) (((pRegs->cpsr & I_BIT) == \
|
||||
I_BIT) ? TRUE : FALSE)
|
||||
|
||||
/*
|
||||
* _WRS_VXDBG_CPU_CTRL_VARS_ALIGN sets the alignment constraint for
|
||||
* vxdbgCpuCtrlVars array.
|
||||
* The value must be:
|
||||
* a power of two no smaller than sizeof(vxdbgCpuCtrlVars), and
|
||||
* a multiple of the cache line size on every ARM variant that supports SMP.
|
||||
*/
|
||||
|
||||
#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN 128
|
||||
#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN_SHIFT 7
|
||||
#define ARM_VXDBG_CPU_CTRL_VARS_ALIGN_SHIFT \
|
||||
#(_WRS_VXDBG_CPU_CTRL_VARS_ALIGN_SHIFT)
|
||||
|
||||
#ifdef _CPU_CACHE_ALIGN_SIZE
|
||||
/*
|
||||
* Validate _WRS_VXDBG_CPU_CTRL_VARS_ALIGN vs current build's
|
||||
* _CPU_CACHE_ALIGN_SIZE
|
||||
*
|
||||
* If any SMP-enabled variant fails this test, _WRS_VXDBG_CPU_CTRL_VARS_ALIGN
|
||||
* must be increased. Since this limit also applies to any subsequent arch-only
|
||||
* release against the same generic binary release, it may be desirable to
|
||||
* allow for growth.
|
||||
*/
|
||||
|
||||
#if (_CPU_CACHE_ALIGN_SIZE > _WRS_VXDBG_CPU_CTRL_VARS_ALIGN)
|
||||
#error Must increase "_WRS_VXDBG_CPU_CTRL_VARS_ALIGN" to at least _CPU_CACHE_ALIGN_SIZE
|
||||
#endif /* _CPU_CACHE_ALIGN_SIZE > _WRS_VXDBG_CPU_CTRL_VARS_ALIGN */
|
||||
#endif /* _CPU_CACHE_ALIGN_SIZE */
|
||||
|
||||
/* externals */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
extern void intVxdbgCpuRegsGet (void);
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxdbgArmLibPh */
|
||||
@@ -0,0 +1,107 @@
|
||||
/* regsArm.h - ARM registers */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996, 1998, 2003, 2004, 2007, 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01i,09may12,j_b enable ARMARCH7M-specific header usage
|
||||
01h,03may12,j_b revert to remove ARMARCH7M-specific header usage
|
||||
01g,01may12,j_b Update for ARMv7M
|
||||
01f,18jun07,m_h Adding definition for WIND_CPU_STATE
|
||||
01e,25aug04,scm add lrReg alternative name
|
||||
01d,18mar04,scm add usr mode rtp support...
|
||||
01c,07may03,pes PAL conditional compilation cleanup.
|
||||
01b,15apr98,kkk added reg_pc, reg_sp, and reg_fp.
|
||||
01a,08may96,cdp written, based on I86 version
|
||||
*/
|
||||
|
||||
#ifndef __INCregsArmh
|
||||
#define __INCregsArmh
|
||||
|
||||
#if (CPU == ARMARCH7M)
|
||||
|
||||
#include "arch/arm/arm-m/regsArm-m.h"
|
||||
|
||||
#else /* (CPU == ARMARCH7M) */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define GREG_NUM 15 /* has 15 32-bit general registers */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* REG_SET - ARM Register set
|
||||
* Note that the exception stack frame relies on the order of items
|
||||
* in this so don't change this without changing the ESF and the stub
|
||||
* in excALib which creates it.
|
||||
*/
|
||||
|
||||
typedef struct /* REG_SET - ARM register set */
|
||||
{
|
||||
ULONG r[GREG_NUM]; /* general purpose registers 0-14 */
|
||||
INSTR *pc; /* program counter */
|
||||
ULONG cpsr; /* current PSR */
|
||||
ULONG ttbase; /* Trans Table Base */
|
||||
} REG_SET;
|
||||
|
||||
typedef struct wind_cpu_state
|
||||
{
|
||||
REG_SET regs;
|
||||
} WIND_CPU_STATE;
|
||||
|
||||
#define fpReg r[11] /* frame pointer */
|
||||
#define spReg r[13] /* stack pointer */
|
||||
#define lrReg r[14] /* link reg pointer */
|
||||
|
||||
#define reg_pc pc /* program counter */
|
||||
|
||||
#define reg_lr lrReg /* link reg pointer */
|
||||
#define reg_sp spReg /* stack pointer */
|
||||
#define reg_fp fpReg /* frame pointer */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#define ARM_REG_SIZE 4
|
||||
#define REG_SET_G_REG_BASE 0x00 /* data reg's base offset to REG_SET */
|
||||
#define REG_SET_G_REG_OFFSET(n) (REG_SET_G_REG_BASE + (n)*ARM_REG_SIZE)
|
||||
#define REG_SET_PC_OFFSET (REG_SET_G_REG_OFFSET(GREG_NUM))
|
||||
#define REG_SET_CPSR_OFFSET (REG_SET_PC_OFFSET + ARM_REG_SIZE)
|
||||
|
||||
#define REG_SET_TTBASE_OFFSET (REG_SET_CPSR_OFFSET + ARM_REG_SIZE)
|
||||
|
||||
#define PC_OFFSET REG_SET_PC_OFFSET
|
||||
|
||||
/* PAL additions */
|
||||
|
||||
/* moved here from h/private/taskLibP.h */
|
||||
|
||||
#define WIND_TCB_R0 WIND_TCB_REGS
|
||||
#define WIND_TCB_R1 (WIND_TCB_R0+4*1)
|
||||
#define WIND_TCB_R4 (WIND_TCB_R0+4*4)
|
||||
#define WIND_TCB_R5 (WIND_TCB_R0+4*5)
|
||||
#define WIND_TCB_SP (WIND_TCB_R0+4*13)
|
||||
#define WIND_TCB_PC (WIND_TCB_R0+4*15)
|
||||
#define WIND_TCB_CPSR (WIND_TCB_PC+4)
|
||||
|
||||
#define WIND_TCB_TTBASE (WIND_TCB_CPSR+4)
|
||||
|
||||
/* End PAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* (CPU == ARMARCH7M) */
|
||||
|
||||
#endif /* __INCregsArmh */
|
||||
@@ -0,0 +1,26 @@
|
||||
/* sigArmCodes.h - ARM signal facility library header file */
|
||||
|
||||
/* Copyright 1996-1997 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,09may96,cdp created
|
||||
*/
|
||||
|
||||
#ifndef __INCsigArmCodesh
|
||||
#define __INCsigArmCodesh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCsigArmCodesh */
|
||||
@@ -0,0 +1,870 @@
|
||||
/* Aligned for arm - no alignment needed */
|
||||
|
||||
|
||||
/* THIS FILE IS AUTO_GENERATED. PLEASE DO NOT EDIT. */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <vxWorks.h>
|
||||
#include <taskLib.h>
|
||||
#include <rtpLib.h>
|
||||
#include <sdLib.h>
|
||||
#include <shlLib.h>
|
||||
#include <signal.h>
|
||||
#include <socket.h>
|
||||
#include <time.h>
|
||||
#include <setjmp.h>
|
||||
#include <ioLib.h>
|
||||
#include <private/semSysCall.h>
|
||||
#include <private/objLibP.h>
|
||||
#include <private/rtpLibP.h>
|
||||
#include <private/mqPxSysCall.h>
|
||||
#include <private/pxObjSysCall.h>
|
||||
#include <private/semPxSysCall.h>
|
||||
#include <private/taskSysCall.h>
|
||||
#include <private/timerSysCall.h>
|
||||
#include <private/eventSysCall.h>
|
||||
#include <sys/resource.h>
|
||||
#include <sys/types.h>
|
||||
#include <base/b_trace_attr_t.h>
|
||||
#include <base/b_trace_id_t.h>
|
||||
#include <base/b_trace_event_id_t.h>
|
||||
#include <base/b_pthread_t.h>
|
||||
|
||||
struct _exitScArgs
|
||||
{
|
||||
int status;
|
||||
};
|
||||
|
||||
struct _creatScArgs
|
||||
{
|
||||
const char * name;
|
||||
mode_t flag;
|
||||
};
|
||||
|
||||
struct _openScArgs
|
||||
{
|
||||
const char * name;
|
||||
int flags;
|
||||
int mode;
|
||||
};
|
||||
|
||||
struct _closeScArgs
|
||||
{
|
||||
int fd;
|
||||
};
|
||||
|
||||
struct _readScArgs
|
||||
{
|
||||
int fd;
|
||||
void * buffer;
|
||||
size_t maxbytes;
|
||||
};
|
||||
|
||||
struct _writeScArgs
|
||||
{
|
||||
int fd;
|
||||
const void * buffer;
|
||||
size_t nbytes;
|
||||
};
|
||||
|
||||
struct _ioctlScArgs
|
||||
{
|
||||
int fd;
|
||||
int function;
|
||||
_Vx_ioctl_arg_t arg;
|
||||
};
|
||||
|
||||
struct dupScArgs
|
||||
{
|
||||
int fd;
|
||||
};
|
||||
|
||||
struct dup2ScArgs
|
||||
{
|
||||
int fd;
|
||||
int fd2;
|
||||
};
|
||||
|
||||
struct pipeScArgs
|
||||
{
|
||||
int filedes[2];
|
||||
};
|
||||
|
||||
struct removeScArgs
|
||||
{
|
||||
const char * name;
|
||||
};
|
||||
|
||||
struct selectScArgs
|
||||
{
|
||||
int width;
|
||||
fd_set * readFds;
|
||||
fd_set * writeFds;
|
||||
fd_set * excFds;
|
||||
struct timeval * timeout;
|
||||
};
|
||||
|
||||
struct socketScArgs
|
||||
{
|
||||
int domain;
|
||||
int type;
|
||||
int protocol;
|
||||
};
|
||||
|
||||
struct bindScArgs
|
||||
{
|
||||
int s;
|
||||
struct sockaddr * name;
|
||||
int namelen;
|
||||
};
|
||||
|
||||
struct listenScArgs
|
||||
{
|
||||
int s;
|
||||
int backlog;
|
||||
};
|
||||
|
||||
struct acceptScArgs
|
||||
{
|
||||
int s;
|
||||
struct sockaddr * addr;
|
||||
int *addrlen;
|
||||
};
|
||||
|
||||
struct connectScArgs
|
||||
{
|
||||
int s;
|
||||
struct sockaddr * name;
|
||||
int namelen;
|
||||
};
|
||||
|
||||
struct sendtoScArgs
|
||||
{
|
||||
int s;
|
||||
caddr_t buf;
|
||||
int bufLen;
|
||||
int flags;
|
||||
struct sockaddr * to;
|
||||
int tolen;
|
||||
};
|
||||
|
||||
struct sendScArgs
|
||||
{
|
||||
int s;
|
||||
const char * buf;
|
||||
int bufLen;
|
||||
int flags;
|
||||
};
|
||||
|
||||
struct sendmsgScArgs
|
||||
{
|
||||
int s;
|
||||
struct msghdr * mp;
|
||||
int flags;
|
||||
};
|
||||
|
||||
struct recvfromScArgs
|
||||
{
|
||||
int s;
|
||||
char * buf;
|
||||
int bufLen;
|
||||
int flags;
|
||||
struct sockaddr *from;
|
||||
int * pFromLen;
|
||||
};
|
||||
|
||||
struct recvScArgs
|
||||
{
|
||||
int s;
|
||||
char * buf;
|
||||
int bufLen;
|
||||
int flags;
|
||||
};
|
||||
|
||||
struct recvmsgScArgs
|
||||
{
|
||||
int s;
|
||||
struct msghdr * mp;
|
||||
int flags;
|
||||
};
|
||||
|
||||
struct setsockoptScArgs
|
||||
{
|
||||
int s;
|
||||
int level;
|
||||
int optname;
|
||||
char * optval;
|
||||
int optlen;
|
||||
};
|
||||
|
||||
struct getsockoptScArgs
|
||||
{
|
||||
int s;
|
||||
int level;
|
||||
int optname;
|
||||
char * optval;
|
||||
int * optlen;
|
||||
};
|
||||
|
||||
struct getsocknameScArgs
|
||||
{
|
||||
int s;
|
||||
struct sockaddr *name;
|
||||
int * namelen;
|
||||
};
|
||||
|
||||
struct getpeernameScArgs
|
||||
{
|
||||
int s;
|
||||
struct sockaddr *name;
|
||||
int *namelen;
|
||||
};
|
||||
|
||||
struct shutdownScArgs
|
||||
{
|
||||
int s;
|
||||
int how;
|
||||
};
|
||||
|
||||
struct mmapScArgs
|
||||
{
|
||||
void * addr;
|
||||
size_t len;
|
||||
int prot;
|
||||
int flags;
|
||||
int fildes;
|
||||
off64_t off;
|
||||
};
|
||||
|
||||
struct munmapScArgs
|
||||
{
|
||||
void * addr;
|
||||
size_t len;
|
||||
};
|
||||
|
||||
struct mprotectScArgs
|
||||
{
|
||||
void * addr;
|
||||
size_t len;
|
||||
int prot;
|
||||
};
|
||||
|
||||
struct killScArgs
|
||||
{
|
||||
OBJ_HANDLE rtpId;
|
||||
int signo;
|
||||
};
|
||||
|
||||
struct sigpendingScArgs
|
||||
{
|
||||
sigset_t * pSet;
|
||||
};
|
||||
|
||||
struct sigprocmaskScArgs
|
||||
{
|
||||
int how;
|
||||
const sigset_t * pSet;
|
||||
sigset_t * pOset;
|
||||
};
|
||||
|
||||
struct _sigqueueScArgs
|
||||
{
|
||||
OBJ_HANDLE rtpId;
|
||||
int signo;
|
||||
const union sigval * pValue;
|
||||
int sigCode;
|
||||
};
|
||||
|
||||
struct _sigsuspendScArgs
|
||||
{
|
||||
const sigset_t * pSet;
|
||||
};
|
||||
|
||||
struct _sigtimedwaitScArgs
|
||||
{
|
||||
const sigset_t * pSet;
|
||||
struct siginfo * pInfo;
|
||||
const struct timespec * pTime;
|
||||
};
|
||||
|
||||
struct _sigactionScArgs
|
||||
{
|
||||
int signo;
|
||||
const struct sigaction * pAct;
|
||||
struct sigaction * pOact;
|
||||
void * retAddr;
|
||||
};
|
||||
|
||||
struct chdirScArgs
|
||||
{
|
||||
const char * name;
|
||||
};
|
||||
|
||||
struct _getcwdScArgs
|
||||
{
|
||||
char * buffer;
|
||||
int length;
|
||||
};
|
||||
|
||||
struct _waitpidScArgs
|
||||
{
|
||||
OBJ_HANDLE childRtpId;
|
||||
int * pStatus;
|
||||
int options;
|
||||
};
|
||||
|
||||
struct sysctlScArgs
|
||||
{
|
||||
int * pName;
|
||||
u_int nameLen;
|
||||
void * pOld;
|
||||
size_t * pOldLen;
|
||||
void * pNew;
|
||||
size_t newLen;
|
||||
};
|
||||
|
||||
struct _schedPxInfoGetScArgs
|
||||
{
|
||||
BOOL * pTimeSlicingOn;
|
||||
ULONG * pTimeSlicePeriod;
|
||||
};
|
||||
|
||||
struct sigaltstackScArgs
|
||||
{
|
||||
stack_t * ss;
|
||||
stack_t * oss;
|
||||
};
|
||||
|
||||
struct unlinkScArgs
|
||||
{
|
||||
const char * name;
|
||||
};
|
||||
|
||||
struct linkScArgs
|
||||
{
|
||||
const char * name;
|
||||
const char * newname;
|
||||
};
|
||||
|
||||
struct _fsyncScArgs
|
||||
{
|
||||
int fd;
|
||||
};
|
||||
|
||||
struct _fdatasyncScArgs
|
||||
{
|
||||
int fd;
|
||||
};
|
||||
|
||||
struct renameScArgs
|
||||
{
|
||||
const char * oldname;
|
||||
const char * newname;
|
||||
};
|
||||
|
||||
struct fpathconfScArgs
|
||||
{
|
||||
int fd;
|
||||
int name;
|
||||
};
|
||||
|
||||
struct pathconfScArgs
|
||||
{
|
||||
const char * path;
|
||||
int name;
|
||||
};
|
||||
|
||||
struct accessScArgs
|
||||
{
|
||||
const char * path;
|
||||
int amode;
|
||||
};
|
||||
|
||||
struct chmodScArgs
|
||||
{
|
||||
const char * path;
|
||||
mode_t mode;
|
||||
};
|
||||
|
||||
struct pxTraceCreationScArgs
|
||||
{
|
||||
int cmd;
|
||||
pid_t pid;
|
||||
trace_attr_t * attr;
|
||||
int fd;
|
||||
trace_id_t * trid;
|
||||
};
|
||||
|
||||
struct pxTraceCtlScArgs
|
||||
{
|
||||
int cmd;
|
||||
trace_id_t trid;
|
||||
struct trace_event_set_t * filter;
|
||||
int how;
|
||||
pthread_t thread_id;
|
||||
void * pc;
|
||||
void * ptr_out;
|
||||
};
|
||||
|
||||
struct pxTraceEventScArgs
|
||||
{
|
||||
int cmd;
|
||||
int id_in;
|
||||
char * data;
|
||||
size_t data_len;
|
||||
pthread_t thread_id;
|
||||
void * pc;
|
||||
trace_event_id_t * id_out;
|
||||
};
|
||||
|
||||
struct pxTraceEventNameQueryScArgs
|
||||
{
|
||||
int cmd;
|
||||
trace_id_t trid;
|
||||
int id_in1;
|
||||
int id_in2;
|
||||
char * name;
|
||||
trace_event_id_t * id_out;
|
||||
int * unavailable;
|
||||
};
|
||||
|
||||
struct pxTraceLogScArgs
|
||||
{
|
||||
int cmd;
|
||||
trace_id_t trid_in;
|
||||
int fd;
|
||||
trace_id_t *trid_out;
|
||||
};
|
||||
|
||||
struct pxTraceEventGetScArgs
|
||||
{
|
||||
int cmd;
|
||||
trace_id_t trid;
|
||||
size_t num_bytes;
|
||||
struct timespec * timeout;
|
||||
struct posix_trace_event_info * event;
|
||||
void * data;
|
||||
size_t * data_len;
|
||||
int * unavailable;
|
||||
};
|
||||
|
||||
struct eventReceiveScArgs
|
||||
{
|
||||
UINT32 events;
|
||||
UINT32 options;
|
||||
_Vx_ticks_t timeout;
|
||||
UINT32 * pEvtsReceived;
|
||||
};
|
||||
|
||||
struct eventSendScArgs
|
||||
{
|
||||
int taskId;
|
||||
UINT32 events;
|
||||
};
|
||||
|
||||
struct eventCtlScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
VX_EVT_CTL_CMD command;
|
||||
void * pArg;
|
||||
size_t * pArgSize;
|
||||
};
|
||||
|
||||
struct msgQSendScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
char * buffer;
|
||||
size_t nBytes;
|
||||
_Vx_ticks_t timeout;
|
||||
int priority;
|
||||
};
|
||||
|
||||
struct msgQReceiveScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
char * buffer;
|
||||
size_t maxNBytes;
|
||||
_Vx_ticks_t timeout;
|
||||
};
|
||||
|
||||
struct _msgQOpenScArgs
|
||||
{
|
||||
const char * name;
|
||||
size_t maxMsgs;
|
||||
size_t maxMsgLength;
|
||||
int options;
|
||||
int mode;
|
||||
void * context;
|
||||
};
|
||||
|
||||
struct objDeleteScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
int options;
|
||||
};
|
||||
|
||||
struct objInfoGetScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
void * pInfo;
|
||||
size_t * pInfoSize;
|
||||
int level;
|
||||
};
|
||||
|
||||
struct _semTakeScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
_Vx_ticks_t timeout;
|
||||
};
|
||||
|
||||
struct _semGiveScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
};
|
||||
|
||||
struct _semOpenScArgs
|
||||
{
|
||||
const char * name;
|
||||
SEM_TYPE type;
|
||||
int initState;
|
||||
int options;
|
||||
int mode;
|
||||
void * context;
|
||||
};
|
||||
|
||||
struct semCtlScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
VX_SEM_CTL_CMD command;
|
||||
void * pArg;
|
||||
size_t * pArgSize;
|
||||
};
|
||||
|
||||
struct _taskOpenScArgs
|
||||
{
|
||||
struct vx_task_open_sc_args * pArgs;
|
||||
};
|
||||
|
||||
struct taskCtlScArgs
|
||||
{
|
||||
int tid;
|
||||
VX_TASK_CTL_CMD command;
|
||||
void * pArg;
|
||||
size_t * pArgSize;
|
||||
};
|
||||
|
||||
struct taskDelayScArgs
|
||||
{
|
||||
_Vx_ticks_t ticks;
|
||||
};
|
||||
|
||||
struct rtpSpawnScArgs
|
||||
{
|
||||
const char * rtpFileName;
|
||||
const char ** argv;
|
||||
const char ** envp;
|
||||
int priority;
|
||||
size_t uStackSize;
|
||||
int options;
|
||||
int taskOptions;
|
||||
};
|
||||
|
||||
struct rtpInfoGetScArgs
|
||||
{
|
||||
OBJ_HANDLE rtpId;
|
||||
RTP_DESC * rtpStruct;
|
||||
};
|
||||
|
||||
struct taskKillScArgs
|
||||
{
|
||||
OBJ_HANDLE taskHandle;
|
||||
int signo;
|
||||
};
|
||||
|
||||
struct _taskSigqueueScArgs
|
||||
{
|
||||
OBJ_HANDLE taskHandle;
|
||||
int signo;
|
||||
const union sigval * pValue;
|
||||
int sigCode;
|
||||
};
|
||||
|
||||
struct _timer_openScArgs
|
||||
{
|
||||
const char * name;
|
||||
int mode;
|
||||
clockid_t clockId;
|
||||
struct sigevent * evp;
|
||||
void * context;
|
||||
};
|
||||
|
||||
struct timerCtlScArgs
|
||||
{
|
||||
TIMER_CTL_CMD cmdCode;
|
||||
OBJ_HANDLE timerHandle;
|
||||
void * pArgs;
|
||||
size_t pArgSize;
|
||||
};
|
||||
|
||||
struct pxOpenScArgs
|
||||
{
|
||||
PX_OBJ_TYPE type;
|
||||
const char * name;
|
||||
int objOpenMode;
|
||||
void * attr;
|
||||
};
|
||||
|
||||
struct pxCloseScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
};
|
||||
|
||||
struct pxUnlinkScArgs
|
||||
{
|
||||
PX_OBJ_TYPE type;
|
||||
const char * name;
|
||||
};
|
||||
|
||||
struct pxCtlScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
PX_CTL_CMD_CODE cmdCode;
|
||||
void * pArgs;
|
||||
size_t * pArgSize;
|
||||
};
|
||||
|
||||
struct pxMqReceiveScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
char * pMsg;
|
||||
size_t msgLen;
|
||||
unsigned int * pMsgPrio;
|
||||
PX_WAIT_OPTION waitOption;
|
||||
const struct timespec * time_out;
|
||||
};
|
||||
|
||||
struct pxMqSendScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
const char * pMsg;
|
||||
size_t msgLen;
|
||||
unsigned int msgPrio;
|
||||
PX_WAIT_OPTION waitOption;
|
||||
const struct timespec * time_out;
|
||||
};
|
||||
|
||||
struct pxSemWaitScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
PX_WAIT_OPTION waitOption;
|
||||
const struct timespec * time_out;
|
||||
};
|
||||
|
||||
struct pxSemPostScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
};
|
||||
|
||||
struct pipeDevCreateScArgs
|
||||
{
|
||||
const char * name;
|
||||
size_t nMessages;
|
||||
size_t nBytes;
|
||||
};
|
||||
|
||||
struct pipeDevDeleteScArgs
|
||||
{
|
||||
const char * name;
|
||||
BOOL force;
|
||||
};
|
||||
|
||||
struct _sdCreateScArgs
|
||||
{
|
||||
char * name;
|
||||
int options;
|
||||
size_t size;
|
||||
off64_t physAddress;
|
||||
MMU_ATTR attr;
|
||||
void ** pVirtAddress;
|
||||
};
|
||||
|
||||
struct _sdOpenScArgs
|
||||
{
|
||||
char * name;
|
||||
int options;
|
||||
int mode;
|
||||
size_t size;
|
||||
off64_t physAddress;
|
||||
MMU_ATTR attr;
|
||||
void ** pVirtAddress;
|
||||
};
|
||||
|
||||
struct sdDeleteScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
int options;
|
||||
};
|
||||
|
||||
struct sdMapScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
MMU_ATTR attr;
|
||||
int options;
|
||||
};
|
||||
|
||||
struct sdUnmapScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
int options;
|
||||
};
|
||||
|
||||
struct sdProtectScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
MMU_ATTR attr;
|
||||
};
|
||||
|
||||
struct _edrErrorInjectScArgs
|
||||
{
|
||||
int kind;
|
||||
const char *fileName;
|
||||
int lineNumber;
|
||||
REG_SET *regset;
|
||||
void *addr;
|
||||
const char *msg;
|
||||
};
|
||||
|
||||
struct wvEventScArgs
|
||||
{
|
||||
int eventId;
|
||||
const char * pData;
|
||||
unsigned int dataSize;
|
||||
};
|
||||
|
||||
struct rtpVarAddScArgs
|
||||
{
|
||||
void ** pVar;
|
||||
void * value;
|
||||
};
|
||||
|
||||
struct sdInfoGetScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
SD_DESC * pSdStruct;
|
||||
};
|
||||
|
||||
struct _shlOpenScArgs
|
||||
{
|
||||
const char * name;
|
||||
int options;
|
||||
};
|
||||
|
||||
struct _shlUnlockScArgs
|
||||
{
|
||||
SHL_ID shlId;
|
||||
};
|
||||
|
||||
struct _shlCloseScArgs
|
||||
{
|
||||
SHL_ID shlId;
|
||||
};
|
||||
|
||||
struct _shlGetScArgs
|
||||
{
|
||||
SHL_ID shlId;
|
||||
SHLINFO *pInfo;
|
||||
};
|
||||
|
||||
struct _shlPutScArgs
|
||||
{
|
||||
SHL_ID shlId;
|
||||
const SHLINFO *pInfo;
|
||||
};
|
||||
|
||||
struct objUnlinkScArgs
|
||||
{
|
||||
const char * name;
|
||||
enum windObjClassType classType;
|
||||
};
|
||||
|
||||
struct getprlimitScArgs
|
||||
{
|
||||
int idtype;
|
||||
OBJ_HANDLE handle;
|
||||
int resource;
|
||||
struct rlimit *rlp;
|
||||
};
|
||||
|
||||
struct setprlimitScArgs
|
||||
{
|
||||
int idtype;
|
||||
OBJ_HANDLE handle;
|
||||
int resource;
|
||||
struct rlimit *rlp;
|
||||
};
|
||||
|
||||
struct _mctlScArgs
|
||||
{
|
||||
void * addr;
|
||||
size_t len;
|
||||
int function;
|
||||
void * arg;
|
||||
};
|
||||
|
||||
struct _taskOpenWithGuardScArgs
|
||||
{
|
||||
struct vx_task_open_guard_sc_args * pArgs;
|
||||
};
|
||||
|
||||
struct clockCtlScArgs
|
||||
{
|
||||
clockid_t clock_id;
|
||||
CLOCK_CTL_CMD cmdCode;
|
||||
void * pArgStruct;
|
||||
size_t * pArgSize;
|
||||
};
|
||||
|
||||
struct _semRTakeScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
_Vx_ticks_t timeout;
|
||||
};
|
||||
|
||||
struct _semWTakeScArgs
|
||||
{
|
||||
OBJ_HANDLE handle;
|
||||
_Vx_ticks_t timeout;
|
||||
};
|
||||
|
||||
struct _semExchangeScArgs
|
||||
{
|
||||
OBJ_HANDLE giveHandle;
|
||||
OBJ_HANDLE takeHandle;
|
||||
_Vx_ticks_t timeout;
|
||||
};
|
||||
|
||||
struct wvRtpEventScArgs
|
||||
{
|
||||
int eventId;
|
||||
const char * pData;
|
||||
unsigned int dataSize;
|
||||
};
|
||||
|
||||
struct _selectScArgs
|
||||
{
|
||||
int width;
|
||||
fd_set * readFds;
|
||||
fd_set * writeFds;
|
||||
fd_set * excFds;
|
||||
struct timeval * timeout;
|
||||
};
|
||||
|
||||
struct _sigtimedwait2ScArgs
|
||||
{
|
||||
const sigset_t * pSet;
|
||||
struct siginfo * pInfo;
|
||||
const struct timespec * pTime;
|
||||
};
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
@@ -0,0 +1,95 @@
|
||||
/* syscallArm.h - ARM specific System Call Infrastructure header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2003, 2005, 2007 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01g,03dec09,cww Moved ARM specific macros from syscallLibP.h
|
||||
01f,04may07,zl updated portable library build configuration.
|
||||
01e,04mar05,scm _SYSCALL_USER_SP_CHECK break signals alt stack option...
|
||||
01d,23feb05,scm re-assign "spare" to user link reg...
|
||||
01c,19nov03,cjj replaced pStackLimit by pStackEnd in _SYSCALL_USER_SP_CHECK
|
||||
01b,14oct03,scm enhanced, flushed out, and debugging.
|
||||
01a,03oct03,jb written.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This header contains ARM specific definitions and constants used by
|
||||
the System Call Infrastructure library.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INCsyscallArmh
|
||||
#define __INCsyscallArmh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#include <taskLib.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* defines */
|
||||
|
||||
#define SYSCALL_ENTRY_FRAME_SIZE 52
|
||||
|
||||
#define _SYSCALL_USER_SP_CHECK(sp)
|
||||
|
||||
/* typedefs */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
/*
|
||||
* The SYSCALL_ENTRY_STATE structure defines the saved machine state
|
||||
* when the system call trap is taken. This information is architecture
|
||||
* specific, and is used by the system call dispatcher to restart system
|
||||
* calls that have been interrupted by the occurance of signals.
|
||||
* System call restart is achieved by restoring the saved state at the
|
||||
* time of the system call trap, and re-issuing the system call.
|
||||
* Arguments to the system call are saved on the kernel stack, and
|
||||
* the address of that array is passed as an argument to the dispatcher.
|
||||
* The layout of this structure must exactly match the ordering of members
|
||||
* of the system call entry frame in src/arch/arm/syscallALib.s.
|
||||
*/
|
||||
|
||||
typedef struct syscall_entry_state
|
||||
{
|
||||
ULONG args[8]; /* argument list (r0-r3 and sp[0]-sp[3]) */
|
||||
ULONG scn; /* System Call Number (SCN) in r12 */
|
||||
ULONG statusReg; /* saved Status Register (spsr) */
|
||||
INSTR *pc; /* Trap return address (lr) */
|
||||
ULONG *pUStack; /* user-mode stack pointer */
|
||||
ULONG usrLnk; /* user-mode link register */
|
||||
} SYSCALL_ENTRY_STATE;
|
||||
|
||||
|
||||
#define ARM_RTP_STACK_OFFSET 12 /* ARM pushes r2, SCn, and lr onto */
|
||||
/* stack prior to signal handling */
|
||||
#define SYSCALL_USER_SP_GET(tid) (char *) \
|
||||
(((SYSCALL_ENTRY_STATE *) ((((WIND_TCB *)(tid))->pExcStackBase) - \
|
||||
(sizeof(SYSCALL_ENTRY_STATE)+ARM_RTP_STACK_OFFSET)))->pUStack)
|
||||
|
||||
#define SYSCALL_USER_PC_GET(tid) (void *) \
|
||||
(((SYSCALL_ENTRY_STATE *) ((((WIND_TCB *)(tid))->pExcStackBase) - \
|
||||
(sizeof(SYSCALL_ENTRY_STATE)+ARM_RTP_STACK_OFFSET)))->pc)
|
||||
|
||||
#define SYSCALL_USER_SCN_GET(tid) (int) \
|
||||
(((SYSCALL_ENTRY_STATE *) ((((WIND_TCB *)(tid))->pExcStackBase) - \
|
||||
(sizeof(SYSCALL_ENTRY_STATE)+ARM_RTP_STACK_OFFSET)))->scn)
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCsyscallArmh */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user